Huge portion of the design is occupied by memories however memory output switching

activity calculation is not straight forward

2. Complex functionalities: Hard macros
3. Multi-million gates cannot afford to have flat analysis due to cycle time and inherent
limitations of probabilistic approaches. We needed to devise a method to do hierarchical
analysis by modeling sub-blocks and using them as a black box.
We used the timing modeling approach to handle (1), (2), (3).
All standard library components are presently modeled in liberty file. [69] Static timing
analysis tools can generate similar liberty file for blocks after completing the analysis. [25]
This file has following information,
Input pin 2 output pin timing arch
Setup and Hold constraints for the data input and clock input
Output timing with respect to either input pin or related clock
We derive output toggle frequency f(out) as below.
36

In case of input 2 output timing Arch

f(out) = maximum(all controlling input toggle rate)

In case of clock 2 output timing Arch

f(out) = average switching activity of clock domain

Figure 2.4 shows the gate level netlist of a design called simple. Figure 2.5 shows the
timing
arcs which will be extracted by Prime Time a leading industry timing analysis tool. [25]
Timing arc information will be used to compute output toggle rate as explained below.
Figure 2.4 Gate Level