I/O MUX CONTROL REGIESTER A (MCRA REGISTER) (PORT A & B CONTROL)

MCRA15

MCRA14

MCRA13

MCRA12

MCRA11

MCRA10

MCRA9

MCRA8

MCRA7

MCRA6

MCRA5

PORT B (IOPB7 IOPB0)

MCRA4

MCRA3

MCRA2

MCRA1

MCRA0

PORT A (IOPA7 IOPA0)

IOPB7

IOPB6

IOPB5

IOPB4

IOPB3

IOPB2

IOPB1 IOPB0 IOPA7

IOPA6

IOPA5

IOPA4

IOPA3

IOPA2

IOPA1

IOPA0

TCLK
INA

TDIR

T2PWM
T2CMP

T1PWM
T1CMP

PWM6

PWM5

PWM4 PWM3 PWM2 PWM1 CAP3

CAP2

CAP1

XINT1

SCI
RXD

SCI
TXD

I/O MUX CONTROL REGIESTER B (MCRB REGISTER) (PORT C & D CONTROL)

MCRB
15

MCRB
14

MCRB
13

MCRB
12

MCRB
11

MCRB
10

PORT D (IOPD0)

MCRB
9

RESERVED
TMS2

TMS

TD0

TDI

TCK

EMU1

EMU0

MCRB
8

MCRB
7

MCRB
6

MCRB
5

MCRB
4

MCRB
3

MCRB
2

MCRB
1

MCRB
0

IOPD0

IOPC7

IOPC6

IOPC5

IOPC4

IOPC3

IOPC2

IOPC1

IOPC0

XINT2
ADC
SOC

CANRX

CANTX

SPISTE

SPICLK

SPISOMI

SPISIMO

BIO

W/R

MCRC
3

MCRC
2

MCRC
1

MCRC
0

PORT C (IOPC7 IOPC0)

I/O MUX CONTROL REGIESTER C (MCRC REGISTER) (PORT E & F CONTROL)

MCRC
15

MCRC
14

MCRC
13

MCRC
12

MCRC
11

MCRC
10

MCRC
9

MCRC
8

MCRC
7

MCRC
6

PORT F (IOPF5-IOPF0)

MCRC
5

MCRC
4

PORT E (IOPE7 IOPE0)

RESERVED

IOPF5

IOPF4

IOPF3

IOPF2

IOPF1

IOPF0

IOPE7

IOPE6

IOPE5

IOPE4

IOPE3

IOPE2

IOPE1

IOPE0

RESERVED

TCLK
INB

TDIRB

T3PWM
T3CMP

T3PWM
T3CMP

CAP6

CAP5 /
QEP4

CAP4 /
QEP3

PWM12

PWM11

PWM10

PWM9

PWM8

PWM7

CLK
OUT

STATUS AND CONTROL REGISTER 0 (ST0)

15

14
ARP

13

12
OV

11
OVM

10
1

9
INTM

4
DP

8
1

7
1

6
1

5
1

4
XF

3
1

2
1

STATUS AND CONTROL REGISTER 1 (ST1)

15

14
ARB

13

12
CNF

11
T/C

10
SXM

9
C

PM

DATA AND DIRECTION CONTROL REGISTER A (FOR PORT A)

DIRECTION

DATA

15

14

13

12

11

10

A7DIR

A6DIR

A5DIR

A4DIR

A3DIR

A2DIR

A1DIR

A0DIR

IOPA7

IOPA6

IOPA5

IOPA4

IOPA3

IOPA2

IOPA1

IOPA0

CMP2
IOPA7

CMP1
IOPA6

CAP3
IOPA5

CAP2
QEP2
IOPA4

CAP1
QEP1
IOPA3

XINT1
IOPA2

PRIMARY PIN NAME

SCIRXD SCITXD
IOPA1
IOPA0

DATA AND DIRECTION CONTROL REGISTER B (FOR PORT B)

DIRECTION

DATA

15

14

13

12

11

10

B7DIR

B6DIR

B5DIR

B4DIR

B3DIR

B2DIR

B1DIR

B0DIR

PRIMARY PIN NAME

IOPB7

IOPB6

IOPB5

IOPB4

IOPB3

IOPB2

IOPB1

IOPB0

TCLKIN
IOPB7

TDIR
IOPB6

T2CMP T1CMP
IOPB5 IOPB4

CMP6
IOPB3

CMP5
IOPB2

CMP4
IOPB1

CMP3
IOPB0

DATA AND DIRECTION CONTROL REGISTER C (FOR PORT C)

DIRECTION
15

14

13

12

11

DATA
10

C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR IOPC7

PRIMARY PIN NAME

IOPC6

IOPC5

IOPC4

CANRX CANTX
IOPC7 IOPC6

DATA AND DIRECTION CONTROL REGISTER D (FOR PORT D)

3
IOPC3

IOPC2

SPISTE SPICLK SPISOMI SPISIMO

IOPC5
IOPC4
IOPC3
IOPC2

IOPC1 IOPC0
BIO
IOPC1

W/R
IOPC0

DIRECTION
15

14

13

12

DATA

11

10

RESERVED

D0DIR

PRIMARY PIN NAME

RESERVED

IOPD0

RESERVED

XINT2 / ADCSOC / IOPD0

DATA AND DIRECTION CONTROL REGISTER E (FOR PORT E)

DIRECTION

DATA

15

14

13

12

11

10

E7DIR

E6DIR

E5DIR

E4DIR

E3DIR

E2DIR

E1DIR

E0DIR

IOPE7

IOPE6

IOPE5

IOPE4

IOPE3

IOPE2

IOPE1

IOPE0

CAP4
QEP
IOPE7

PWM12
IOPE6

PWM11 PWM10
IOPE5
IOPE4

PWM9
IOPE3

PWM8
IOPE2

PWM7
IOPE1

CLKOUT
IOPE0

PRIMARY PIN NAME

DATA AND DIRECTION CONTROL REGISTER F (FOR PORT F)

DIRECTION
15

14

RE
SER
VED

F6DIR

DATA

13

12

11

10

F5DIR

F4DIR

F3DIR

F2DIR

F1DIR

F0DIR

RE
SER
VED

IOPF6

IOPF5

IOPF4

IOPF3

IOPF2

IOPF1

IOPF0

IOPF6

TCLKIN2
IOPF5

TDIR2
IOPF4

T4PWM
T4CMP
IOPF3

T3PWM
T3CMP
IOPF2

CAP6
IOPF1

CAP5
QEP4
IOPF0

RE
SER
VED

PRIMARY PIN NAME

TIMER CONTROL REGISTER 1(T1 CON REGISTER)

15

14

FREE SOFT

13
RE
SER
VED

12

11

10

TMODE1 TMODE0 TPS2 TPS1 TPS0

RESERVED

TENABLE

TIMER CONTROL REGISTER 2 (T2 CON REGISTER)

TCLKS1 TCLKS0 TCLD1

TCLD0 TECMPR

0
RE
SER
VED

15

14

FREE SOFT

13
RE
SER
VED

12

11

10

TMODE1 TMODE0

TPS2 TPS1 TPS0

T2SWT1

TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0

TECMPR

SELT1PR

TIMER CONTROL REGISTER 3 (T3 CON REGISTER)

15

14

FREE SOFT

13

12

RE
SER
VED

11

10

TMODE1 TMODE0

TPS2 TPS1 TPS0

RESERVED

0
RE
SER
VED

TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0

TECMPR

TECMPR

SELT3PR

TIMER CONTROL REGISTER 4 (T4CON REGISTER)

15

14

FREE SOFT

13
RE
SER
VED

12

11

10

TMODE1 TMODE0 TPS2 TPS1 TPS0 T4SWT3

TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0

GP TIMER CONTROL REGISTER A (GPTCON A)

15

14

RESERVED

T2STAT

13

T1STAT

12

11

RESERVED

10

T2TOADC

T1TOADC

TCOMPOE

RESERVED

T2PIN

T1PIN

GP TIMER CONTROL REGISTER B (GPTCON B)

15

14

13

RESERVED

T4STAT

T3STAT

12

11

RESERVED

10

T4TOADC

T3TOADC

6
TCOMPOE

RESERVED

T4PIN

T3PIN

COMPARE CONTROL REGISTER A (COMCON A)

15

14

13

12

11

10

CENABLE

CLD1

CLD0

SVENABLE

ACTRLD1

ACTRLD0

FCOMPOE

PDPINTA
STATUS

COMPARE CONTROL REGISTER B (COMCON B)

RESERVED

15

14

13

CENABLE

CLD1

12

11

10

PDPINTA
STATUS

CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE

RESERVED

COMPARE ACTION CONTROL REGISTER A (ACTRA)

15

14 13 12

SVRDIR D2 D1 D0

11

10

CMP6
ACT1

CMP6
ACT0

CMP5
ACT1

CMP5
ACT0

CMP4
ACT1

CMP4
ACT0

CMP3
ACT1

CMP3
ACT0

CMP2
ACT1

CMP2 CMP1 CMP1

ACT0 ACT1 ACT0

COMPARE ACTION CONTROL REGISTER B (ACTRB)

15

14 13 12

SVRDIR D2 D1 D0

11

10

CMP12
ACT1

CMP12
ACT0

CMP11
ACT1

CMP11
ACT0

CMP10
ACT1

CMP10
ACT0

CMP9
ACT1

CMP9
ACT0

CMP8
ACT1

CMP8 CMP7 CMP7

ACT0 ACT1 ACT0

DEADBAND TIMER CONTROL REGISTER A(DBTCON A)

15

14

13

12

RESERVED

11

10

DBT3

DBT2

DBT1

DBT0

EDBT3

EDBT2

EDBT1

DBTPS2

DBTPS1

DBTPS0

RESERVED

DEADBAND TIMER CONTROL REGSITER B(DBTCON B)

15

14

13

12

RESERVED

11

10

DBT3

DBT2

DBT1

DBT0

EDBT3

EDBT2

EDBT1

DBTPS2

DBTPS1

DBTPS0

RESERVED

CAPTURE CONTROL REGISTER A(CAPCON A)

15

14

13

12

11

10

CAPRES

CAP12EN

CAP3EN

RESERVED

CAP3TSEL

CAP12TSEL

CAP3TOADC

CAP1EDGE

CAP2EDGE

CAP3EDGE

RESERVED

CAPTURE CONTROL REGISTER B(CAPCON B)

15

14

CAPRES

13

CAP45EN

12

11

10

CAP6EN

RESERVED

CAP6TSEL

CAP45TSEL

CAP6TOADC

CAP4EDGE

CAP5EDGE

CAP6EDGE

RESERVED

CAPTURE FIFO STATUS REGISTER A (CAPFIFO A)

15
14
RESERVED

13
12
CAP3FIFO

11
10
CAP2FIFO

9
8
CAP1FIFO

4
3
RESERVED

CAPTURE FIFO STATUS REGISTER B (CAPFIFO B)

15

14

RESERVED

13

12

11

CAP6FIFO

10

CAP5FIFO

CAP4FIFO

RESERVED

EVA INTERRUPT FLAG REGISTER A

15

14

13

12

11

RESERVED

10
T1OFIN
T
FLAG

8
T1CIN
T
FLAG

T1UFINT
FLAG

7
T1PIN
T
FLAG

RESERVED

CMP3INT CMP2INT CMP1INT PDPINTA

FLAG
FLAG
FLAG
FLAG

EVA INTERRUPT FLAG REGISTER B

15

14

13

12

11

10

RESERVED

EVA INTERRUPT FLAG REGISTER C

3
T2OFIN
T
FLAG

2
T2UFINT
FLAG

1
T2CIN
T
FLAG

0
T2PINT
FLAG

15

14

13

12

11

10

RESERVED

EVA INTERRUPT MASK REGISTER A

15

14

13

12

11

10

(EVAIMRA REGISTER)
9

EVA INTERRUPT MASK REGISTER B

15

14

13

T1OFINT T1UFINT T1CINT

ENABLE ENABLE ENABLE

RESERVED

12

11

10

T1PINT
ENABLE

13

12

11

10

0
PDPINTA
ENABLE

(EVAIMRB REGISTER)

EVA INTERRUPT MASK REGISTER C

14

CMP3INT CMP2INT CMP1INT

ENABLE ENABLE ENABLE

RESERVED

3
2
1
0
T2OFIN
T2UFINT T2CINT
T2PINT
T
ENABLE ENABLE ENABLE
ENABLE

RESERVED

15

2
1
0
CAP3INT CAP2INT CAP1INT
FLAG
FLAG
FLAG

(EVAIMRC REGISTER)
9

2
CAP3INT
ENABLE

RESERVED

1
CAP2INT
ENABLE

0
CAP1INT
ENABLE

EVB INTERRUPT FLAG REGISTER A

15

14

13

12

11

RESERVED

10
T3OFIN
T
FLAG

9
T3UFINT
FLAG

8
T3CIN
T
FLAG

EVB INTERRUPT FLAG REGISTER B

15

14

13

12

11

10

7
T3PIN
T
FLAG
7

RESERVED

3
2
1
0
CMP6INT CMP5INT CMP4INT PDPINTB
FLAG
FLAG
FLAG
FLAG
4

RESERVED

3
T4OFIN
T
FLAG

2
T4UFINT
FLAG

1
T4CIN
T
FLAG

0
T4PINT
FLAG

EVB INTERRUPT FLAG REGISTER C

15

14

13

12

11

10

RESERVED

2
1
0
CAP6INT CAP5INT CAP4INT
FLAG
FLAG
FLAG

EVB INTERRUPT MASK REGISTER A

15

14

13

12

11

10

T3OFIN
T3UFINT T3CINT
T3PINT
T
ENABLE ENABLE ENABLE
ENABLE

RESERVED

RESERVED

CMP6INT CMP5INT CMP4INT PDPINTB

ENABLE ENABLE ENABLE ENABLE

EVB INTERRUPT MASK REGISTER B

15

14

13

12

11

10

T4OFINT T4UFINT T4CINT

ENABLE ENABLE ENABLE

RESERVED

T4PINT
ENABLE

EVB INTERRUPT MASK REGISTER C

15

14

13

12

11

10

CAP6INT CAP5INT CAP4INT

ENABLE ENABLE ENABLE

RESERVED
MAXIMUM CONVERSION CHANNELS REGISTER (MAXCONV)
15

14

13

12

11

10

9 8

RESERVED

MAXCONV2_2

MAXCONV2_1

MAXCONV2_0

MAXCONV1_3

MAXCONV1_2

MAXCONV1_1

MAXCONV1_0

ADC CONTROL REGISTER (ADCTRL1)

15

14

RESERVED

13

RESET SOFT

12

11

10

FREE

ACQPS3

ACQPS2

ACQPS1

ACQPS0

CPS

CONTRUN

INT
PRI

SEQ
CASC

CAL
ENA

BRG
ENA

HI /
LO

STEST
ENA

ADC CONTROL REGISTER (ADCTRL2)

15

14

13

EVB
SOC
SEQ

RST SEQ1
/ STRT
CAL

SOC
SEQ1

12

11

10

SEQ1
BSY

INT ENA
SEQ1
(MODE 1)

INT ENA
SEQ1
(MODE 0)

INT
FLAG
SEQ1

EVA
SOC
SEQ1

EVA
SOC
SEQ1

EXT
SOC
SEQ1

RST
SEQ2

SEQ2
BSY

INT ENA
SEQ2
(MODE 0)

INT ENA
SEQ2
(MODE 0)

INT
FLAG
SEQ2

EVB
SOC
SEQ2

AUTOSEQUENCE STATUS REGISTER (AUTO_SEQ_SR)

15

14

13

12

RESERVED

11

10

SEQ
CNTR3

SEQ
CNTR2

SEQ
CNTR1

SEQ
CNTR0

RESERVED

SEQ2STATE2

SEQ2STATE1

SEQ2STATE0

SEQ1STATE3

SEQ1STATE2

SEQ1STATE1

SEQ1STATE0

ADC INPUT CHANNEL SELECT SEQUENCING CONTROL REGISTER (CHSELSEQn) ( n=1,2,3,4 )

CHSELSEQ1 REGISTER
15

14

13

12

11

CONV03

10

CONV02

CONV01

CONV00

CHSELSEQ2 REGISTER
15

14

13

12

11

CONV07

10

CONV06

CONV05

CONV04

CHSELSEQ3 REGISTER
15

14

13

12

11

CONV11

10

CONV10

CONV09

CONV08

CHSELSEQ4 REGISTER
15

14

13

CONV15

12

11

10

CONV14

CONV13

CONV12

EVENT MANAGER INTERRUPT REGISTERS , DEADBAND TIMER AND GP TIMER CONTROL REGISTERS
ADC REGISTERS CAPTURE UNIT CONTROL REGISTERS SPI & ITS INTERRUPT CONTROL REGISTERS
COMPARE UNIT CONTROL REGISTERS SCI & ITS INTERRUPTS CONTROL REGISTERS
PRIMARY/SECONDARY FUNCTION MULTIPLEXED PIN REGISTERS CAN CONTROL REGISTERS