CMOS Testing-2: - Design and Test - Design For Testability (DFT) - Built-In Self-Test - IDDQ Testing

CMOS Testing-2
Design and test

Design for testability (DFT)
Scan design
Built-in self-test
IDDQ testing
ECE 261
James Morizio
Design and Test Flow: Old View
Test was merely an afterthought
Specification
Design
errors
Design
Random
defects
Fabrication
Synthesis, full-custom
simulation, verification,
test generation
Testing
Pass
Fail
Accept
ECE 261
Reject
James Morizio
Design and Test Flow: New View
Design and test are tightly coupled
Specification
Design
errors
Design for
testability
Design
improvements
Random
defects
Fabrication
Process
improvements
Testing
Diagnosis
Pass
Fail
Accept
ECE 261
Reject
James Morizio
Testing Sequential Circuits

Difficult problem-internal states cannot be directly controlled
and observed
Long test sequences are necessary
Solution: Scan design-simplify to combinational circuit testing
Primary
inputs
(controllable)
State inputs
(not controllable)
ECE 261
Combinational
logic
Registers
James Morizio
Primary
outputs
(observable)
State outputs
(not observable)
Design for Test

Design the chip to increase observability and
controllability
If each register could be observed and controlled, test
problem reduces to testing combinational logic between
registers.
Better yet, logic blocks could enter test mode where they
generate test patterns and report the results automatically.
ECE 261
James Morizio
Scan Design
Make all flip-flops directly controllable and observable by adding
multiplexers
Popular design-for-test (DFT) technique-circuit is now
combinational for testing purposes
Primary
inputs
Combinational
logic
Primary
outputs
Scan out
State inputs
(controllable)
Scan cells
State outputs
(observable)
Scan in
ECE 261
James Morizio
Convert each flip-flop to a scan register
SCAN
Only costs one extra multiplexer
Normal mode: flip-flops behave as usual

Scan mode: flip-flops behave as shift register
CLK
Flop
Scan Design
SI
D
Flop
Flop
Flop
Flop
Flop
Logic
Cloud
Logic
Cloud
Flop
Flop
Flop
Flop
outputs
Flop
inputs
Flop
Contents of flops
can be scanned
out and new
values scanned
in
Flop
scan-in
scanout
ECE 261
James Morizio
Scan Cell Design

Data
0
(Functional)
N/T = 1: Test mode
1
Scan in
(Test data)
D0
N/T = 0: Normal mode

Clock
N/T
D1
D2
D3
Scan
out
Scan
in
N/T
Clock
ECE 261
Q0
Q1
James Morizio
Q2
Q3
8
Scannable Flip-flops
SCAN
(a)
SI
CLK
Flop
SCAN
Q
SI
(b)
SCAN
s
(c)
ECE 261
SI
s
James Morizio
Scan Design
Separate input and output 4-bit scan registers

Test sequence: {01100, 11011}, first 4 bits are for flip-flops
1
0
0110
1101
Test data
Controllable
primary
input
Scan chain/
Scan path
N/T
Combinationalcircuit
circuit
Combinational
Test responses
N/T
ECE 261
James Morizio
10
Steps in Scan Testing

N/T = 1: Scan in test pattern, hold appropriate bit
pattern on controllable primary inputs
N/T = 0: Apply test pattern to combinational circuit
N/T=1: Scan out test responses
Scan provides complete controllability and
observability
Testing time? How many cycles? How to test scan
registers?
ECE 261
James Morizio
11
Normal data
Long Scan Chains
Scan chain
Test data
Test vectors need to be translated to scan format
ECE 261
James Morizio
12
Built-in Self-test
Built-in self-test lets blocks test themselves
Generate pseudo-random inputs to comb. logic
Combine outputs into a syndrome
With high probability, block is fault-free if it produces
the expected syndrome
ECE 261
James Morizio
13
Built-in Self Testing (BIST)

Inputs
Test
Test
generator
generator
(TGC)
(TGC)
0
1
Circuit
under test
Outputs
(CUT)
Response
Response
monitor
monitor
(RM)
(RM)
Error
Control
On-chip test generator and response monitor

ECE 261
James Morizio
14
BIST: Advantages
Lower cost due to elimination of external tester
Sematechs projection: 500 MHz tester (400 pins) will

cost $50M in 2010, 90% of on-chip testing will be done
using BIST
In-system, at-system, high-quality testing

Faster fault detection, ease of diagnosis
Overcomes pin limitations and related interfacing
problems
Reduces maintenance and repair costs at system
level
ECE 261
James Morizio
15
BIST: Issues
Test strategy (random, exhaustive, deterministic)
Circuit partitioning
Test pattern generation
Exhaustive: counters
Random: Linear-feedback shift registers (LFSRs)
Deterministic: ROM, other methods?
Response analysis
Test control and scheduling
ECE 261
James Morizio
16
BIST Logic Circuits
Linear-feedback shift-register (LFSR)
Test patterns
Multiple-input signature register (MISR)
Test responses
Signature
ECE 261
James Morizio
17
BIST Pattern Generation

Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
18
BIST Pattern Generation

ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
19
PRSG
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
20
PRSG
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
010
21
PRSG

ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
010
100
22
PRSG
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
010
100
001
23
PRSG
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
010
100
001
011
24
PRSG
ECE 261
Q[1]
Flop
Q[0]
Flop
Flop
CLK
Q[2]
Step
0
1
2
3
4
5
6
7
James Morizio
Q
111
110
101
010
100
001
011
111 (repeats)
25
BILBO
Built-in Logic Block Observer
Combine scan with PRSG & signature analysis
D[0]
D[1]
D[2]
Q[0]
PRSG
ECE 261
Logic
Cloud
Flop
Flop
SI
Flop
C[0]
C[1]
Q[2] / SO
Q[1]
Signature
Analyzer
James Morizio
MODE
Scan
Test
Reset
Normal
C[1]
0
0
1
1
C[0]
0
1
0
1
26
Boundary Scan
Testing boards is also difficult
Need to verify solder joints are good
Drive a pin to 0, then to 1
Check that all connected pins get the values
Through-hold boards used bed of nails

SMT and BGA boards cannot easily contact pins
Build capability of observing and controlling pins
into each chip to make board test easier
ECE 261
James Morizio
27
Boundary Scan Example

Pac kage Interconnec t
CHIP B
CHIP C
Serial Data Out
CHIP A
CHIP D
IO pad and Boundary Scan

Cell
Serial Data In
ECE 261
James Morizio
28
Boundary Scan Interface

IEEE 1149.1 JTAG standard
Boundary scan is accessed through five pins
TCK:
TMS:
TDI:
TDO:
TRST*:
test clock
test mode select
test data in
test data out
test reset (optional)
Chips with internal scan chains can access the chains

through boundary scan for unified test strategy.
ECE 261
James Morizio
29
BIST in Industry
Early days: AT&T (Lucent) incorporated BIST in
hundreds of commercial chips
Intel: 80386, Pentium, Pentium Pro
Hardware overhead typically 15% of self-tested
portion (around 5% for entire chip, e.g. 6% for the
Pentium Pro)
Regular embedded arrays (RAMs, PLAs) almost
always tested using BIST: DEC Alpha, PowerPC
BIST for irregular logic not so widespread
ECE 261
James Morizio
30
IDDQ Testing
Based on current measurements, not voltage
IDDQ = IDD quiescent
In CMOS technology, quiescent current is very

low
Testing idea: check for faults by detecting current
spikes
Advantage: Massive observability, good for detecting shorts
Disadvantage: slow, leakage current closer to quiescent current for
deep submicron
ECE 261
James Morizio
31

CMOS Testing-2: - Design and Test - Design For Testability (DFT) - Built-In Self-Test - IDDQ Testing

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CMOS Testing-2: - Design and Test - Design For Testability (DFT) - Built-In Self-Test - IDDQ Testing

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CMOS Testing-2

Design and test

Design and Test Flow: Old View

Test was merely an afterthought

Design and Test Flow: New View

Design and test are tightly coupled

Testing Sequential Circuits

Design for Test

Convert each flip-flop to a scan register

Only costs one extra multiplexer

Normal mode: flip-flops behave as usual

Scan Cell Design

N/T = 1: Test mode

N/T = 0: Normal mode

Separate input and output 4-bit scan registers

Steps in Scan Testing

Long Scan Chains

Built-in Self Testing (BIST)

On-chip test generator and response monitor

Sematechs projection: 500 MHz tester (400 pins) will

In-system, at-system, high-quality testing

BIST Logic Circuits

Linear-feedback shift-register (LFSR)

Multiple-input signature register (MISR)

BIST Pattern Generation

BIST Pattern Generation

Linear Feedback Shift Register

Through-hold boards used bed of nails

Boundary Scan Example

Serial Data Out

IO pad and Boundary Scan

Boundary Scan Interface

Boundary scan is accessed through five pins

Chips with internal scan chains can access the chains

In CMOS technology, quiescent current is very

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