MC LC

MC LC.................................................................................................................... 1
PHN CNG CNG VIC.........................................................................................3
NI DUNG TI.....................................................................................................4
1.

Quy trnh thit k ASIC s dng b phn mm ca Synopsys..................4

1.1 Tng quan v cng ngh ASIC..................................................................4
1.2 Quy trnh thit k ASIC..................................................................................5
1.3 B phn mn Synopsys..............................................................................7

2.

Tng quan ti............................................................................................9

3.

S khi ca cc module............................................................................9
3.1 Module digital_clock_top............................................................................9
3.2 Module counter............................................................................................11
3.3Module extract_bits........................................................................................13
3.4 Module LED_7_segs...................................................................................15

4.

RTL Coding..................................................................................................16
4.1 Module Top_DongHoSo..............................................................................16
4.2 Module Counter............................................................................................17
4.3 Module ExtractBits.......................................................................................18
4.4 Module Led7seg............................................................................................19

5.

M phng trn ModelSim...........................................................................20

5.1 Module TestBench.........................................................................................20

6.

Thit k trn Synopsys................................................................................22

6.1 Leda..............................................................................................................22
6.2 VCS_Kim tra chc nng trc khi tng hp...............................................26
6.3 Design Compiler:..........................................................................................28
6.4 VCS_Kim tra sau khi tng hp....................................................................45
6.5 Formality.......................................................................................................46
1

6.6 Primetime trc khi layout............................................................................51

6.7 IC Compiler..................................................................................................56
6.8 VCS_ Kim tra sau khi layout.......................................................................75
6.9 PT_Kim tra sau khi layout...........................................................................76
TNG KT................................................................................................................79

PHN CNG CNG VIC

STT
1
2
3
4
5

H tn
V Ngc Din
Nguyn Vn Hip
ng nh Lm
L Vn Sn
Nguyn Trung Thnh

MSSV
20111327
20111591
20111735
20112066
20112190

Cng vic
Thit k Synopsys
V s khi trn Visio v vit bo co
Thit k trn Synopsys
Code verilog
Code verilog v m phng

NI DUNG TI
1. Quy trnh thit k ASIC s dng b phn mm ca Synopsys
1.1 Tng quan v cng ngh ASIC
ASIC - Application Specific Integrated Circuit: mch thch hp ng dng chuyn bit.
ASIC c xy dng bng vic kt ni cc mch c sn d c xy dgj theo cc
phng php mi v vy ASIC thun tin v d dng hn. Asic l mt mch thch hp
c sn xut cho mt ng dng c trng v thng c kch thc tng nh.
Cng ngh ASIC c s dng rng khp trong cc thit b iu khin t ng
iu khin cc chc nng ca cc phng tin truyn thng, xe c, cc h thng x l,
dy chuyn cng nghip
1.1.1 S lc qu trnh pht trin ca mch thch hp IC
SSI : Small Scale Intergation Mch tch hp c nh ( <10 transistor)
MSI: Medium Scale Integration Mch tch hp c trung bnh (10100
transistors)
LSI: Large Scale Integration Mch tch hp c ln (1001000 transistors)
VLSI: Very Large Scale Integration Mc tch hp c rt ln (103 106
transistors)
1.1.2 Phn loi ASIC

Phn loi ASIC da vo phng php thit k

Full custom ASIC
Full custom ASIC l IC c ch, l mt vi mch c cc t bo lgic (logic cell)
v cc lp mt n c xy dng (c ch ha) theo yu cu ca khch hng.
4

Nhng IC c ch ny thng nhm ti cc ng dng ring bit v do ,

chng ta c th gi mt s IC c ch ny l ASIC c ch. u im ca cc
IC ny l s ti u v din tch v hiu sut lm vic, tuy nhin quy trnh thit
k tn nhiu thi gian, chi ph cao dn n gi thnh sn phm rt t.
Semi Custom ASIC
Semi Custom ASIC l cc IC c thit k da trn cc khi c nh ngha sn.
Semi Custom ASIC c chia thnh cc hng nh sau:
ASIC da trn cc t bo chun (Standard-Cell-Based ASIC): mi t bo l
mt tp hp m t cc chc nng logic, thng s vt l (tr, in cm, in
dung, in tr...) v cc c tnh hnh hc cn thit cho vic to ra mt n ca
mt phn t c bn nh cc cng AND, OR, XOR, MUX, FF...u im: Tit
kim thi gian, gim chi ph sn xut v gim ri ro do s dng t bo chun
c thit k sn v kim tra trc. Nhc im : mt thi gian ch to cc
lp mt n, khng ti u v din tch cng nh hiu sut.
ASIC da trn mng cng lgc (Gate-Array-Based ASIC): ASIC c c
sn bng mng cc cng hoc cc cell ging ht nhau nhng cha tng c
kt ni vi nhau. Cc cell ny c t ti cc v tr c xc nh trc.
Channeled-gate aray ASIC: Cc kt ni v cc mng logic nm trn cng mt
lp, cc kt ni to thnh cc knh nm gia cc mng cng logic.
Channeless-gate aray ASIC: Cc kt ni nm lp trn, cn cc mng logic
nm lp di.
Cc vi mch lp trnh c (PLD: Programmable Logic Devices): PLD: gm
mt mng logic AND/OR lp trnh c c kch thc xc nh. Mch logic
thc hin trong PLD theo dng tng ca tch (sum-of-product). PLD c th
cu hnh hay lp trnh to nn mt b phn ty bin cho cc ng dng
ring bit nn chng cng thuc h ASIC.
c im: logic cell v cc lp mt n khng c ty bin, thit k nhanh gi thnh
r.
Mng cng lgc c th lp trnh c theo trng (FPGA: Field
Programmable Gate Array): Kin trc ca FPGA l kin trc mng cc khi
logic, khi logic, im ny gip FPGA c th cha nhiu hn cc phn t
logic v pht huy ti a kh nng lp trnh ca cc phn t logic v h thng
mch kt ni.

1.2 Quy trnh thit k ASIC

Quy trnh thit k ASIC c chia lm hai phn chnh l front-end v backend. S thit k c miu t trong Hnh 2. Front-end bao gm cc bc khng
5

ph thuc vo cng ngh ch to, l qu trnh kim th thit k v ta c th s dng

nhng d liu ca phn ny cho nhiu cng ngh ch to khc nhau m khng nh
hng n sn phm cui cng. Ngc li, back-end gm cc bc thc hin da trn
cng ngh s dng.

S thit k ASIC
Design specification
Design specification l mt phn quan trng ca lung thit k ASIC.
Trong bc ny,cc c tnh v chc nng ca chip ASIC c nh ngha. K
hoch thit k cng ca ra nh thi gian hon thnh d n, chi ph, din tch
chip .
Da vo yu cu chc nng v yu cu phi chc nng kin trc v vi kin trc
cho tng module ca ASIC c xc nh. Trong qu trnh m phng kin trc, kin
trc ASIC c th thay i nu kt qu m phng cho thy n khng p ng nhng
yu cu v c t.
RTL coding
RTL coding l bc m t thit k di dng m RTL bng mt ngn ng m t
phn cng nh VHDL hoc verilog. M RTL phi m bo c th tng hp c
thnh mch vt l, do vic m ha RTL phi tun theo mt b cc quy tc ph
thuc vo vo kh nng h tr ca nh sn xut phn cng
6

 Logic synthesis
Logic synthesis l bc tng hp mch t code RTL thnh cng logic. Da vo
nhng cell c sn trong tp tin th vin cng ngh, mch cng logic c tng hp
thc hin nhng chc nng nh code RTL m t. Kt qu ca bc Synthesis ny l
cc "net-list" cu trc theo mt tiu chun no .
Logic verification and testing
Logic verification and testing l bc kim tra chc nng ca mch t hp c
t bc trc, so vi yu cu chc nng trong specs. Ngoi ra, bc ny c th bao
gm c vic kim tra timing.
Physical layout
Phn ny thng c m nhim bi chuyn gia trong cc hng sn xut bn
dn. H s dng cc cng c chuyn net-list sang kiu d liu cho layout. Netlist
s tr thnh bn v cch b tr cc transistor, capacitor, resistor,... y phi tun th
nghim ngt mt th gi l Design Rule. Cc lut ny c a ra da vo cc gii
hn ca vic ch to, m bo bn Physical layout c th ch to c.
Layout verification and implementation
Layout verification and implementation l bc kim tra sau layout kim tra
chc nng ca mch so vi mch netlist to ra t cc phn trc. Ngoi ra bc
ny, cc lut ca nh sn xut a ra cng c kim tra.
Fabrication
Fabrication l bc cui cng, l ch tao chip da vo mch layout.
1.3 B phn mn Synopsys
1.3.1 Trnh t cc bc thit k mt ASIC (design flow) trong Synopsys.
Design entry
S dng schematic hoc dng ngn ng m t phn cng nh VHDL,
Verilog, System Verilog.
Logic synthesis
Dng HDL v cng c tng hp logic xy dng netlist l s m t
ca components v kt ni (interconnect) gia chng
System partitioning
Chia h thng ln thnh cc khi thch hp.
Simulation
Kim tra chc nng ca h thng.
Kim tra timing ca h thng m bo p ng c cc yu cu v
thi gian.
Floorplanning
Sp xp cc block trn chip.
Placement
Phn chia v tr ca cc cells trong 1 khi.
7

 Routing
To nn cc kt ni gia cc cells v cc blocks.
Circuit extraction
Tnh ton tr khng v dung khng ca cc interconnect
Post layout simulation
Kim tra kh nng lm vic n nh ca ton b thit k trong trng
hp c thm ti t lp interconnect.
Cc bc thit k 1 - 5: logic.
Cc bc thit k 5 9 : vt l.
1.3.2 Cc phn mm trong b phn mm ca Synopsys.
Synopsys cung cp cc phn mm phc v hu ht cc cng on trong quy
trnh thit k ASIC, tp hp thnh b Synopsys Tools. Cc phn mm trong b
phn mm thit k ASIC ca Synopsys:
Leda
Leda l mt cng c kim tra i km vi mt s lut nh trc kim tra
m Verilog hoc VHDL. Leda kim th c code RTL v netlist, Leda c th
kim tra thit k t u n cui tm nhng li c th dn ti vn trong
cc qu trnh m phng, tng hp mch.
VCS
VCS l chng trnh m phng m phn cng. VCS cho php ngi thit k
phn tch, dch v m phng cc miu t phn cng bng Verilog... u
vo VCS l cc tp HDL (.v, .sv, .vhd . . .), th vin ca nh sn xut IC, tp
cha cc thng s tr (.sdf). u ra VCS l kt qu m phng (file u
ra .txt, .doc; waveform ...).
Design Compiler
Design compiler (DC) l cng c quan trng nht trong b sn phm
tng hp ca Synopsys. Phn mm DC s ti u thit k a ra mt m
hnh logic nh nht v nhanh nht thc hin chc nng a ra.
Yu cu u vo tng hp mch bao gm 3 thnh phn:
RTL Source: Code VHDL hoc Verilog
Contraints: cc thit lp ban u cho u vo
Technology Libraries: Cc th vin cng ngh ca cc nh sn xut
u ra sau khi thc hin phn mm Design Compier:
Gate-level Netlist *.v: file m t mch bng cc phn t logic c bn, u vo
cho VCS.
File *.svf: file thng tin ci t Formality cho vic so snh s ging nhau
u ra
trong Formality
File *.ddc: lu thit k unmapped
File *.sdc: ghi ra script trong Synopsys Design Contraints nh dng .sdc
8

 File *.sdf: ghi ra mt file ch thch Standard Delay Format

Primetime
Primetime l mt cng c phn tch thi gian tnh mc cng cho cc thit k phc
tp, nhiu triu cng. Primetime c tch hp vo trong qu trnh tng hp
vt l ca Synopsys v n s dng nhiu th vin, c s d liu v cc cu lnh
ging nh cc cng c khc ca Synopsys nh Design Compiler. u vo ca
Primetime l cc file u ra sau khi tng hp (netlist, .sdf, .sdc) v Th vin cng
ngh. u ra ca Primetime l cc thng tin v tr v d liu in dung k sinh.
IC Compiler
L cng c thc hin tng hp mc vt l, bao gm layout (thc hin vic sp xp
v
ti u v tr cc khi, ni dy, b tr ng i ca xung clock) v gii nn RC. IC
Compiler cho php ngi thit k lm vic c hiu qu cao khi thit k cc khi phc
tp. u vo: netlist (.v) hoc file .ddc, .sdc. u ra: netlist (.v), .sdc,
Formality
Formality l phn mn pht hin ra s khc bit khng mong mun c th xy
ra
trong qu trnh trin khai thit k. Formality thc hin kim chng hnh thc
xem xt s tng ng gia hai thit k v a ra cc phn tch chi tit v bt c s
sai khc no gia chng. u vo : 2 file HDL cn kim chng, file .svf. u ra: kt
qu so snh 2 file HDL.
2. Tng quan ti
Ti liu m t phng thc hot ng ca khi ng h s n gin, da vo
tn hiu iu khin ca sn dng xung nhp thc hin cc b m gi, pht, giy
ng vi chu k iu khin l 1s v a tn hiu hin th ln LED 7 thanh. Module gm
c 3 u vo: clk, en, rst v 6 u ra 7 bit gip cho vic hin th ln 6 LED 7 thanh.
Tn hiu clk l tn hiu clk chnh cho module. Vi mi sn ln ca xung clk, sau mt
chu k Tclk, gi tr u ra s c hin th. Tn hiu rst gip cho module khi to li
gi tr ban u ca cc thanh ghi d liu cha bn trong module. rst l tn hiu tch cc
mc thp. Tn hiu en cho php tn hiu c hin th trn LED 7 thanh hay khng. en
l tn hiu tch cc mc cao.
3. S khi ca cc module.
3.1 Module digital_clock_top
3.1.1 S khi.

S khi ca IC ng h s
3.1.1.1 Chc nng.
Module digital_clock_top ng vai tr l top module trong khi thit k. Trong
module khi to mu cc module lin quan, thc hin kt ni tn hiu gia cc mu
ny.
3.1.1.2 u vo v u ra.
Tn chn
I/ S Reg
Nhim v
O bit
clk

en

rst

tens_hour_o

units_hour_o

tens_min_o

units_min_o

tens_sec_o

units_sec_o

Sn ln ca tn hiu l iu kin thc hin lnh

trong mch tun t.
Tn hiu cho php hoc khng cho php hin th
March 20, 2015 [THIT K NG H S N
GIN]ICDESIGN LAB 5 kt qu ln LED 7
thanh.
Tn hiu thit lp li cc gi tr gi, pht, giy ban
u ca ng h.
biu din tn hiu hng chc ca gi trn LED 7
thanh.
biu din tn hiu hng n v ca gi trn LED 7
thanh.
biu din tn hiu hng chc ca pht trn LED 7
thanh.
biu din tn hiu hng n v ca pht trn LED 7
thanh.
biu din tn hiu hng chc ca giy trn LED 7
thanh.
biu din tn hiu hng n v ca giy trn LED 7
10

thanh.
3.1.1.3 S ni dy bn trong.

S ni dy trong khi digital_clock_top

3.2 Module counter
3.2.1 S khi.

S khi module counter

11

3.2.2 Chc nng.

Module counter thc hin tng gi tr counter_o thm 1 mi khi xut hin sn
dng ca xung iu khin clk. Khi gi tr ca counter bng gi tr ca set_number,
counter_o c gn tr v bng 0.C flag_o dng thc hin to tn hiu xung cho
cc module counter khc. Khi gi tr counter_o tr v 0, c flag_o c gn gi tr 1,
cc trng hp khc, c flag bng 0.ng vi cc tn hiu u vo, sau mt chu k
xut hin tn hiu u ra.
3.2.3 u vo, u ra, v cc tn hiu bn trong.
Tn chn

I/O

clk

S
bit
1

rst

Re
g

set_number I
counter_o
O

6
6

flag_o

Nhim v
Sn ln ca tn hiu l iu kin thc hin lnh
trong khi counter.
Tn hiu thit lp li cc gi tr gi, pht, giy ban
u ca ng h.
Gi tr gii hn cho b m
Gi tr m c a ra ngoi, bng gi tr
counter_r khi en = 1b1, unknown khi en = 1b0.
C bo lm tn hiu iu khin thay tn hiu clk
cho cc module counter khc.

3.2.4 S thut ton.

S thut ton khi module counter

12

3.3Module extract_bits.
3.3.1 S khi.

S khi module extract_bits

3.3.2 Chc nng.
Module extract_bits thc hin bin i gi tr ca 6 bt u vo thnh 4 bt gi
tr hng chc v 4 bt gi tr hng n v. Module l mch t hp. Module s a ngay
kt qu u ra khi gi tr u vo thay i. Module gm tn hiu 6 bit u vo
number_i v hai tn hiu 4 bit u ra tens_o v units_o.
3.3.3 u ra v u vo.
Tn chn
number_i
tens_o
units_o

I/O
I
O
O

S bit
6
4
4

Nhim v
Gi tr a vo cn chuyn i
Gi tr hng chc ca s a vo
Gi tr hng n v ca s a vo.

3.3.4 S thut ton.

13

S thut ton khi module extract_bits

3.3.5 S khi bn trong
14

S khi bn trong ca module extract_bits

3.4 Module LED_7_segs.
3.4.1 S khi.

S khi module LED_7_segs

3.4.2 Chc nng.
Module LED_7_segs thc hin chc nng chuyn i s nh phn 4 bit sang
7bit hin th ln Led 7 thanh. Module s a tn hiu ra ngay khi tn hiu 4 bit u
vo thay i. Module c hai u vo: en v 4 bit input_i, mt u ra 7 bit output_o.
Khi tn hiu en = 1b1, 7 bit output_o s biu din gi tr s hc ca 4 bit u vo
input_4 hin th ln LED 7 thanh. Nu en = 1b0, gi tr ca tn hiu output_o s
c gn bng 7b0000000.
3.4.3 u vo u ra.
Tn chn

I/O

S
Reg Nhim v
bit
en
I
1
Cho php tn hiu u ra hin th kt qu trn LED.
input_i
I
4
Gi tr cn hin th
output_o O
7
R
Biu din ca u vo trn LED 7 thanh
3.4.4 Bng gi tr u vo u ra.

15

En
1b0
1b1
1b1
1b1
1b1
1b1
1b1
1b1
1b1
1b1
1b1

u vo
4bxxxx
4b0000
4b0001
4b0010
4b0011
4b0100
4b0101
4b0110
4b0111
4b1000
4b1001

u ra
7b0000000
7b1111110
7b1111110
7b1101101
7b1111001
7b0110011
7b1011011
7b1011111
7b1110000
7b1111111
7b1111011

Hin th
0
1
2
3
4
5
6
7
8
9

4. RTL Coding
4.1 Module Top_DongHoSo
module DongHoSo(tens_hour_o, units_hour_o, tens_min_o, units_min_o,
tens_sec_o, units_sec_o, clk, en, rst );
input clk, en, rst;
output [6:0] tens_hour_o, units_hour_o, tens_min_o, units_min_o,
tens_sec_o, units_sec_o;

parameter set_number_s=6'd59, set_number_p=6'd59, set_number_h=6'd23;

wire [5:0] second_w, minute_w, hour_w;

wire [3:0] tens_sec_w ,units_sec_w, tens_min_w, units_min_w, tens_hour_w,
units_hour_w;
wire minute_clk_w, hour_clk_w, day_clk_w;

counter Second(.clk(clk), .rst(rst),

.set_number(set_number_s),.counter_o(second_w),.flag_o(minute_clk_w));
counter Minute(.clk(minute_clk_w), .rst(rst), .set_number(set_number_p),
.counter_o(minute_w), .flag_o(hour_clk_w));
counter Hour(.clk(hour_clk_w),.rst(rst), .set_number(set_number_h),
.counter_o(hour_w), .flag_o(day_clk_w));

16

extractBits S(.number_i(second_w), .tens_o(tens_sec_w),

.units_o(units_sec_w));
extractBits M(.number_i(minute_w), .tens_o(tens_min_w),
.units_o(units_min_w));
extractBits H(.number_i(hour_w), .tens_o(tens_hour_w),
.units_o(units_hour_w));

led7seg S1(.en(en), .input_i(tens_sec_w), .output_o(tens_sec_o));

led7seg S2(.en(en), .input_i(units_sec_w), .output_o(units_sec_o));
led7seg M1(.en(en), .input_i(tens_min_w), .output_o(tens_min_o));
led7seg M2(.en(en), .input_i(units_min_w), .output_o(units_min_o));
led7seg H1(.en(en), .input_i(tens_hour_w), .output_o(tens_hour_o));
led7seg H2(.en(en), .input_i(units_hour_w), .output_o(units_hour_o));
endmodule

4.2 Module Counter

module counter(counter_o, flag_o, clk, rst, set_number);
input clk, rst;
input [5:0]set_number;
output [5:0] counter_o;
output flag_o;
reg [5:0] counter_o;
reg flag_o;

always @(posedge clk or negedge rst)

if (rst == 1'b0)
begin
counter_o <=6'd0;
flag_o <=1'b0;
end
else
if(counter_o == set_number)

17

begin
counter_o <= 6'd0;
flag_o <= 1'b1;
end
else
begin
counter_o <= counter_o + 1;
flag_o <= 1'b0;
end
endmodule

4.3 Module ExtractBits

module extractBits (tens_o, units_o, number_i );
input [5:0] number_i;
output [3:0] tens_o;
output [3:0] units_o;
reg [3:0] tens_o;
reg [3:0] units_o;

reg[3:0]

d1, d2, d3, c1, c2, c3;

always @(number_i)
begin
d1={1'b0,number_i[5:3]};
if(d1>4'd4) c1 = d1 + 2'd3;
else c1 = d1;
d2={c1[2:0],number_i[2]};
if(d2>4'd4) c2 = d2 + 2'd3;
else c2 = d2;
d3={c2[2:0],number_i[1]};

18

if(d3>4'd4) c3 = d3 + 2'd3;
else c3 = d3;
if(number_i== 6'b111111)
begin
tens_o = 4'b1111;
units_o = 4'b1111;
end
else
begin
tens_o = {1'b0, c1[3], c2[3], c3[3]};
units_o = {c3[2:0], number_i[0]};
end
end
endmodule

4.4 Module Led7seg

module led7seg(output_o,input_i, en);
input [3:0]input_i;
input en;
output reg [6:0]output_o;
always @(en or input_i)
begin
if(en) begin
if(input_i == 0)
output_o = 7'b1111110;
else if(input_i == 1)
output_o = 7'b0110000;
else if(input_i == 2)
output_o = 7'b1101101;
else if(input_i == 3)

19

output_o = 7'b1111001;
else if(input_i == 4)
output_o = 7'b0110011;
else if(input_i == 5)
output_o = 7'b1011011;
else if(input_i == 6)
output_o = 7'b1011111;
else if(input_i == 7)
output_o = 7'b1110000;
else if(input_i == 8)
output_o = 7'b1111111;
else if(input_i == 9)
output_o = 7'b1111011;
else output_o = 7'b1111110;end
else output_o = 7'b0000000;
end
endmodule

5. M phng trn ModelSim

5.1 Module TestBench
` module tb_digital_clock();
reg

rst;

reg

clk;

reg

en;

wire

[6:0] hour_led_tens;

wire

[6:0] hour_led_unit;

wire

[6:0] min_led_tens;

wire

[6:0] min_led_unit;

20

wire

[6:0] sec_led_tens;

wire

[6:0] sec_led_unit;

DongHoSo test(
.rst(rst),
.en(en),
.clk(clk),
.tens_hour_o(hour_led_tens),
.units_hour_o(hour_led_unit),
.tens_min_o(min_led_tens),
.units_min_o(min_led_unit),
.tens_sec_o(sec_led_tens),
.units_sec_o(sec_led_unit)

);
initial begin
#1

rst = 0; en = 0;

#1

rst = 1; en = 1;

//#1000000000

$finish;

end

initial begin
clk=1;
forever #5 clk = ~clk;
end

endmodule

21

6. Thit k trn Synopsys

6.1 Leda
- To th mc rtl cha code Verilog ca thit k v th mc leda trong
project. M ca s terminal, chn ng dn n th mc leda, ri g lnh
leda, ca s giao din phn mm hin ra:
-

Chn New project OK

Hnh 1 To project mi bng leda

-

Sau khi ca s hin ra trong mc Project Name c th thay tn project c ui

m rng l .pro, sau chn next.

Hnh 2 t tn cho project

Sau khi ca s mi hin ra, trong mc Verision chn 2001 (verilog 2001):
22

Hnh 3 Chn ngn ng miu t phn cng v phin bn

-

Chn Next. Ca s tip theo hin ra

Hnh 4 Thm file vo project

23

Chn Add ri chn ng dn n th mc cha code verilog. Chn OK

chn Next ca s tip theo chn Finish.

Hnh 5 To xong project

-

Vo Check chn Load Configuration ri chon RTL. Chn biu tng !

xut hin ca s:

Hnh 6 Cu hnh chn reset v enable

-

Sau khi xut hin ca s vo mc Test clock/reset thit lp clock v reset ri

chn OK.
24

Ca s mi s hin th cc trng thi kim tra nh sau:

Hnh 7 Check li
-

Nu ca s hin th trng thi cc mu xanh th code c kim tra ng

Nu hin th cc mu nu bo cc cnh bo nn c qua v c th iu chnh.

Nu hin th cc mu phi c chi tit cc cnh bo vo sa li code tun

theo cc lut mnh chn.

Sau khi sa code chy li kim tra mt ln na cho n khi no trn ca s khng
xut hin mu na.

25

6.2 VCS_Kim tra chc nng trc khi tng hp.

- To th mc vcs trong project. Trong th mc vcs to th mc
pre_syn cha cc file sinh ra trong qu trnh m phng code RTL
trc khi tng hp bng design compiler. Copy cc file .v t th mc rtl
vo th mc pre_syn.
- Vo th mc pre_syn m ca s lnh Terminal g lnh sau:
vcs -debug +v2k *.v

Hnh 8 Khi ng vcs

-

Sau khi phn tch cc file .v xong n s to ra mt file simv trong th

mc pre_syn. tip tc vo terminal g lnh sau thc hin m phng
chc nng:
./simv gui

26

Hnh 9 Start gui VCS

-

Sau khi ca s hin ra chn file testbench click chut phi vo chn Add
to Wave ri chn New Wave view. Ca s mi hin ra bm F5 hoc
chn run (mi tn c chiu hng xung di) s xut hin ra timing cn
kim tra.

Kt qu:

Hnh 10 Kt qu m phng
-

Da vo kt qu hin th trn waveform chng ta c th kt lun rng code

Rtl tha mn cc yu cu chc nng ca specification.

27

6.3 Design Compiler:

- To th mc dc trong project, vo terminal g lnh:
design_vision
-

Giao din ngi dng hin ln:

Hnh 11 Khi ng DC

Hnh 12 Mn hnh khi ng Design Compiler

28

 Bc 1: Ci t th vin
File Setup

Hnh 13 Ci t th vin
-

Search path : chn ng dn n th vin milkyway :

/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gs
bwp/LM/

Link library : ng dn n th vin bao gm 2 th vin Synthetic library v

Target library

Target library: th vin cng ngh ca nh sn xut

/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gs
bwp/LM/tcbn45gsbwpbc.db

Symbol library : th vin k hiu c sn trong th mc ci t ca synopsys

/opt/synopsys/dc/libraries/syn/generic.sdb

Synthetic library : th vin tng hp c sn trong th vin ca synopsys

29

/opt/synopsys/dc/libraries/syn/dw_foundation.sldb

Bc 2 : To file theo di qu trnh c ui m rng .svf.

-

Vo terminal g lnh
set_svf top.svf

Bc 3: c file *.v
File Read
c tt c cc file verilog trong th mc rtl tr cc file testbench.

Hnh 14 c file thit k

Bc 4 : Analyze
File Analyze

30

Hnh 15 Analyze

Bc 5: Elaborate
File Elaborate
Trong mc Design chn file top module

Hnh 16 Elaborate

Bc 6: Kim tra thit k

Design Check Design OK
31

Bc ny s kim tra thit k. Trn ca s terminal s c cc cnh bo nn c

k.

Hnh 17 Check Design

Bc 7: Set clock constraints

-

Chn vo biu tng

trn thanh menu s hin ln schematic. S dng I
(zoom in) v O (zoom out) phng to hoc thu nh s , dng ln chut v
shift hoc ctrl ln xung hoc sang ngang.

Chn vo tn hiu clk trong s :

32

Hnh 18 Chn tn hiu clock set Constraints

-

Sau khi chn tn hiu clk vo Atributes trn thanh Menu chn Specify
Clock

Ta c cc thit lp sau:
create_clock -name "clk" -period 1000000000 -waveform { 0 500000000 } { clk }

Trong mc Clock name t tn l clk.

Trong mc Period : 1000000000 (ns)(do chu k thc hin ca ng h s l

1s ).

Trong mc rising: 0 (ti 0 th xut hin sng ln ca xung nhp).

Trong mc falling: 500000000 ns (ti 0.5 s th xut hin sn xung ca xung

nhp).

Chn Don't touch network : trong qu trnh tng hp th tn hiu clock c

bo v.

Chn Fix hold : khc phc cc li hold time sau khi tng hp.

Ngoi ra cn c cc rng buc khc bng cch s dng cu lnh nh:

- set_clock_uncertainty 10000000 [get_clocks clk] // thit lp lch gia 2 FF k
tip nhau.
33

set_clock_latency 200000000 [get_clocks clk] // thit lp tr ca xung clock

t b to dao ng n FF.

set_input_transition 100000000 [all_inputs] // thit lp tr chuyn trng thi

ca lock ( dc ca sn clock).

Bc 8: Thit lp cc rng buc thit k (constrain)

Tr u vo: Chn cc tn hiu u vo trn s (tr tn hiu clock)
Trn thanh Menu vo Atributes chn Operating Environment Input delay

Hnh 19 Xt constraints cho input

Tr u ra : Chn cc tn hiu ra trn s
Trn thanh Menu vo Atributes chn Operating Environment Output delay

34

Hnh 20 Xt constraints cho output

iu kin hot ng (Operating condition)
Trn thanh Menu vo Atributes chn Operating Environment Operating
conditions

Hnh 21 Xt iu kin hot ng

Wire load:
Trn thanh Menu vo Atributes chn Operating Environment Wire load

35

Hnh 22 Wire Load

Thit lp in tr, in dung u vo, u ra cho IC:
Khi cc cng kch thch u vo v ti u ra cha bit th ta dng Load Budget,
xc nh d phng cho thit k.
Gi s cc u vo c kch thch bng cell yu nht
set
all_in_ex_clk
[remove_from_collection
[all_inputs]
[get_ports clk]]
set_driving_cell
-no_design_rule
-lib_cell
INVD0BWP
$all_in_ex_clk
t in dung u vo ln nht l 10 cell AN2D0BWP
set
MAX_INPUT_LOAD
[expr
[load_of
tcbn45gsbwpbc/AN2D0BWP/A1] * 10]
set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk
t in dung u ra ln nht l 3 khi 10 cell
set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]
Hnh v:

Design constraints
Trn thanh Menu vo Atributes chn Operating Environment Design constraints
36

Hnh 23 Xt kch thc ti a

-

C th thit lp thm cc rng buc v cng sut ng, cng sut dng r, Max
fanout, maxtransition.
Bc 9 : Compile Design
- Trn thanh Menu vo Design Compile Design OK
Ngoi ra bn c thm cc la chn sao cho sau qu trnh tng hp thit k ca
mnh ti u nht.

Hnh 24 Compile

37

Hnh 25 Kt qu sau Compile Design

Bc 10: Compile Ultra

- Sau qu trnh tng hp thit k, bc ny s va tng hp va ti u ha thit
k nhng cng no tha hoc khng cn thit trong qu trnh tng hp s b
xa.
- Trn thanh Menu vo Design Compile Ultra OK
-

Sau qu trnh tng hp khi xem li s mch s tr nn phc tp hn rt

nhiu:

Hnh 26 Kt qu sau Compile ultra

38

C th thy rng sau khi compile ultra th mch hon ton l cc standard cell
ni vi nhau => c th xut ra file netlist.

Bc 11 : To file .ddc
- File .ddc c s dng cho phn mm ICC layout v kim tra chc nng
trong Primetime
File Save as

Hnh 27 To file *.ddc

Bc 12 : To file Netlist
- File Netlist l file m t mc cng ca thit k bao gm cc cell c bn (AND,
OR, MUX, FF) c ni dy vi nhau.
File Save as

Hnh 28 To file netlish dng cho formality

39

 Bc 13 : To file .sdf
-

File .sdf l file nh ngha tr tng cng, dy dn..

Vo terminal g lnh sau:

write_sdf top.sdf

Bc 14 : To file .sdc
-

File .sdc (synopsys design constraints) c s dng trong ICC a cc

rng buc thit k ca mnh vo thc hin layout.

Vo Terminal g lnh sau:

write_sdc top.sdc

Bc 15 : Xut bo co
-

Sau khi tng hp kim tra xem thit k ca mnh c p ng c cc yu

cu v timing, cng sut, din tch,.. hay khng cn phi xem qua cc bo co
m phn mm t ng to ra cho mnh. C mt s bo co in hnh nh
sau:

Report_timing : Timing Report Timing Path

Hnh 29 Xut Report Timing Path

40

Report_constraints: Design Report Constraints

Hnh 30 Xut Report Constraints

-

Report_power : Design Report Power

Hnh 31 Xut Report Power

41

Report_Resource : Design Report resource

Hnh 32 Xut Report resource

Max time

Hnh 33 Report Timing

42

 Min time

Hnh 34 Report Timing

Bc 16 : Tt file theo di
-

Vo terminal g cu lnh:
set_svf off

File .svf c s dng trong qu trnh kim tra Formality.

Thit lp cho Design Compiler:

set_svf top.svf
read_file
-format
verilog
{/home/lab/VLSI10/rtl/DongHoSo.v
/home/lab/VLSI10/rtl/counter.v
/home/lab/VLSI10/rtl/extractBits.v
/home/lab/VLSI10/rtl/led7seg.v}
analyze
-format
verilog
{/home/lab/VLSI10/rtl/led7seg.v
/home/lab/VLSI10/rtl/extractBits.v
/home/lab/VLSI10/rtl/counter.v
/home/lab/VLSI10/rtl/DongHoSo.v}
elaborate DongHoSo -architecture verilog -library WORK
uplevel #0 check_design
change_selection [get_s clk]
create_clock -name "clk" -period 1000000000 -waveform { 0 500000000 } { clk }
change_selection [get_s en]
change_selection -add [get_s rst]
set_input_delay -clock clk -add_delay -max -rise 200000000 "rst en"
set_input_delay -clock clk -add_delay -max -fall 200000000 "rst en"

43

set_input_delay -clock clk -add_delay -min -rise 100000000 "rst en"

set_input_delay -clock clk -add_delay -min -fall 100000000 "rst en"
change_selection [get_s {{tens_hour_o[6:0]} {tens_hour_o[6]} {tens_hour_o[5]}
{tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]}}]
change_selection -add [get_s {{tens_hour_o[0]}}]
change_selection -add [get_s {{tens_min_o[6:0]} {tens_min_o[6]} {tens_min_o[5]}
{tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}}]
change_selection -add [get_s {{tens_min_o[0]}}]
change_selection -add [get_s {{tens_sec_o[6:0]} {tens_sec_o[6]} {tens_sec_o[5]}
{tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]}}]
change_selection -add [get_s {{tens_sec_o[0]}}]
change_selection
-add
[get_s
{{units_hour_o[6:0]}
{units_hour_o[6]}
{units_hour_o[5]}
{units_hour_o[4]}
{units_hour_o[3]}
{units_hour_o[2]}
{units_hour_o[1]}}]
change_selection -add [get_s {{units_hour_o[0]}}]
change_selection
-add
[get_s
{{units_min_o[6:0]}
{units_min_o[6]}
{units_min_o[5]}
{units_min_o[4]}
{units_min_o[3]}
{units_min_o[2]}
{units_min_o[1]}}]
change_selection -add [get_s {{units_min_o[0]}}]
change_selection -add [get_s {{units_sec_o[6:0]} {units_sec_o[6]} {units_sec_o[5]}
{units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]}}]
change_selection -add [get_s {{units_sec_o[0]}}]
set_output_delay -clock clk -add_delay -max -rise 200000000 "{tens_min_o[6]}
{tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}
{tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]}
{tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]}
{units_min_o[4]}
{units_min_o[3]}
{units_min_o[2]}
{units_min_o[1]}
{units_min_o[0]}
{tens_hour_o[6]}
{tens_hour_o[5]}
{tens_hour_o[4]}
{tens_hour_o[3]}
{tens_hour_o[2]}
{tens_hour_o[1]}
{tens_hour_o[0]}
{units_sec_o[6]}
{units_sec_o[5]}
{units_sec_o[4]}
{units_sec_o[3]}
{units_sec_o[2]}
{units_sec_o[1]}
{units_sec_o[0]}
{units_hour_o[6]}
{units_hour_o[5]}
{units_hour_o[4]}
{units_hour_o[3]}
{units_hour_o[2]}
{units_hour_o[1]}
{units_hour_o[0]}
{units_sec_o[6]}
{tens_hour_o[2]}
{tens_sec_o[5]}
{units_min_o[4]}
{units_hour_o[3]}
{tens_min_o[3]}
{tens_hour_o[6]}
{units_sec_o[3]}
{tens_sec_o[2]}
{units_min_o[1]}
{units_hour_o[0]}
{tens_min_o[0]}
{tens_hour_o[3]}
{tens_sec_o[6]}
{units_min_o[5]}
{units_hour_o[4]}
{tens_min_o[4]}
{units_sec_o[0]}
{units_sec_o[4]}
{tens_hour_o[0]}
{tens_sec_o[3]}
{units_min_o[2]}
{units_hour_o[1]}
{tens_min_o[1]}
{tens_hour_o[4]}
{units_min_o[6]}
{units_hour_o[5]}
{tens_min_o[5]}
{units_sec_o[1]}
{tens_sec_o[0]}
{units_sec_o[5]}
{tens_hour_o[1]}
{tens_sec_o[4]}
{units_min_o[3]}
{units_hour_o[2]}
{tens_min_o[2]}
{tens_hour_o[5]}
{units_hour_o[6]}
{tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"
set_output_delay -clock clk -add_delay -max -fall 200000000 "{tens_min_o[6]}
{tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}
{tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]}
{tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]}
{units_min_o[4]}
{units_min_o[3]}
{units_min_o[2]}
{units_min_o[1]}
{units_min_o[0]}
{tens_hour_o[6]}
{tens_hour_o[5]}
{tens_hour_o[4]}
{tens_hour_o[3]}
{tens_hour_o[2]}
{tens_hour_o[1]}
{tens_hour_o[0]}
{units_sec_o[6]}
{units_sec_o[5]}
{units_sec_o[4]}
{units_sec_o[3]}
{units_sec_o[2]}
{units_sec_o[1]}
{units_sec_o[0]}
{units_hour_o[6]}
{units_hour_o[5]}
{units_hour_o[4]}
{units_hour_o[3]}
{units_hour_o[2]}
{units_hour_o[1]}
{units_hour_o[0]}
{units_sec_o[6]}
{tens_hour_o[2]}
{tens_sec_o[5]}
{units_min_o[4]}
{units_hour_o[3]}
{tens_min_o[3]}
{tens_hour_o[6]}
{units_sec_o[3]}
{tens_sec_o[2]}
{units_min_o[1]}
{units_hour_o[0]}
{tens_min_o[0]}
{tens_hour_o[3]}
{tens_sec_o[6]}

44

{units_min_o[5]}
{units_hour_o[4]}
{tens_min_o[4]}
{units_sec_o[0]}
{units_sec_o[4]}
{tens_hour_o[0]}
{tens_sec_o[3]}
{units_min_o[2]}
{units_hour_o[1]}
{tens_min_o[1]}
{tens_hour_o[4]}
{units_min_o[6]}
{units_hour_o[5]}
{tens_min_o[5]}
{units_sec_o[1]}
{tens_sec_o[0]}
{units_sec_o[5]}
{tens_hour_o[1]}
{tens_sec_o[4]}
{units_min_o[3]}
{units_hour_o[2]}
{tens_min_o[2]}
{tens_hour_o[5]}
{units_hour_o[6]}
{tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"
set_output_delay -clock clk -add_delay -min -rise 100000000 "{tens_min_o[6]}
{tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}
{tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]}
{tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]}
{units_min_o[4]}
{units_min_o[3]}
{units_min_o[2]}
{units_min_o[1]}
{units_min_o[0]}
{tens_hour_o[6]}
{tens_hour_o[5]}
{tens_hour_o[4]}
{tens_hour_o[3]}
{tens_hour_o[2]}
{tens_hour_o[1]}
{tens_hour_o[0]}
{units_sec_o[6]}
{units_sec_o[5]}
{units_sec_o[4]}
{units_sec_o[3]}
{units_sec_o[2]}
{units_sec_o[1]}
{units_sec_o[0]}
{units_hour_o[6]}
{units_hour_o[5]}
{units_hour_o[4]}
{units_hour_o[3]}
{units_hour_o[2]}
{units_hour_o[1]}
{units_hour_o[0]}
{units_sec_o[6]}
{tens_hour_o[2]}
{tens_sec_o[5]}
{units_min_o[4]}
{units_hour_o[3]}
{tens_min_o[3]}
{tens_hour_o[6]}
{units_sec_o[3]}
{tens_sec_o[2]}
{units_min_o[1]}
{units_hour_o[0]}
{tens_min_o[0]}
{tens_hour_o[3]}
{tens_sec_o[6]}
{units_min_o[5]}
{units_hour_o[4]}
{tens_min_o[4]}
{units_sec_o[0]}
{units_sec_o[4]}
{tens_hour_o[0]}
{tens_sec_o[3]}
{units_min_o[2]}
{units_hour_o[1]}
{tens_min_o[1]}
{tens_hour_o[4]}
{units_min_o[6]}
{units_hour_o[5]}
{tens_min_o[5]}
{units_sec_o[1]}
{tens_sec_o[0]}
{units_sec_o[5]}
{tens_hour_o[1]}
{tens_sec_o[4]}
{units_min_o[3]}
{units_hour_o[2]}
{tens_min_o[2]}
{tens_hour_o[5]}
{units_hour_o[6]}
{tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"
set_output_delay -clock clk -add_delay
-min -fall 100000000 "{tens_min_o[6]}
{tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}
{tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]}
{tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]}
{units_min_o[4]}
{units_min_o[3]}
{units_min_o[2]}
{units_min_o[1]}
{units_min_o[0]}
{tens_hour_o[6]}
{tens_hour_o[5]}
{tens_hour_o[4]}
{tens_hour_o[3]}
{tens_hour_o[2]}
{tens_hour_o[1]}
{tens_hour_o[0]}
{units_sec_o[6]}
{units_sec_o[5]}
{units_sec_o[4]}
{units_sec_o[3]}
{units_sec_o[2]}
{units_sec_o[1]}
{units_sec_o[0]}
{units_hour_o[6]}
{units_hour_o[5]}
{units_hour_o[4]}
{units_hour_o[3]}
{units_hour_o[2]}
{units_hour_o[1]}
{units_hour_o[0]}
{units_sec_o[6]}
{tens_hour_o[2]}
{tens_sec_o[5]}
{units_min_o[4]}
{units_hour_o[3]}
{tens_min_o[3]}
{tens_hour_o[6]}
{units_sec_o[3]}
{tens_sec_o[2]}
{units_min_o[1]}
{units_hour_o[0]}
{tens_min_o[0]}
{tens_hour_o[3]}
{tens_sec_o[6]}
{units_min_o[5]}
{units_hour_o[4]}
{tens_min_o[4]}
{units_sec_o[0]}
{units_sec_o[4]}
{tens_hour_o[0]}
{tens_sec_o[3]}
{units_min_o[2]}
{units_hour_o[1]}
{tens_min_o[1]}
{tens_hour_o[4]}
{units_min_o[6]}
{units_hour_o[5]}
{tens_min_o[5]}
{units_sec_o[1]}
{tens_sec_o[0]}
{units_sec_o[5]}
{tens_hour_o[1]}
{tens_sec_o[4]}
{units_min_o[3]}
{units_hour_o[2]}
{tens_min_o[2]}
{tens_hour_o[5]}
{units_hour_o[6]}
{tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"
set_operating_conditions -library tcbn45gsbwpbc BCCOM
change_selection
set_wire_load_model -name TSMC512K_Lowk_Aggresive -library tcbn45gsbwpbc
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports clk]]
set_driving_cell -no_design_rule -lib_cell INVD0BWP $all_in_ex_clk
set MAX_INPUT_LOAD [expr [load_of tcbn45gsbwpbc/AN2D0BWP/A1] * 10]
set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk
set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]

45

set_max_area 1000
compile -exact_map -ungroup_all
compile_ultra
uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1
-significant_digits 2 -sort_by group }
uplevel #0 { report_timing -path full -delay min -nworst 1 -max_paths 1
-significant_digits 2 -sort_by group }
uplevel #0 { report_constraint -significant_digits 2 }
uplevel #0 { report_power -analysis_effort low }
uplevel #0 { report_resources }
write -hierarchy -format verilog -output /home/lab/VLSI10/dc/top_netlist.v
write -hierarchy -format ddc -output /home/lab/VLSI10/dc/top.ddc
write_sdf top.sdf
write_sdc top.sdc
set_svf -off

6.4 VCS_Kim tra sau khi tng hp

- To th mc after_syn trong th mc vcs
- Sau khi tng hp bng cng c Design Compiler s sinh ra mt file Netlist c
ui m rng l .v bao gm cc cell c bn c ni dy vi nhau v file
delay c ui m rng l .sdf. kim tra timming sau khi tng hp cn c
4 file cn thit l:
file netlist .v

file delay .sdf

file th vin cell tcbn45gsbwp.v
file testbench .v
Ch : cc file .v u phi chn dng `timescale 1ns/1ps.
- Cc file kia cn phi copy vo trong th mc after_syn.
- Vo terminal g cc lnh sau :
vlogan -debug +v2k *.v
vcs -debug tn file module ca testbench -sdf typ:tn modue top:file.sdf l
comp.log
V d: vcs -debug digital_clock_tb -sdf typ:digital_clock_top:top.sdf -l comp.log
- Sau khi phn tch cc file trn trong th mc, s to ra file simv.
- Vo terminal g lnh sau:
./simv gui
- Ri lm tng t nh cc bc trc khi trc khi tng hp.

46

Hnh 35 Kt qu m phng VCS sau DC

-

C th thy mch vn p ng c yu cu v chc nng nh ban u. Cc

im mu vng trong wave form l do m phng c cha tham s v thi gian
gy ra tr, dn ti chuyn trng thi khng ng thi trn cc ng tn hiu.

6.5 Formality
To th mc fm trong project. thc hin phn mm cn co cac file sau:
File theo doi top.svf
Cc file code RTL *.v
File Netlist top.v
Bc 1: M terminal g lnh hin th giao din ngi dng
fm_shell gui

47

Hnh 36 Khi ng formality

Bc 2: Chn Guidance chn ng dn n file top.svf chn Load Files

Hnh 37 Load file *.svf

Bc 3: Chn Reference c tt c cac file verilog tr file testbench
Chn Load File
48

Hnh 38 Load cc file trc khi tng hp

Vo mc 3 chn Set Top Design chn file top module Set top Set
reference

Hnh 39 Set top

Bc 4 : Chn Implementation
49

 Chn Verilog chn ng dn m file top.v sau khi tng hp trong th

mc dc.
Chn Load File.

Hnh 40 Load file sau khi tng hp

Chn Read DB Libraries : chn file tcbn45gsbwpbc.db trong th vin
Milkyway chn Load Files

Hnh 41 Chn th vin tng hp

Chn file top module Set top Set Implementation.
50

Hnh 42 Set top cho file .v sau tng hp

Bc 5: Match
-

Chn Run Matching s c ca s thng bo c bao nhiu im so snh ging

nhau v bao nhiu im so snh khc nhau.

Hnh 43 Run Matching

Bc 6 : Verify
-

Chn Verify : Trn ca s bo Verify Succeeded tc la kim tra thnh

cng.
51

Trong mc Debug s hin ra cac im so sanh gia 2 file code RTL va file
netlist.

Hnh 44 Verify
6.6 Primetime trc khi layout
M phng mch tng hp logic bng vcs ch cho ta bit thit k sau khi tng hp
logic c tha mn cc yu cu chc nng hay khng, m khng m bo thit k
khng vi phm cc tiu chun v thi gian. m bo iu ny, thit k ca chng ta
phi c kim tra bng phn mm prime time trong b phn mm synopsys, prime
time s kim tra li thi gian tt cc cc path c th ca thit k.
Bc 1 : Ci t th vin
To th mc pt trong project
Vo th mc pt m ca s lnh g lnh:
pt_shell
Ci t Search Path:
set lib_path "/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM";
set ADDITIONAL_SEARCH_PATH "$lib_path";
set TARGET_LIBRARY_FILES "tcbn45gsbwpbc.db";
set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH";
set_app_var target_library $TARGET_LIBRARY_FILES;
set_app_var link_library "* $target_library";

Bc 2 : c file .ddc
c file .ddc s dng cu lnh sau:
read_ddc ../dc/top.ddc
52

Hnh 45 Khi ng PrimeTime

M giao din ngi dng dng lnh :
start_gui
Bc 3: Xut bo co
Xut bo co Coverage.txt:
Vo timing Analysis Coverage Lu file bo co t tn file l
coverage.txt
Report Coverage

53

Report : analysis_coverage
-check_type {setup hold recovery removal min_period min_pulse_width
clock_separation max_skew clock_gating_setup clock_gating_hold out_setup out_hold
nochange}
Design : DongHoSo
Version: D-2010.06-SP3-4
Date : Wed Jun 3 18:25:36 2015
****************************************
Type of Check
Total
Met
Violated
Untested
-------------------------------------------------------------------------------setup
20
7 ( 35%)
0 ( 0%)
13 ( 65%)
hold
20
7 ( 35%)
0 ( 0%)
13 ( 65%)
recovery
20
7 ( 35%)
0 ( 0%)
13 ( 65%)
removal
20
7 ( 35%)
0 ( 0%)
13 ( 65%)
min_pulse_width
160
28 ( 18%)
0 ( 0%)
132 ( 83%)
out_setup
42
42 (100%)
0 ( 0%)
0 ( 0%)
out_hold
42
42 (100%)
0 ( 0%)
0 ( 0%)
-------------------------------------------------------------------------------All Checks
324
140 ( 43%)
0 ( 0%)
184 ( 57%)

Nh vy, tt c cc path(324 path) ca thit k u c kim tra v khng c path

no gp phi cc li v thi gian.
-

Tin hnh thit lp ng h v tr u vo nh thc hin vi bc tng hp

bng cc lnh c ly t file command.log xut ra trong bc tng hp
create_clock -name "clk" -period 1000000000 -waveform { 0 500000000
set_input_delay -clock clk -add_delay

-max -rise 200000000 "rst en"

set_input_delay -clock clk -add_delay -max -fall 200000000 "rst en"

set_input_delay -clock clk -add_delay -min -rise 100000000 "rst en"
set_input_delay -clock clk -add_delay
set_output_delay -clock clk -add_delay

-min -fall 100000000 "rst en"

-max -rise 200000000 "."

set_output_delay -clock clk -add_delay -max -fall 200000000 "."

set_output_delay -clock clk -add_delay -min -rise 100000000 "."
set_output_delay -clock clk -add_delay

-min -fall 100000000 "."

54

{ clk

Hnh 46 Thit lp constraint

Xut bo co trn ti a :
Vo Timing Report Timing Lu tn file l rpt_timing_max.txt

55

Hnh 47 Export Report Timing maxdelay

Report Timing maxdelay
----------------------------------------------------------------------------data required time

800000000.000

data arrival time

-200000000.325

--------------------------------------------------------------slack (MET)

600000000.000

Xut bo co tr ti thiu:
Report Timing Edit Trong th mc Data type chn min Lu tn file
l mindelay.txt

56

Hnh 48 Export Report Timing mindelay

Report Timing mindelay
-------------------------------------------------------------------------data required time

0.011

data arrival time

-0.075

----------------------------------------------------------------------------slack (MET)

0.065

6.7 IC Compiler
Phn IC Complier l phn mm c chc nng layout to ra IC da vo file nestlist
(.ddc), (.sdc) v cc th vin vt l (milkyway techfile). Quy trnh thit k ca IC
Complier c biu din nh sau :

57

 Bc 1: Ci t d liu
- M ca s giao din ngi dung bng cch g lnh sau:
icc_shell gui

Hnh 49 Khi ng ICC

58

Ci t th vin
File Setup Application Setup
Thc hin tng t nh bc ci t th vin trong Design Compiler

Hn 50 Ci t th vin
-

To th vin milkyway
File Creat Library

59

Hnh 51 To th vin
-

C cc thit lp sau:
New library path: Chn ng dn n th mc minh cn cha th vin
New library name : t tn th vin
V d :my_lib
Technology Files: Chn ng dn n file th vin cong ngh trong
Milkyway
/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/HVH_0d5_0/tsmcn
45_10lm7X2ZRDL.tf
Trong mc input reference libraries Chn Add chn n th vin
tcnbn45gspwb
60

/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tc
bn45gsbwp
Chn Open library.
Chn OK.
-

c File top.ddc
File Import Read DDC

Hnh 52 c file *.DDC

-

c file top.sdc

File SDC l file rng buc thit k. No c a vao rang buc thit k sao cho
thit k ca mnh ti u nht.
File Import Read SDC

Hnh 53 c file *.SDC

61

Sau khi c file top.sdc, chn Window New layout window , s xut hin
ca s giao din hin th cc cell c xp chng ln nhau.

Hnh 54 Cc cell ca IC cha sp xp

62

To TLU+
File Set TLU+

Hnh 55 Xt th vin TLU+

C cc thit lp sau:
Max TLU+ file : Chn n th vin cng ngh theo ng dn sau:
/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p
10m+alrdl_rcbest_top2.tluplus
Min TLU+ file : Chn n th vin cong ngh theo ng dn sau:
/
home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p
10m+alrdl_rcworst_top2.tluplus
Layer name : Chn n th vin cong ngh theo ng dn sau:
/
home/lab/Desktop/milkyway/tcbn45gsbwp_120atechfiles/tluplus/star.map_10
M
-

Lu : Trong th vin c nhiu la chn khc nhau ng vi s lp metal khc

nhau.

kim tra th vin s dng cc lnh sau :

63

check_library
check_tlu_plus_files
list_libs
-

Ngoi ra c th xut cc bo co kim tra xem trong qu trnh layout gp

phi vn g thng qua cc lnh sau:
check_timing
report_timing_requirements
report_disable_timing
report_case_analysis
report_clock
report_clock skew

Trong khi tng hp, cc cng c xt mc l tng nn khi layout cn phi

xa c tnh ny, s dng cu lnh:
remove_ideal_network [get_ports]

Sau khi ci t xong d liu, cn lu li bc ny c th d dng xem li cc

thit lp ca mnh, s dng cu lnh sau:
save_mw_cel -as data_setup
Hoc vao File Save Design.

Bc 2: Floor Planning
-

Thc hin khi to nn

Floorplan Initialize Floorplan

64

Hnh 56 Khi to nn
Sau khi khi to nn s c hnh nh sau:

Thc hin to chn ni ngun v ni t VDD v VSS

PreRoute Derive PG Conection

65

Hnh 57 VDD v VSS

-

To cc vng dy VDD v VSS

Preroute Creat ring Net(chn VDD)

66

Hnh 58 Chn lp cho VDD

-

Tip theo chn VSS

67

Hnh 59 Chn lp cho VSS

-

Sau khi to c cc vng dy VDD v VSS trn hnh s xut hin nh sau:

Hnh 60 Sau khi to VDD v VSS

68

Thit lp rng cho day ngun dy t cho tng lp kim loi:

Preroute Creat power strap

VDD:

Hnh 61 rng VDD

VSS:

69

Hnh 62 rng VSS

-

To vng m:
Preroute Creat Pad ring

Hnh 63 To vng m
-

Sau khi xong bc Floor Planning ta cn lu li s dng cu lnh

save_mw_cel -as floorplanned

Bc 3: Placement (sp xp cell) v kim tra tc nghn

70

 Placement Core Placement and Optimization

Hnh 64 Sp xp cell
Sau khi sp xp cc cell xong ta c:

kim tra tc nghn xut bo co sau:

report_congestion
global

-grc_based

-by_layer

-routing_stage

Lu li qu trnh thc hin Placement:

save_mw_cel -as placed

71

 Bc 4: To clock tree
Clock Tree Synthesis l cng c dng ti u ng tn hiu clock phn phi
cho cc mch dy trong thit k. Khi khng c Clock Tree Synthesis th trong thit
k s xut hin nh sau:

Khi thc hin xong Clock Tree Synthesis, phn b tn hiu clock s nh sau:

72

thc hin Clock Tree Synthesis, chn Clock Core CTS and Optimization

Hnh 65 Clock tree

-

Sau khi to c clock tree:

Hnh 66 Kt qu clock tree

73

Lu li bc to clock tree
save_mw_cel -as ctsed
Bc 5: Thc hin i dy
Route Core Routing and Optimization

Hnh 67 Routing
Lu li kt qu sau khi i dy t ng
save_mw_cel -as routed
Route Extract RC

74

Hnh 68 Extract RC
Kt qu sau ICC:

Bc 6: Xut cc file .sdc, .sdf, .v, .spef,..v bo co

To th mc rpt trong th mc icc cha cc file report

Xut cc file .sdc, .sdf, .v, ...

write_sdf icc.sdf
write_sdc icc.sdc
write -format ddc
{icc.ddc}

-hierarchy

-modified

-output

write_verilog icc.v

Xut ra cc file bo co vo th mc rpt

report_qor > rpt_icc_qor.txt

75

report_area > rpt_icc_area.txt

report_constraint -all_violators > rpt_icc_constraint.txt
report_port > rpt_icc_port.txt
report_power > rpt_icc_power.txt
report_timing > rpt_icc_timing.txt
report_timing -nosplit > rpt_icc_timing_nosplit.txt
report_timing -delay min > rpt_icc_timing_delay_min.txt
report_design -physical > rpt_icc_design_physical.txt

6.8 VCS_ Kim tra sau khi layout

To th mc after_icc trong vcs.
Trong qa trnh Layout c th lm sai timing v vy sau khi layout xong cn
phi kim tra li timing xem c ng nh timming mnh kim tra sau khi
tng hp hay khng.
kim tra timming bc ny cn c cc file sau:

file .v c to ra sau khi layout

file delay .sdf c to ra sau khi layout
file th vin cell tcbn45gsbwp.v
file testbench .v
Thc hin cc bc tng t nh khi kim tra chc nng trc khi tng hp.

76

Hnh 69 Kt qu m phng VCS sau ICC

6.9 PT_Kim tra sau khi layout

- S dng file .ddc c to ra sau khi chy ICC. Cc bc thc hin tng t
nh trc khi layout.
PT sau ICC

77

Report : analysis_coverage
-check_type {setup hold recovery removal min_period
min_pulse_width clock_separation max_skew clock_gating_setup
clock_gating_hold out_setup out_hold nochange}
Design : DongHoSo
Version: D-2010.06-SP3-4
Date
: Wed Jun 3 22:28:49 2015
****************************************
Type of Check
Total
Met
Violated
Untested
------------------------------------------------------------------------------setup
20
7 ( 35%)
0 ( 0%)
13
( 65%)
hold
20
7 ( 35%)
0 ( 0%)
13
( 65%)
recovery
20
7 ( 35%)
0 ( 0%)
13
( 65%)
removal
20
7 ( 35%)
0 ( 0%)
13
( 65%)
min_pulse_width
160
28 ( 18%)
0 ( 0%)
132
( 83%)
out_setup
42
42 (100%)
0 ( 0%)
0 (
0%)
out_hold
42
42 (100%)
0 ( 0%)
0 (
0%)
------------------------------------------------------------------------------All Checks
324
140 ( 43%)
0 ( 0%)
184
( 57%)

***** End Of Report *****

Report timing max sau ICC

----------------------------------------------------------------------data required time
999999999.989
data arrival time
-200000000.169
-----------------------------------------------------------------------slack (MET)
800000000.000
Report timing min sau ICC
78

-----------------------------------------------------------------------data required time

0.008
data arrival time
-0.063
----------------------------------------------------------------------slack (MET)
0.065

79

TNG KT
Trong qu trnh thc hin phn bi tp ln trn nhm :
-

Tham kho mt s ti liu nh: Slide bi ging VLSI ca TS Nguyn V

Thng, slide bi ging verilog ca TS Nguyn Hong Dng, SPEC hng dn
bi tp ln ca thy Nguyn Nam Phong, , gio trnh Thc hnh Thit k h
thng s v IC s ca H Bch Khoa H Ch Minh.
Thun li: c s h tr tn tnh chu o ca cc thy Nguyn V Thng,
Nguyn Nam Phong. S h tr ca cc anh kha trn tng nghin cu v s
dng synopsys v cc bn tham gia kha hc phn cng.
Kh khn: Ln u lm quen vi phn mm mi, yu cu cao v cc chun nn
trong qu trnh chy code cha th sa c li: Dng min_clock_w ti u
ra ca counter second lm u vo clk cho khi counter minute, tng t vi
hour_clock_w.
Th nghim phng n B: Phn m phng chy th trn leda c cht chnh sa
v code vt qua li v t lut ca leda.

Chng em xin cm n!

80