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  • NVL-05.Area-Delay-Power Efficient Carry-Select Adder

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    The document proposes a new area-delay-power efficient carry-select adder. It analyzes the logic operations in conventional carry-select adders and binary-to-excess-1 converters to identify redundant logic. The proposed design eliminates redundant logic operations, schedules the carry-select operation before calculating the final sum, and involves significantly less area and delay than recently proposed designs. It is well-suited for use in square-root carry-select adders due to its small carry-output delay.

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    NVL-05.Area–Delay–Power Efficient Carry-Select Adder

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    The document proposes a new area-delay-power efficient carry-select adder. It analyzes the logic operations in conventional carry-select adders and binary-to-excess-1 converters to identify redundant logic. The proposed design eliminates redundant logic operations, schedules the carry-select operation before calculating the final sum, and involves significantly less area and delay than recently proposed designs. It is well-suited for use in square-root carry-select adders due to its small carry-output delay.

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    17 views3 pages

    NVL-05.Area-Delay-Power Efficient Carry-Select Adder

    Uploaded by

    sivakumarb92
    The document proposes a new area-delay-power efficient carry-select adder. It analyzes the logic operations in conventional carry-select adders and binary-to-excess-1 converters to identify redundant logic. The proposed design eliminates redundant logic operations, schedules the carry-select operation before calculating the final sum, and involves significantly less area and delay than recently proposed designs. It is well-suited for use in square-root carry-select adders due to its small carry-output delay.

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    © All Rights Reserved
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    of 3

    AreaDelayPower Efficient Carry-Select Adder

    AIM:
    The main aim of the project is to design AreaDelayPower Efficient
    Carry-Select Adder.

    (ABSTRACT)
    The logic operations involved in conventional carry select adder (CSLA) and
    binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data
    dependence and to identify redundant logic operations. By eliminated all the
    redundant logic operations present in the conventional CSLA and proposed a new
    logic formulation for CSLA. In the proposed scheme, the carry select (CS)
    operation is scheduled before the calculation of final-sum, which is different from
    the conventional approach The proposed CSLA design involves significantly less
    area and delay than the recently proposed BEC-based CSLA. Due to the small
    carry-output delay, the proposed CSLA design is a good candidate for square-root
    (SQRT) CSLA.

    Proposed Architecture:
    In the architecture there is RCA block which is implemented with full adders These
    full adders can be replaced with 3:2 compressors which makes the architecture
    more faster then the exciting . And we can increase bit size .
    Advantage:
    CD logics advantages in terms of delay and EDP were also demonstrated in 8-bit
    Wallace tree multipliers. Compared to 32-bit adders, CD logic achieves a similar
    delay improvement, but has an even better EDP reduction, primarily because the
    final adder which makes up the critical path of the multiplier is a relatively small

    circuit block of the overall circuitry. At 25%, CD logic is 52, 25, and 37% more
    EDP-efficient than static, dynamic, and pseudo-nMOS logic, respectively
    .
    BLOCK DIAGRAM:

    Proposed SQRT-CSLA for n = 16


    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:
    [1] K. K. Parhi, VLSI Digital Signal Processing. New York, NY, USA:Wiley,1998.
    [2] A. P. Chandrakasan, N. Verma, and D. C. Daly, Ultralow-power electronics for
    biomedical applications, Annu. Rev. Biomed. Eng., vol. 10, pp. 247274, Aug.
    2008.
    [3] O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput., vol. EC-11,
    no. 3, pp. 340344, Jun. 1962.

    [4] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electron.
    Lett., vol. 37, no. 10, pp. 614615, May 2001.
    [5] Y. He, C. H. Chang, and J. Gu, An area-efficient 64-bit square root carry select
    adder for low power application, in Proc. IEEE Int. Symp. Circuits Syst., 2005,
    vol. 4, pp. 40824085.

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