Figure6.1ANDoperation.

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Figure6.2NOToperation.

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Figure6.3ORoperation.

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Figure6.4Additionallogicgatesymbols.

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Figure6.5BasicBooleanoperationscanbeimplementedwithNANDgates.
Therefore,anyBooleanfunctioncanbeimplementedbytheuse\breakofNANDgatesalone.

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Figure6.6TheAND,OR,and\breakNOToperationscanbeimplementedwithNORgates.SeeExercise6.1.

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Figure6.7CircuitsforExercise6.2.

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Figure6.8Outputvoltagerangesforthe7400ALSTTLlogicfamily.

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Figure6.9Logicinverter.

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Figure6.10Inputandoutputvoltagerangesforthe7400ALSTTLlogicfamilyoperatedfroma+5Vsupply.

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Figure6.11Referencedirectionsforinputandoutputcurrents.(I_Ohasanegativevalueiftheoutputsourcescurrent.)

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Figure6.12Portionofalogiccircuit.Theinverterhasafanoutof3(i.e.,theinverterdrives3inputs).

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Figure6.13Simplifiedcircuitforalogicinverter.

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Figure6.14Loadcapacitancecausesdynamicpowerdissipationinalogicgate.

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Figure6.15Inputpulseandoutputofatypicalinverter.

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Figure6.16AglitchintheoutputoftheANDgatecausedbypropagationdelayintheinverter.
NotethatwehaveassumedzerodelayfortheANDgate.

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Figure6.17Logicgatesimplementedwithelectronicswitches.SeeExercise6.4.

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Figure6.18MOSinverterwithpullupresistor.

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Figure6.19LoadlineanalysisforthecircuitofFigure6.18a.

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Figure6.20Invertertransfercharacteristic.

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Figure6.21a&bThelowtohighoutputtransitionoftheresistorpullupNMOSinverter.

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Figure6.21cThelowtohighoutputtransitionoftheresistorpullupNMOSinverter.

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Figure6.22Loadlineanalysisofthehightolowtransition.

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Figure6.23Cascadeofthreeinverters.

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Figure6.24InputandoutputwaveformsforthethirdstageofFigure6.23.

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Figure6.25SeveraltypesofMOSinvertercircuits.

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Figure6.26CircuitforExample6.6.

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Figure6.29TransfercharacteristicoftheNMOSpullupinverter.

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Figure6.30CMOSinverter.

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Figure6.31aGraphicalanalysisoftheCMOSinverter.

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Figure6.31bGraphicalanalysisoftheCMOSinverter.

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Figure6.32TransfercharacteristicofatypicalCMOSinverter.TheletteredpointscorrespondtothepointsofFigure6.31.

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Figure6.33SupplycurrentforaCMOSinverter.

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Figure6.34TransfercharacteristicforCMOSinverterwithVton=0.6V,Vtop=0.6V,andVDD=3V.

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Figure6.35ThehightolowtransitionoftheCMOSinverter.

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Figure6.36IdealizedwaveformsforthehightolowtransitionoftheCMOSinverter.

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Figure6.37CascadeofthreeCMOSinverters.

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Figure6.38WaveformsforstagethreeofFigure6.37.

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Figure6.39CMOSlogicgates.

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Figure6.40ThreeinputNORgate.

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Figure6.41CircuitsusedtoplotthetransfercharacteristicsofatwoinputNANDgate.

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Figure6.45TransfercharacteristicsofatwoinputNANDgate.

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Figure6.46CircuitsusedtodeterminethepropagationdelaysofthetwoinputNANDgate.

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Figure6.47SwitchingtransientsofthetwoinputNANDgate.

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Figure6.48StaticCMOSgatescontainredundantswitchingfunctions

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Figure6.49DynamiclogicNORgate.

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Figure6.50DynamicCMOSimplementationofF=(AB+C+DE).

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Figure6.51CMOSanalogswitch.

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Figure6.52EquivalentcircuitandsymbolfortheCMOStransmissiongate.

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Figure6.53Passtransistorlogic.

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