Professional Documents
Culture Documents
Dien Tu So
Dien Tu So
IN T S
(Dng cho sinh vin h o to i hc t xa)
Lu hnh ni b
H NI - 2006
IN T S
Bin son :
LI GII THIU
Cng vi s tin b ca khoa hc v cng ngh, cc thit b in t ang v s tip tc c
ng dng ngy cng rng ri v mang li hiu qu cao trong hu ht cc lnh vc kinh t k thut
cng nh i sng x hi.
Vic x l tn hiu trong cc thit b in t hin i u da trn c s nguyn l s. Bi
vy vic hiu su sc v in t s l iu khng th thiu c i vi k s in t hin nay.
Nhu cu hiu bit v k thut s khng phi ch ring i vi cc k s in t m cn i vi
nhiu cn b k thut chuyn ngnh khc c s dng cc thit b in t.
Ti liu ny gii thiu mt cch h thng cc phn t c bn trong cc mch in t s kt
hp vi cc mch in hnh, gii thch cc khi nim c bn v cng in t s, cc phng php
phn tch v thit k mch logic c bn.
Ti liu bao gm cc kin thc c bn v mch cng logic, c s i s logic, mch logic t
hp, cc trig, mch logic tun t, cc mch pht xung v to dng xung, cc b nh thng dng.
c bit l trong ti liu ny c b xung thm phn logic lp trnh v ngn ng m t phn cng
VHDL. y l ngn ng ph bin hin nay dng to m hnh cho cc h thng k thut s. Tt
c gm 9 chng. Trc v sau mi chng u c phn gii thiu v phn tm tt gip ngi
hc d nm bt kin thc hn. Cc cu hi n tp ngi hc kim tra mc nm kin thc
sau khi hc mi chng. Trn c s cc kin thc cn bn, ti liu c gng tip cn cc vn
hin i, ng thi lin h vi thc t k thut.
Ti liu gm c 9 chng c b cc nh sau:
Chng 1: H m
Chng 2: i s Boole v cc phng php biu din hm
Chng 3: Cng logic TTL v CMOS
Chng 4: Mch logic t hp.
Chng 5: Mch logic tun t.
Chng 6: Mch pht xung v to dng xung.
Chng 7: B nh bn dn.
Chng 8: Logic lp trnh.
Chng 9 : Ngn ng m t phn cng VHDL.
Do thi gian c hn nn ti liu ny khng trnh khi thiu st, rt mong ngi c gp .
Cc kin xin gi v Khoa K thut in t 1- Hc vin Cng ngh Bu chnh vin thng.
Xin trn trng cm n.
Chng 1: H m
CHNG 1: H M
GII THIU
Khi ni n s m, ngi ta thng ngh ngay n h thp phn vi 10 ch s c k
hiu t 0 n 9. My tnh hin i khng s dng s thp phn, thay vo l s nh phn vi hai
k hiu l 0 v 1. Khi biu din cc s nh phn rt ln, ngi ta thay n bng cc s bt phn
(Octal) v thp lc phn (HexaDecimal).
m s lng ca cc i lng l mt nhu cu ca lao ng, sn xut. Ngng mt qu
trnh m, ta c mt biu din s. Cc phng php m v biu din s c gi l h m.
H m khng ch c dng biu din s m cn l cng c x l.
C rt nhiu h m, chng hn nh h La M, La Tinh ... H m va c tnh a dng va
c tnh ng nht v ph bin. Mi h m c u im ring ca n nn trong k thut s s s
dng mt s h b khuyt cho nhau.
Trong chng ny khng ch trnh by cc h thp phn, h nh phn, h bt phn, h thp
lc phn v cn nghin cu cch chuyn i gia cc h m. Chng ny cng cp n s nh
phn c du v khi nim v du phy ng.
NI DUNG
1.1. BIU DIN S
Nguyn tc chung ca biu din l dng mt s hu hn cc k hiu ghp vi nhau theo qui
c v v tr. Cc k hiu ny thng c gi l ch s. Do , ngi ta cn gi h m l h
thng s. S k hiu c dng l c s ca h k hiu l r. Gi tr biu din ca cc ch khc
nhau c phn bit thng qua trng s ca h. Trng s ca mt h m bt k s bng ri, vi i
l mt s nguyn dng hoc m.
Bng 1.1 l lit k tn gi, s k hiu v c s ca mt vi h m thng dng.
Tn h m
S k hiu
C s (r)
H nh phn (Binary)
0, 1
H bt phn (Octal)
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
10
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
16
Bng 1.1
Ngi ta cng c th gi h m theo c s ca chng. V d: H nh phn = H c s 2, H
thp phn = H c s 10...
2
Chng 1: H m
Di y, ta s trnh by tm tt mt s h m thng dng.
1.1.1 H thp phn
Cc k hiu ca h nh nu bng 1.1. Khi ghp cc k hiu vi nhau ta s c mt
biu din. V d: 1265,34 l biu din s trong h thp phn:
= di 10i
n 1
n : s ch s phn nguyn,
m : s ch s phn phn s.
u im ca h thp phn l tnh truyn thng i vi con ngi. y l h m con ngi
d nhn bit nht. Ngoi ra, nh c nhiu k hiu nn kh nng biu din ca h rt ln, cch biu
din gn, tn t thi gian vit v c.
Nhc im chnh ca h l do c nhiu k hiu nn vic th hin bng thit b k thut s
kh khn v phc tp.
Biu din s tng qut:
Vi c s bt k r v d bng h s a tu ta s c cng thc biu din s chung cho tt c
cc h m:
= a n 1 r n 1 + ... + a1 r1 + a 0 r 0 + a 1 r 1 + ... + a m r m
m
= a i ri
n 1
Trong mt s trng hp, ta phi thm ch s trnh nhm ln gia biu din ca cc h.
V d: 3610 , 368 , 3616 .
1.1.2 H nh phn
1.1.2.1. T chc h nh phn
H nh phn (Binary number system) cn gi l h c s hai, gm ch hai k hiu 0 v 1, c
s ca h l 2, trng s ca h l 2n. Cch m trong h nh phn cng tng t nh h thp phn.
Khi u t gi tr 0, sau ta cng lin tip thm 1 vo kt qu m ln trc. Nguyn tc cng
nh phn l : 0 + 0 = 0, 1 + 0 = 1, 1 + 1 = 10 (102 = 210).
3
Chng 1: H m
Trong h nh phn, mi ch s ch ly 2 gi tr hoc 0 hoc 1 v c gi tt l "bit". Nh
vy, bit l s nh phn 1 ch s. S bit to thnh di biu din ca mt s nh phn. Mt s nh
phn c di 8 bit c gi 1 byte. S nh phn hai byte gi l mt t (word). Bit tn cng bn
phi gi l bit b nht (LSB Least Significant Bit) v bit tn cng bn tri gi l bit ln nht
(MSB - Most Significant Bit).
Biu din nh phn dng tng qut :
N 2 = b n 1b n 2 ....b1b0 .b 1b 2 ....b m
Trong , b l h s nhn ca h. Cc ch s ca h s ng thi cng bng ly tha ca
trng s tng ng. V d :
0.
s nh phn phn s
22
21
20
21
22
N2
= b n 1 2n 1 + ... + b1 21 + b0 20 + b 1 21 + ... + b m 2 m
m
= b i 2i
n 1
10 - 1 = 1 (mn 1)
Khi tr nhiu bit nh phn, nu cn thit ta mn bit k tip c trng s cao hn. Ln tr k
tip li phi tr thm 1.
c. Php nhn
Qui tc nhn hai bit nh phn nh sau:
0x0=0 , 0x1=0 ,1x0=0 ,1x1=1
Php nhn hai s nh phn cng c thc hin ging nh trong h thp phn.
Ch : Php nhn c th thay bng php dch v cng lin tip.
d. Php chia
Php chia nh phn cng tng t nh php chia hai s thp phn.
u im chnh ca h nh phn l ch c hai k hiu nn rt d th hin bng cc thit b c,
in. Cc my vi tnh v cc h thng s u da trn c s hot ng nh phn (2 trng thi). Do
4
Chng 1: H m
, h nh phn c xem l ngn ng ca cc mch logic, cc thit b tnh ton hin i - ngn
ng my.
Nhc im ca h l biu din di, mt nhiu thi gian vit, c.
1.1.3 H bt phn v thp lc phn
1.1.3.1 H bt phn
1. T chc ca h : Nhm khc phc nhc im ca h nh phn, ngi ta thit lp cc h
m c nhiu k hiu hn, nhng li c quan h chuyn i c vi h nh phn. Mt trong s
l h bt phn (hay h Octal, h c s 8).
H ny gm 8 k hiu : 0, 1, 2, 3, 4, 5, 6 v 7. C s ca h l 8. Vic la chn c s 8 l
xut pht t ch 8 = 23. Do , mi ch s bt phn c th thay th cho 3 bit nh phn.
Dng biu din tng qut ca h bt phn nh sau:
N8
= O n 1 8n 1 + ... + O0 80 + O 1 81 + ... + O m 8 m
m
= Oi 8i
n 1
Lu rng, h thp phn cng m tng t v c gii rng hn h bt phn, nhng khng
th tm c quan h 10 = 2n (vi n nguyn).
2. Cc php tnh trong h bt phn
a. Php cng
Php cng trong h bt phn c thc hin tng t nh trong h thp phn. Tuy nhin,
khi kt qu ca vic cng hai hoc nhiu ch s cng trng s ln hn hoc bng 8 phi nh ln
ch s c trng s ln hn k tip.
b. Php tr
Php tr cng c tin hnh nh trong h thp phn. Ch rng khi mn 1 ch s c
trng s ln hn th ch cn cng thm 8 ch khng phi cng thm 10.
Cc php tnh trong h bt phn t c s dng. Do , php nhn v php chia dnh li
nh mt bi tp cho ngi hc.
1.1.3.2 H thp lc phn
1.T chc ca h
H thp lc phn (hay h Hexadecimal, h c s 16). H gm 16 k hiu l 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, F.
Trong , A = 1010 , B = 1110 , C = 1210 , D = 1310 , E = 1410 , F = 1510 .
C s ca h l 16, xut pht t yu t 16 = 24. Vy, ta c th dng mt t nh phn 4 bit
(t 0000 n 1111) biu th cc k hiu thp lc phn. Dng biu din tng qut:
Chng 1: H m
N16
= Hi 16i
n 1
chia
57/2
28
28/2
14
14/2
7/2
3/2
1/2
LSB
MSB
Chng 1: H m
Phn nguyn ta va thc hin v d a), do ch cn i phn phn s 0,375.
Bc
Nhn
Kt qu
Phn nguyn
0,375 x 2
0.75
0,75 x 2
1.5
0,5 x 2
1.0
0,0 x 2
Kt qu : 0,37510 = 0,01102
S dng phn nguyn c v d 1) ta c :
57,37510 = 111001.01102
= a n 1 r n 1 + .... + a 0 r 0 + a 1 r 1 + .... + a m r m
N10
Chng 1: H m
1.3 S NH PHN C DU
1.3.1 Biu din s nh phn c du
C ba phng php th hin s nh phn c du sau y.
1. S dng mt bit du. Trong phng php ny ta dng mt bit ph, ng trc cc bit tr
s biu din du, 0 ch du dng (+), 1 ch du m (-).
2. S dng php b 1. Gi nguyn bit du v ly b 1 cc bit tr s (b 1 bng o ca cc
bit cn c ly b).
3. S dng php b 2
L phng php ph bin nht. S dng th hin bng s nh phn khng b (bit du bng
0), cn s m c biu din qua b 2 (bit du bng 1). B 2 bng b 1 cng 1.
C th biu din s m theo phng php b 2 xen k: bt u t bit LSB, dch v bn tri,
gi nguyn cc bit cho n gp bit 1 u tin v ly b cc bit cn li. Bit du gi nguyn.
1.3.2 Cc php cng v tr s nh phn c du
Nh ni trn, php b 1 v b 2 thng c p dng thc hin cc php tnh nh
phn vi s c du.
1. Biu din theo bit du
a. Php cng
Hai s cng du: cng hai phn tr s vi nhau, cn du l du chung.
Hai s khc du v s m c tr s nh hn: cng tr s ca s dng vi b 1 ca s m.
Bit trn c cng thm vo kt qu trung gian. Du l du dng.
Hai s khc du v s m c tr s ln hn: cng tr s ca s dng vi b 1 ca s m.
Ly b 1 ca tng trung gian. Du l du m.
b. Php tr. Nu lu rng, - (-) = + th trnh t thc hin php tr trong trng hp ny
cng ging php cng.
2. Cng v tr cc s theo biu din b 1
a. Cng
Hai s dng: cng nh cng nh phn thng thng, k c bit du.
Hai s m: biu din chng dng b 1 v cng nh cng nh phn, k c bit du. Bit trn
cng vo kt qu. Ch , kt qu c vit di dng b 1.
Hai s khc du v s dng ln hn: cng s dng vi b 1 ca s m. Bit trn c
cng vo kt qu.
Hai s khc du v s m ln hn: cng s dng vi b 1 ca s m. Kt qu khng c bit
trn v dng b 1.
b. Tr
thc hin php tr, ta ly b 1 ca s tr, sau thc hin cc bc nh php cng.
8
Chng 1: H m
3. Cng v tr nh phn theo biu din b 2
a. Cng
Hai s dng: cng nh cng nh phn thng thng. Kt qu l dng.
Hai s m: ly b 2 c hai s hng v cng, kt qu dng b 2.
Hai s khc du v s dng ln hn: ly s dng cng vi b 2 ca s m. Kt qu bao
gm c bit du, bit trn b i.
Hai s khc du v s m ln hn: s dng c cng vi b 2 ca s m, kt qu dng
b 2 ca s dng tng ng. Bit du l 1.
b. Php tr
Php tr hai s c du l cc trng hp ring ca php cng. V d, khi ly +9 tr i +6 l
tng ng vi +9 cng vi -6.
1.4. DU PHY NG
1.4.1 Biu din theo du phy ng
Gm hai phn: s m E (phn c tnh) v phn nh tr M (trng phn s). E c th c
di t 5 n 20 bit, M t 8 n 200 bit ph thuc vo tng ng dng v di t my tnh. Thng
thng dng 1 s bit biu din E v cc bit cn li cho M vi iu kin:
1/ 2 M 1
E v M c th c biu din dng b 2. Gi tr ca chng c hiu chnh m bo
mi quan h trn y c gi l chun ha.
1.4.2 Cc php tnh vi biu din du phy ng
Ging nh cc php tnh ca hm m. Gi s c hai s theo du phy ng chun ha:
X = 2E x ( M x ) v Y = 2
Tch: Z = X.Y = 2
Ey
( M y ) th:
E x +E y
Thng: W = X / Y = 2
( M x .M y ) = 2E
E x E y
Mz
( M x / M y ) = 2E
Mw
TM TT
Trong chng ny chng ta gii thiu v mt s h m thng c s dng trong h
thng s: h nh phn, h bt phn, h thp lc phn. V phng php chuyn i gia cc h m
.
Ngoi ra cn gii thiu cc php tnh s hc trong cc h .
Chng 1: H m
CU HI N TP
1. nh ngha th no l bit, byte?
2. i s nh phn sau sang dng bt phn: 0101 1111 0100 1110
a. 57514
b. 57515
c. 57516
d. 57517
3. Thc hin php tnh hai s thp lc phn sau: 132,4416 + 215,0216.
a. 347,46
b. 357,46
c. 347,56
d. 357,67
4. Thc hin php cng hai s c du sau theo phng php b 1:
0000 11012 + 1000 10112
a. 0000 0101
b. 0000 0100
c. 0000 0011
d. 0000 0010
5. Thc hin php cng hai s c du sau theo phng php b 2:
0000 11012 1001 10002
a. 1000 1110
b. 1000 1011
c. 1000 1100
d. 1000 1110
6. Hai byte c bao nhiu bit?
a. 16
b. 8
c. 32
d. 64
10
CM trng
thi Ngt:
A= 0
CM trng
thi ng:
A=1
NI DUNG
2.1 I S BOOLE
2.1.1. Cc nh l c bn:
STT
Tn gi
Dng tch
Dng tng
ng nht
X.1 = X
X+0=X
Phn t 0, 1
X.0 = 0
X+1=1
X.X = 0
X + X =1
Bt bin
X.X = X
X+X=X
Hp th
X + X.Y = X
X.(X + Y) = X
Ph nh p
X=X
nh l
DeMorgan
12
m0
m1
m2
m3
m4
m5
m6
m7
N = 22
f ( X n 1,..., X 0 ) =
2n 1
a i mi
i =0
13
f ( X n 1,..., X 0 ) =
2n 1
( a i + mi )
i =0
f = AB + AC + BC
p dng nh l, A + A = 1 , X + XY = X ta c:
f = AB + AC + BC ( A + A )
= AB + ABC + AC + ABC
= AB + AC
Vy nu trong tng cc tch, xut hin mt bin v o ca bin trong hai s hng khc
nhau, cc tha s cn li trong hai s hng to thnh tha s ca mt s hng th ba th s
hng th ba l tha v c th b i.
2.3.2 Phng php bng Cc n
Phng php ny thng c dng rt gn cc hm c s bin khng vt qu 5.
Cc bc ti thiu ha:
1. Gp cc k cn c gi tr 1 (hoc 0) li thnh tng nhm 2, 4, ...., 2i . S trong
mi nhm cng ln kt qu thu c cng ti gin. Mt c th c gp nhiu ln trong cc
nhm khc nhau. Nu gp theo cc c gi tr 0 ta s thu c biu thc b ca hm.
2. Thay mi nhm bng mt hng tch mi, trong gi li cc bin ging nhau theo dng
v ct.
3. Cng cc hng tch mi li, ta c hm ti gin.
V d: Hy dng bng Cc n gin c hm :
f ( A, B, C ) = (1, 2, 3, 4, 5 )
Li gii:
BC
00
01
11
10
f1 = B
Hnh 2-2
14
f 2 = AC
f = f1 + f 2 = B + AC
Nu gp cc c gi tr 0 li theo hai nhm, ta thu c biu thc hm b f :
f = AB + BC
2.3.3. Phng php Quine Mc. Cluskey
Phng php ny c th ti thiu ha c hm nhiu bin v c th tin hnh cng vic
nh my tnh.
Cc bc ti thiu ha:
1. Lp bng lit k cc hng tch di dng nh phn theo tng nhm vi s bit 1 ging
nhau v xp chng theo s bit 1 tng dn.
2. Gp 2 hng tch ca mi cp nhm ch khc nhau 1 bit to cc nhm mi. Trong mi
nhm mi, gi li cc bin ging nhau, bin b i thay bng mt du ngang (-).
Lp li cho n khi trong cc nhm to thnh khng cn kh nng gp na. Mi ln rt gn,
ta nh du # vo cc hng ghp cp c. Cc hng khng nh du trong mi ln rt gn s
c tp hp li la chn biu thc ti gin.
V d. Hy tm biu thc ti gin cho hm:
Bng b
Hng tch
Nh phn
Rt gn ln u.
Rt gn ln th 2.
sp xp
ABCD
ABCD
ABCD
10
1010
1 0 1 - # (10,11)
11--
(12,13,14,15)
12
1100
1 - 1 0 # (10,14)
1-1-
(10,11,14,15)
11
1011
1 1 0 - # (12,13)
13
1101
1 1 - 0 # (12,14)
14
1110
1 - 1 1 # (11,15)
15
1111
1 1 - 1 # (13,15)
1 1 1 - # (14,15)
Bng 2.3
A BCD
10
11
11-1-1-
12
13
14
15
x
Bng 2.4
T bng 2-4, ta nhn thy rng 4 ct c duy nht mt du "x" ng vi hai hng 11-- v 1-1-.
Do , biu thc ti gin l :
f ( A, B, C, D ) = AB + AC
f = f ( A, B ) = A.B
hoc nhiu bin:
f ( A, B, C, D,...) = A.B.C.D...
A
B
A
B
C
D
E
&
A
B
C
D
E
&
16
Li vo A
Li ra f
Li vo B
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
17
1s
1s
f ( A, B ) = A + B
f ( A, B, C, D...) = A + B + C + D + ...
A
F
A
B
A
B
C
D
E
C
D
E
a) Theo gi tr logic
b) Theo mc in th
18
1 0
t2
t1
t0
t3
t4
t5
t6
t7
1
t8
t9
A
f
t10
A = 0 th A = 1 ,
nu A = 1 th A = 0
Hnh 2-9
a) Theo gi tr logic
b) Theo mc logic
19
0 0
1 1 1
0
t
V
0
H
t
0
0 0
1 1 1
L
b) Logic dng vi mc m.
f =
AB
f = ABCD...
K hiu cng NAND (hnh 2-12a,b) v bng trng thi (bng 2-8).
A
A
B
C
A
B
C
D
&
&
f = A + B hay f = A + B + C + ...
A+B
A
B
A+B
B
A
AB
f = AB + AB
AB
f = AB + AB
f = AB
A
f
=1
f = AB + AB hay f = A B = A ~ B
K hiu ca cng XNOR hai li vo c trnh by hnh 2-17.
22
=1
VVHmax
VRHmax
VVHmax
NH
4v
3v
VVHmin
2v
1v
0v
0,8v
VVLma
Vo
NH
3,5v
VVLma
1,5v
VRHmax
VRHmin
VRHmin
2,4v
NL 0,4v
VVHmin
4,9v
NL
VRLmax
Ra
a) i vi h TTL
0,1v
Vo
VRLmax
Ra
b) i vi h CMOS
VVL
TT
VRH
VVH
Cng I
VNL
TT
VVH
TT
Cng II
VRL
Cng I
VVL
TT
VRH
Cng II
24
Cng chu ti
Cc cng ti
A
B
Cng chu ti
A
B
Cc cng ti
IRL
IRH
a) Mc ra ca cng chu ti l H
b) Mc ra ca cng chu ti l L
+Vcc
ICCH
H
H
H
ICCL
L
Ra
Ra
tTHL
tTLH
TM TT
Trong chng 2 chng ta gii thiu v cc phng php biu din v rt gn hm Boole.
Ngoi ra cn gii thiu mt s cng logic thng dng v cc tham s chnh ca chng.
CU HI N TP
Bi 2.1 Rt gn hm sau theo phng php dng bng Karnaugh:
1. F (A, B, C) = (0, 2, 4, 6,7).
a.
AB + C
b. AB + C
c.
AB + C
d. AB + C
2. F (A, B, C, D) = (0, 1, 8, 9, 10)
a.
BC + D
b. BC + ABD
c.
BC + ABD
d. BC + ABD
2.2 Rt gn hm sau theo phng php i s
1. C D + C D . A C + D
a.
CD
b. CD
c.
CD
d. CD
2. A BC . A B + BC + C A
AB + AC
b. AB + AC + BC
c. AC + BC
a.
d. AB + BC
2.3 Rt gn hm sau theo phng php Quine-Mc.CLUSKEY:
F (A, B, C, D) = (2, 3, 6, 7, 12, 13, 14, 15).
a.
26
AC + AB
AC + AB
d. AC + AB
c.
A
B
a.
b.
c.
d.
Do u bng A+B
Do u bng B
Do u bng AB
Do u bng A+AB
B
Hnh 1
a.
b.
c.
d.
AB + AB
AB + AB
AB + AB
AB + AB
A B = A B + AB
27
AND, OR v NOT
NAND, AND v NOT
AND, NOR v NAND
AND, OR v XNOR
0 v 0
0 v 1
1 v 0
1 v 1
28
A AND B
A XOR B
A OR B
A NAND B
Bo ho.
Khng bo ho.
Trong mch logic bo ho, cc transistor c vn hnh trong vng bo ho, cn trong cc
mch logic khng bo ho th cc transistor khng lm vic ti vng bo ho.
Cc h mch logic lng cc c bo ho l:
Schottky TTL.
PMOS.
NMOS.
CMOS
29
NI DUNG
3.1. CC H CNG LOGIC
3.1.1. H DDL
DDL (Diode Diode Logic) l h cng logic do cc diode bn dn to thnh. Hnh 3-1a,b l
s cng AND, OR 2 li vo h DDL.
+5V
A
B
D1
R1
f
D2
A
B
a) Cng AND
A
B
D1
A
B
D2
R1
b) Cng OR
OR
A (V)
B (V)
F (V)
A (V)
B (V)
F (V)
0,7
0,7
4,3
0,7
4,3
4,7
4,3
2k
4k
D2
D1
D3
5k
Q1
+5V
2k
4k
a)
+5V
+5V
D1
D2
f
D3
A
D4
Q1
5k
B
b)
B (V)
F (V)
5,7
32
+Vcc
R3
300
R2
1,6k
R1
4k
Q3
A
Q1
Q2
D3
A
f
Q4
D1
R4
1k
D2
+Vcc
R2
4k
R1
4k
R3
1,6k
D3
R5
1,6k
R7
130
Q7
Q6
A
Q4
Q1
Q2
D1
D2
D4
f
Q3
Q8
Q5
R4
1 k
R6
1 k
33
Q1
R2
1,6k
Q2
Q3
R3
1,6k
D1
A
B
E
(a)
(b)
Hnh 3-8. K hiu ca cng ba trng thi : (a) cng NOT; (b) cng AND.
Hot ng ca cng NAND 3 trng thi c gii thch bng bng trng thi 3-3. Khi trn
li vo E c mc logic thp, cng hot ng nh mt cng NAND. Trn li ra f s tn ti hai
trng thi cao v thp nh thng l.
34
+5V
R1
4k
R5
130
R3
1,6k
R2
4k
D1
R5
Q4
Q3
Q1
+Vcc
Q4
D2
Li ra Z cao
Q2
Q5
R4
1k
Q5
B
E
a) K hiu Diode
Schottky
b) Cu to bn dn
Schottky
c) K hiu bn
dn Schottky
R3
R2
900
50
Q3
A
Q1
R4
3,5k
Q2
D1
D2
R5
500
Q5
f
Q6
R6
250
Q4
36
VDD
S
Q1
f=A
D
S
Q3
D
Q4
Q2
f= A+B
D
S
G
VSS
Q5
D
VSS
a) Cng NOT
b) Cng NOR
Hnh 3-12. Mch in ca cng NOT v NOR theo cng ngh PMOS.
2. Loi NMOS
VDD
VDD
Q1
Q1
f
f
A
Q2
Q2
A
Q3
B
Q3
B
VSS
a) Cng NAND
VSS
b) Cng NOR
Hnh 3-13. Mch in cng NAND v NOR theo cng ngh NMOS.
37
Q1
D
D
Q1
Q2
D
f
A
Q2
f
Q3
Q4
B
a) Cng NOT
b) Cng NAND
38
S
Vo/Ra
Vo/Rao
Ra/Vo
+5V
Ra/Vo
Q2
iu khin
G
a) Mch in
b) K hiu
Li
vo
+Vcc
D
C
R5
R8
R6
Q8
Q7
A
Q4
Q1
R1
Q2
R2
Q3
R3
Q5
Li ra NOR
Q6
RE
Ra
- 0,9 V
D1
D2
-1,29
R4
Li ra OR
R7
- 1,75 V
R9
-Vcc = - 5V
a) Mch in nguyn l
- 1,4 V - 1,2 V Vo
b) th mc vo/ra
Ti CMOS
12V
= 1, 76mA
6,8k
40
+ 12V
6,8k
TTL h mch
Collector
Ti CMOS
+ 12V
3,3k
iu khin
TTL
B chuyn mc
40109
Ti CMOS
Hnh 3-19. B chuyn mc CMOS cho php s dng hai loi ngun +5V v +12V.
3.2.2. Giao tip gia CMOS v TTL
to ra c giao tip gia h CMOS v TTL th ta phi quan tm n vn chuyn
mc in p cho ti khi trng thi li ra ca CMOS ph hp vi li vo ca TTL. Ta phi m
bo chc chn li ra trng thi L ca CMOS lun lun nh hn 0,8 V(y l in p li vo ln
nht trng thi L ca h TTL). in p li ra trng thi H ca CMOS lun lun ln hn 2
V(y l in p li vo nh nht trng thi H ca h TTL).
a. Cng in p cung cp +5V.
Theo s liu k thut ca IC 74Cxx th trng hp xu nht dng li ra ca CMOS iu
khin TTL l:
IOL MAX = 360A
iu ny c ngha l iu khin CMOS c th cho nhn dng l 360 A khi trng thi L,
l dng vo i vi IC TTL loi Schottky cng sut thp. Mt khc, iu khin CMOS c th
cho dng ngun 360 A, n ln hn mc cn thit iu khin dng vo trng thi H. Nh
vy h s ghp ti gia CMOS v 74LS l bng 1.
41
+ 5V
Ti TTL
iu khin
CMOS
Tng m
CMOS
+ 5V
Ti TTL
Hnh 3-21. iu khin CMOS hot ng thch hp nht vi ngun cung cp +12V.
42
+ 12V
3,3k
iu khin
CMOS
Tng m
CMOS h
cc mng
Ti TTL
TM TT
Chng 3 trnh by cu trc, nguyn l v c im ca cng thng dng. Xut pht t
thc t mch in vi mch ho, nn trng tm ch nghin cu ca chng ta l cc cng c
vi mch ho.
C 2 loi vi mch s ph bin nht : TTL v MOS. TTL l cng ngh in hnh trong nhm
cng ngh transistor bao gm TTL, HTL, ECL, MOS l cng ngh vi mch s dng MOSFET,
trong in hnh l MOS
ng thi trong chng 3 cng a ra vn giao tip gia cc h cng vi nhau.
CU HI N TP
1. Chc nng ca mch logic RTL c s nh hnh v sau:
a. NOR
43
b. OR
c. AND
d. NAND
2. Vi mch c s nh trong cu hi 1, nhng in p logic li vo tng ng vi cc
mc logic cao v thp ln lt l 10 V v 0 V th chc nng ca mch l g?
a. NOR
b. OR
c. AND
d. NAND
3. Cho mch c s nh s sau, in p logic li v tng ng vi cc mc logic cao v
thp ln lt l 1 V v 0 V, nu chc nng ca mch?
a. NOR
b. OR
c. AND
d. NAND
4. Chc nng ca diode D3 trong s sau l g?
a. Cch ly transistor Q3 v Q4
b. Dch mc in p lm cho Q3 v Q4 khng bao gi cng ng hoc cng m
44
c. Chng nhiu li ra
d. Cch ly Q4 khi mch ngoi ni vo u ra f
5. Chc nng ca mch biu din trong s nh cu hi 4 s thay i th no nu diode D3
chuyn ti chn base ca transistor Q3 (cathode D3 ni vi base Q3 cn anode ni vi
collector Q2)?
a. Q3 lun cm
b. Q3 lun m
c. Chc nng ca mch khng thay i
d. Li ra lun trng thi treo
6. Cng collector h s hot ng bnh thng nh cc cng logic bnh thng nu :
a. Mch tr thnh cng NAND vi hai trng thi li ra nh cc cng NAND thng
b. Mch tr thnh cng NOR
45
a. Li vo ny c tnh logic 0
b. Li vo ny c tnh logic 1
c. Mch khng hot ng
d. C ba cch tr li trn u sai
11. So snh cng NOT h MOS v CMOS ta thy :
a. c- C th coi l mc 1
b. c- Phi coi l mc 0
c. Khng c- mch hot ng bnh thng th u vo khng dng phi ni
vi mc logic 0
a. Tn s cng tc nhanh
b. in p ngun nui thp
c. Cng sut tiu th thp
d. chng nhiu cao
47
48
NI DUNG
4.1 KHI NIM CHUNG
Cn c vo c im v chc nng logic, cc mch s c chia thnh 2 loi chnh: mch t
hp v mch tun t (mch tun t c trnh by chng sau).
1) c im c bn ca mch t hp
Trong mch s, mch t hp l mch m tr s n nh ca tn hiu u ra thi im ang
xt ch ph thuc vo t hp cc gi tr tn hiu u vo. c im cu trc mch t hp l c
cu trc nn t cc cng logic. Vy cc mch in cng chng 2 v cc mch logic chng 3
u l cc mch t hp.
2) Phng php biu din chc nng logic
Cc phng php thng dng biu din chc nng logic ca mch t hp l hm s
logic, bng trng thi, s dng logic, bng Cac n (Karnaugh), cng c khi biu th bng th
thi gian dng xung.
i vi vi mch c nh (SSI) thng biu din bng hm logic. i vi vi mch c va
(MSI) thng biu din bng bng trng thi.
S khi tng qut ca mch logic t hp c trnh by hnh 4-1.
x0
x1
Mch logic t
hp
xn-1
Y0
Y1
Ym-1
Ym-1 = fm-1(x0,x1,...,xn-1).
T , ta thy rng c im ni bt ca mch logic t hp l hm ra ch ph thuc cc bin
vo m khng ph thuc vo trng thi ca mch. Cng chnh v th, trng thi ra ch tn ti trong
thi gian c tc ng vo.
Th loi ca mch logic t hp rt phong ph. Phm vi ng dng ca chng cng rt rng.
49
B
0
Biu thc ca hm l: f = A B + A B = A B
hoc
f = AB A AB B
VAC
Hnh 4-2 Mch in ca h thng chiu sng
50
B
0
1
0
1
f
0
1
1
0
00
01
11
10
01
11
10
x1
x2
x3
x4
t1
Mch
logic
f(x)
(x1
x2
x3
x4 )
p ng ra
f(Q) = 1
'
t0
t1
f(0101) = 0
f(P) = 1
thi gian tr
0
x2
0
Q
f(x)
P
1
0
t0
t'0
t
t1
Do c hin tng "chy ua" gia cc tn hiu vo vi nhau trong thi gian chuyn t QP
m xut hin hazard. Nu f(Q) = f(P) tc l c s thay i ca tn hiu vo nhng s iu khin
u ra ca mch logic vn khng i d l 0 hay 1, nhng xut hin hazard, khi s lng tn hiu
chy ua khng nhiu, chnh l hazard tnh.
Hazard nht thi cng chnh l hazard tnh, tc l loi hazard ch xut hin nh mt xung
khng theo quy nh ca hm logic. Hin tng ny khng nguy him, v rng ca xung
hazard tnh t lun nh hn thi gian tr ca mch, nn mch logic vn hot ng bnh thng
d c xut hin hazard.
Nhng hazard tnh nguy him ch: n c th gy ra "sai nhm" cho iu khin ca h
thng logic khi gi tr rng hazard (t) ln, iu ny s xy ra khi s "chy ua" ca tn
hiu vo qu chnh lch, ngha l c tn hiu vo "chy" qu nhanh cn tn hiu khc li "chy"
qu chm, hin tng ny c minh ho hnh 4-6.
x1, x4
0
x2
f(x)
P
t
t
0
t0 t'0
t1
54
Trong thc t khi thay i tn hiu vo ca mch logic ng vi qu trnh chuyn i (QP)
c th c rt nhiu tn hiu vo cng thay i khi c s chy ua ca cc tn hiu vo ti u ra
ca mch. V d trng hp Q = (0000); P = (1101), d dng nhn thy c s chy ua (X)
(X)
(x1 x2
x3
x4)
t0
f(Q) = 1
t'0
f(X') = 0
"
t0
f(X") = 1
t1
f(P) = 0
t
0
f(x)
0
t0 t'0
t"0 t1
55
Hazard c th xut hin do chc nng ca mch trong c hai trng hp l hm f(X) ly gi
tr logic l 0 hoc 1.
Hazard nht thi gi l hazard hm s trong thi gian chuyn i t QP nu:
- f(Q)=f(P)
- Hm f(X) ly c hai gi tr 1 v 0 trong thi gian chuyn i t QP
iu ny c ngha l trong thi gian chuyn i QP th hm logic khng thay i gi tr
(f(Q)=f(P)), nhng nu ly f(Q)=f(P) = 0 th th hazard vn xut hin hoc ly f(Q)=f(P)=1 th
hazard vn xy ra. Hin tng ny c gi l hazard hm s. Trn thc t c nhng hm s
hazard nht thi ch xut hin khi iu khin logic l 1 (f(X) = 1) cn iu khin logic u ra l
0 th khng c hazard nht thi xut hin v ngc li c th iu khin ra khng b hazard.
nguy him ca hazard hm s cng ging nh hazard tnh, nhng n nguy him hn
mt mc na v bt k qu trnh iu khin no (0 hay 1) u c kh nng xut hin hazard, tc l
iu c kh nng gy ra "sai nhm" khi iu khin mch.
4.4.3.4. Hazard logic trong mch logic.
y l loi hazard nguy him nht, hay gy ra iu khin "sai nhm" nhiu nht trong cc
h thng mch t hp iu khin.
Bn cht ca loi hazard ny nh sau:
Khi tp tn hiu vo ca hm logic thay i ng thi nhiu bin trong thi gian chuyn i
Q P, m mi mt ln tn hiu vo c thi gian tr khc nhau, trong qu trnh "chy ua" ny
gp phi trng hp Q = (00000), P = (11101)
(X)
(x1
x2
x3
x4
x5)
t0
'
t0
"
t0
t"'0
0
0
1
1
56
f(X') = 0
1
1
0
0
f(X") = 0
f(X"') = 0
t1
f(Q) = 1
f(P) = 1
(X)
t
0
f(x)
- f(Q)=f(P)
P
t
0
t0 t'0 t"0 t"'0 t1
Hnh 4-8. Hazard logic
t0
t1
Tm li, mi mt mch iu khin c th xut hin nhiu loi hazard, c mch logic c s
lng bin s "chy ua" rt ln nhng hazard li khng xut hin, nhng c mch rt n gin
th hazard li xut hin v gy ra iu khin "sai nhm". V vy mun khc phc c hazard th
phi cn c vo mch in c th ca n, ri dng k thut phn tch pht hin kh nng xut hin
hazard, sau tm cch khc phc hazard. Sau y l mt vi bin php khc phc v hn ch s
xut hin hazard trong h thng logic diu khin.
4.4.4. Cc bin php khc phc Hazard.
x1
x2
x3
2
Hnh 4-10. Phng php khc
phc Hazard
57
59
Thp phn
Gray
Gray d 3
0010
0000
0
0110
0001
1
0111
0011
2
0101
0010
3
0100
0110
4
1100
0111
5
1101
0101
6
1111
0100
7
1110
1100
8
1010
1101
9
1011
1111
10
1001
1110
11
1000
1010
12
0000
1011
13
0001
1001
14
0011
1000
15
Bng 4-3. M Gray v Gray d 3
4.5.1.3. M chn, l.
M chn v m l l hai loi m c kh nng pht hin li hay dng nht. thit lp loi
m ny ta ch cn thm mt bit chn/ l (bit parity) vo t hp m cho, nu tng s bit 1 trong
t m (bit tin tc + bit chn/l) l chn th ta c m chn v ngc li ta c m l.
BCD 8421 BCD 8421chn BCD 8421l
PC
PL
0000 1
0000 0
0000
0001 0
0001 1
0001
0010 0
0010 1
0010
0011 1
0011 0
0011
0100 0
0100 1
0100
0101 1
0101 0
0101
0110 1
0110 0
0110
0111 0
0111 1
0111
1000 0
1000 1
1000
1001 1
1001 0
1001
Bng 4-4. M BCD 8421 chn / l
4.5.2. Mch m ho.
Mch in thc hin vic chuyn tin tc sang m, c gi l mch m ho hay mch ghi
m.
4.5.1.1. Mch m ho t thp phn sang BCD 8421
Vo
Thp
phn
1
2
3
4 Mch
5 m ho
6
7
8
9
Vo thp
phn
0
1
2
3
4
5
6
7
8
9
A
8
B
4
C
2
D
Ra
BCD
8421
Ra BCD
8 4 2 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
+5V
R4
= (8,9)
= ( 4,5,6,7)
C = 2 + 3 + 6 + 7 = (2,3,6,7)
D = 1 + 3 + 5 + 7 + 9 = (1,3,5,7,9)
Cn c h phng trnh, ta xy dng c
mch in ca b m ho. Hoc dng ma trn
diode (cng OR) xy dng
Hoc c th c vit li nh sau (dng
nh l DeMorgan) v dng ma trn diode (cng
AND) xy dng mch:
A = 8+9 = 8 . 9
B = 4+5+ 6+ 7 = 4 . 5 . 6 . 7
C = 2 + 3+ 6 + 7 = 2 . 3 . 6 . 7
D = 1+ 3 + 5 + 7 + 9 = 1 . 3 . 5 . 7 . 9
R3
R2
R1
1
2
3
4
5
6
7
8
9
61
Vo
Ra
Thp phn
A B C D
L1L2L3L4L5L6L7L8L9
8 4 2 1
0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 1
1 0 0 0 0 0 0 0 0
0 0 1 0
x 1 0 0 0 0 0 0 0
0 0 1 1
x x 1 0 0 0 0 0 0
0 1 0 0
x x x 1 0 0 0 0 0
0 1 0 1
x x x x 1 0 0 0 0
0 1 1 0
xx x x x 1 0 0 0
0 1 1 1
x x x x x x 1 0 0
1 0 0 0
x x x x x x x 1 0
1 0 0 1
x x x x x x x x 1
Bng 4-6. Bng trng thi ca b m ho
u tin
Theo bi, s m ho thc hin theo mc u tin t L1 n L9, khi cc tn hiu cng tc
ng th cc tn hiu c mc u tin thp khng tc dng, ngha l bt k mc logic ca n l 0
hay 1 u khng nh hng n li ra nn gi n l iu kin tu chn, k hiu l "x".
Bng trng thi phn nh yu cu thit k, m ho theo cp u tin.
T bng trng thi ta c th vit c biu thc li ra nh sau:
D = 1 ti cc li: + L1 v bng 0 ti cc li L2, L4, L6, L8
+ L3 v bng 0 ti cc li L4, L6, L8
+ L5 v bng 0 ti cc li L6, L8
+ L7 v bng 0 ti cc li L8
+ L9
Nn ta vit c hm D:
D = L1. L 2 . L 4 . L 6 . L 8 + L 3 . L 4 . L 6 . L 8 + L 5 . L 4 . L 6 . L 8 + L 7 . L 8 + L 9
Tng t nh vy ta vit c hm ca B, C v A nh sau:
C = L 2 . L 4 . L 5 . L8 . L 9 + L 3 . L 4 . L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9
B = L 4 . L8 . L 9 + L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9
A = L 8 .L 9
Mch in thc hin vic chuyn t m sang tin tc c gi l mch gii m ho.
62
A0
D0
B gii
m nh
phn
A1
D1
An-1
D2n- 1
74154
A0
A1
A2
A3
E1
E2
Vo
A
Vo
iu
khin
Li ra
hin th ch s ca mt h m phn bt k, ta
c th dng dng c 7 on. Cu to ca n nh ch hnh 4-15.
Cc on c hnh thnh bng nhiu loi vt liu khc nhau,
nhng phi c kh nng hin th c trong cc iu kin nh
sng khc nhau v tc chuyn mch phi ln. Trong k thut
s, cc on thng c dng l LED hoc tinh th lng (LCD).
a
b
f
e
Hnh 4-15 Cu to
dng c 7 on sng
D
C
B
A
Mch
1 gii m
2 7 on
4
8
a
b
c
d
e
f
g
63
MUX
2n 1
X0
X1
Y- Li ra
Xj
X2n-1
X2n-1
An-1 An-2 A0
n li vo iu khin
(a) S khi
Hnh 4-17. B hp knh MUX 2n 1
64
En
Chn mch
Vo
d liu
D7
E1
E2
Vo cho
php
Yj
Li vo X
D0
74151
Vo iu
khin
Y0
Y1
Y0
Y1
MUX
2n 1
A0
A1
A2
Yj
Li vo
Y2n-1
Y2n-1
A0
A1
A2
D
E1
E2
74138
Vo iu
khin
Vo d
liu
Y0
Y7
Vo cho
php
65
Mch cng hay (b cng) l mch s hc nh phn quan trng, v trong x l nh phn phn
ln cc php tnh c thc hin thng qua php cng.
Mch logic thc hin php cng hai s nh phn 1 bit c li nh u vo c gi l mch
ton tng. S khi tng qut ca mt mch ton tng c biu din hnh 4-21.
Theo hnh 4-21 v nguyn l cng hai s nh phn mt bit c trng s bt k, ta c th lp
bng trng thi cho mch ton tng.
Cc hm ra Si , Ci s c dng:
Si = ai bi Ci-1
C i = a i b i C i1 + a i b i C i1 + a i b i C i 1
Ci-1
0
0
0
0
1
1
1
1
hay
Si
bi
Ci
ai
0
0
1
1
0
0
1
1
bi
0
1
0
1
0
1
0
1
Si
0
1
1
0
1
0
0
1
Ci
0
0
0
1
0
1
1
1
Si
Pi
G i Pi
Ci-1
a) Mch in
TT
Ci
Gi
ai bi
b) K hiu
Hnh 4-21 a, b Mch ton tng v k hiu
Mch logic thc hin biu thc li ra tng v li ra nh c trnh by hnh 4-21a v k
hiu ca n l hnh 4-21b.
4.7.2 Mch cng nh phn song song
Ta c th ghp nhiu b cng hai s nh mt bit li vi nhau thc hin php cng hai s
nh phn nhiu bit. S khi ca b cng c trnh by hnh 4-22 v c gi l b cng
song song.
S0
Si
S2
S1
B ton
tng
CRi
CVi
bi
ai
CR2
B ton
tng
CV1 CR0
CV2 CR1
b2
a2
B ton
tng
B ton
tng
b1
a1
66
CV0
b0
a0
ai
bi
ai
0
0
1
1
gi
bi
0
1
0
1
gi
1
0
0
1
vi
g2 = a 2 b2
g1 = a 1 b1
g0 = a 0 b0
4.8.2. B so snh.
4.8.2.1. B so snh 1 bit.
f < = a i . bi
f = = a i bi
f > = a i . bi
67
ai
bi
ai
0
0
1
1
bi
0
1
0
1
f<
0
1
0
0
f=
1
0
0
1
f=
f>
0
0
1
0
f<
f>
a2
b2
f>
a1
b1
a0
b0
Hnh 4-26. Mch in ca b so snh ln hn 4 bit
Mt trong nhng b so snh thng dng hin nay l 7485. IC ny so snh 2 s nh phn 4
bit.
68
Vo
d2
0
0
1
1
0
0
1
1
d3
0
1
0
1
0
1
0
1
n bit d
liu
Ra
Xe Xo
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Xo
To bit
chn/l
Xe
X o = X e = d1 d 2 d 3
4.9.2. Mch kim tra chn/l.
n bit d liu
Kim tra h
chn/l
Fo
Fe
Bit chn l
(Xo, Xe)
d1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Vo
d2 d3
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Fe
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
Ra
Fo
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Fo = d1 d2 d3 X
Fo = Fe
69
Khi logic: Thc hin cc php tnh logic nh l AND, OR, NOT, XOR.
Khi s hc: Thc hin cc php tnh s hc nh l: cng, tr, tng 1, gim 1.
S khi ca 1 n
v s hc logic ALU 4 bit
c m t hnh 4-29:
4
Thanh ghi A
4
Thanh ghi B
4
4
M l li vo chn
Cin
php tnh s hc hay logic.
M
(Mode)
ALU
F0, F1 l hai li vo chn
F0 Chn chc nng
chc nng. Sau khi mt
F1 (Php tnh)
php tnh s hc hay logic
4
4
c thc hin th kt qu
Ghi trng thi
s c ghi ln 1 thanh ghi,
v d thanh ghi A. Kt qu
ny c th c s dng
Hnh 4-29. S khi ca ALU 4 bit
thc hin php tnh sau. B
ALU cn to ra cc bit trng thi chuyn i thanh ghi. V d: Carry out: nu c nh; Zero: nu
kt qu php tnh bng 0.
TM TT
Trong chng ny, chng ta gii thiu mch logic t hp. Mch t hp do cc phn t
logic c bn cu trc nn. c im ca mch t hp l tn hiu u ra thi im bt k no
cng ch ph thuc vo tn hiu u vo thi im m khng lin quan n trng thi vn
c ca mch.
Mch t hp rt phong ph, ta khng th xem xt ht trong chng 4. Trng tm ca chng
ta l nm vng c im mch t hp v phng php chung khi thit k, phn tch mch t hp.
V vy, chng ta gii thiu mt cch chn lc b m ho, b gii m, b hp knh, phn knh,
mch cng, tr, mch so snhtrong qu trnh , ta xem xt phng php phn tch v thit
k mch t hp.
Khi phn tch mch t hp cho, ta c th vit ra hm logic u ra cho tng cp ca s ,
ri tin hnh ti thiu ho hm logic biu th r mi quan h gia u ra vi u vo. Cn
lu thm rng phi xem xt n hin tng Hazard- l hin tng chy ua trong mch logic v
cch khc phc hin tng ny.
70
CU HI N TP
1.
2.
3.
4.
5.
6.
8.
B hp knh c kh nng:
a. ni mt li vo mch vi mt li ra trong mt nhm cc li ra.
b. ni ng thi mt li vo mch vi mt hoc nhiu li ra ca mt nhm cc li ra.
c. ni mt li vo trong mt nhm cc li vo vi mt li ra.
d. ni ng thi mt hoc nhiu li vo vi mt li ra.
9.
10.
U RA
D LIU
U VO
D LIU
(a)
72
(b)
Hnh 4-29.
11.
12.
13.
14.
15.
16.
17.
19.
20.
Mt ALU c cha:
a. Mt khi s hc.
b. Mt khi logic.
c. Mt khi so snh.
d. Mt khi s hc v mt khi logic.
74
NI DUNG
5.1. KHI NIM CHUNG V M HNH TON HC
5.1.1. Khi nim chung
x1
x2
z1
z2
Mch t hp
Ql
zj
W1
Wk
Mch nh
Hnh 5-1. S khi ca mch tun t.
75
X - tp tn hiu vo.
Q - tp trng thi trong trc ca mch.
W - hm kch.
Z - cc hm ra
Trig c t 1 n mt vi li iu
khin, c hai li ra lun lun ngc nhau
l Q v Q . Tu tng loi trig c th c
thm cc li vo lp (PRESET) v li
vo xo (CLEAR). Ngoi ra, trig cn c
li vo ng b (CLOCK). Hnh 5-2 l
s khi tng qut ca trig.
Phn loi:
PR
Q
Cc li vo
iu khin
Clock
CLR
Hnh 5-2. S tng qut ca mt Trig
Theo phng thc hot ng thi ta c hai loi: trig ng b v trig khng ng
b. Trong loi trig ng b li c chia lm hai loi: trig thng v trig chnh
- ph (Master- Slave).
76
TRIG
TRIG
TRIG D
TRIG T
TRIG RS
NG B
KHNG NG
TRIG JK
CHNH - PH
LOI THNG
Hnh 5-3.
5 2.1.1. Trig RS
S
Clock
>C
R
a)
b)
Hnh 5-4. S k hiu ca trig RS
Qk
Mod hot ng
Qk
Mod hot ng
Nh
Nh
Xo
Nh
Lp
Xo
Cm
Lp
Cm
R
S
S
Q
Q
R
77
Qk
Ck
Nh
Ck
Xo
Ck
Lp
Ck
Mod hot ng
Q
C
C
Q
C
Q
C
Q
78
T
Qk
C
Q
Q
Hnh 5-8. S nguyn l v k hiu ca trig T
Nhn xt: T cc bng trng thi ca cc trig trn ta thy rng: Cc trig D v RS c
th lm vic c ch khng ng b v mi tp tn hiu vo iu khin D, RS
lun lun tn ti t nht 1 trong 2 trng thi n nh. Trng thi n nh l trng thi
tho mn iu kin Qk = Q. Cn trig T v trig JK khng th lm vic c ch
khng ng b v mch s ri vo trng thi dao ng nu nh tp tn hiu vo l 11
i vi trig JK hoc l 1 i vi trig T. Nh vy, trig D, trig RS c th lm vic
c hai ch : ng b v khng ng b cn trig T v trig JK ch c th lm vic
ch ng b.
> TRIG
79
C 4 loi trig c gii thiu l trig RS, JK, D v T. Trn thc t c khi trig loi ny
li c s dng nh trig loi khc. Ni dung phn ny l xy dng cc trig yu cu t cc
trig cho trc.
Vi 4 loi trig trn th c 12 kh nng chuyn i sang nhau.
D
RS
JK
Mt trong cc phng php xy dng trig loi X t loi Y cho trc c cho s
khi hnh 5-11.
Cc li vo X l cc li vo ca trig loi X cn thit k. Li ra ca mch logic l cc li
vo ca trig Y cho trc. Nh vy, bi ton chuyn i t trig loi Y sang trig loi X l xy
dng mch t hp c cc u vo l X v Q; cc li ra l Y biu din bi h hm:
Y = f (X, Q)
thc hin chuyn i trig loi Y sang loi X cn thc hin cc bc sau:
Ti thiu ho cc hm ny v xy dng cc s .
Mch
logic t
hp
Q
Trig
loi Y
80
Qk
RS
JK
X0
0X
01
1X
10
X1
0X
X0
00
0
X
01
0
0
11
1
0
JK
Q
0
1
10
1
X
00
X
0
01
X
1
11
0
1
10
0
0
R = KQ
S = JQ
Bng 5-6. Bng tnh S v R
K
J
Bng chuyn i trng thi bao gm cc hng v cc ct, cc hng ghi cc trng thi trong,
cc ct ghi cc gi tr ca tn hiu vo. Cc ghi gi tr cc trng thi trong k tip m mch s
chuyn n ng vi cc gi tr hng v ct. Bng chuyn i trng thi c m t bng 5-6.
Tn hiu vo
V
V1
V2
Vn
Trng thi
k tip Qk
S
S1
Trng
thi
trong
S2
:
:
Sn
Bng 5-6. Bng chuyn i trng thi
Cc hng ca bng ghi cc trng thi trong, cc ct ghi cc tn hiu vo. Cc ghi gi tr
ca tn hiu ra tng ng. Bng tn hiu ra c m t bng 5-7.
V
V1
Trng
thi
trong
Tn hiu vo
V2
.
Vn
Tn hiu
ra - R
S1
S2
:
:
Sn
Bng 5-7. Bng tn hiu ra
C th gp hai bng chuyn i trng thi v bng tn hiu ra thnh mt bng chung gi l
bng chuyn i trng thi / ra. Lc trn cc ghi cc gi tr ca trng thi k tip v tn hiu
ra (Sk / R) tng ng vi trng thi hin ti v tn hiu vo.
Bng chuyn i trng thi v tn hiu ra c m t bng 5-8.
Tn hiu vo
V
V1
V2
Vn
S
5.3.2.
hnh trng
thi.
82
Trng
thi
trong
S1
S2
:
:
Sn
Bng 5-8. Bng chuyn i trng thi v tn hiu ra
Trng thi k
tip Sk v
Tn hiu ra R
Bi ton ban u
Hnh thc ho
M ho trng thi
H hm ca mch
83
in.
5.4.1.1. Cc bc thit k
Sau y gii thiu thut ton xc nh phng trnh li vo kch cho cc trig t hnh
trng thi.
i vi trig Qi bt k s thay i trng thi t Qi n Qki ch c th c 4 kh nng nh hnh
5-16.
Qi = 0
0
Qi = 1
1
2
3
Hnh 5-14. Cc cung biu din s thay i trng thi t Qi n Qki ca trig Qi
01
1
11
3
10
2
Q'1
100
000
0
Q'3
Q'1Q'2Q'3
011
001
Q'2Q'3
3
Q'3
010
01
11
0
1
Q2Q3
Q1
00
10
1
x
Q2Q3
Q1
00
1
01
11
10
1
10
1
x
11
D2 = Q 2 Q 3 + Q 2 Q 3 = Q 2 Q 3
D1 = Q2Q3
01
D3 = Q1 Q 3
D3 = Q1 Q 3
b) Xc nh phng trnh kch cho Trig T.
Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3
Q2Q3
Q1
Q2Q3
00
01
0
1
11
10
Q1
1
1
00
01
11
10
x
T2 = Q3
T1 = Q1 + Q2Q3
Q2Q3
Q1
00
01
11
10
1
T3 =
Bng 5-10.
Q1
Ch khi vit cc biu thc Ton, Toff ca trig th I ta cn phi n gin cc biu thc v
a v dng:
Ton = ( T* ) Q i rt ra Ji = T*.
Toff = ( T** ) Q i rt ra Ki = T**.
Vit cc biu thc Ton, Toff cho cc trig v t xc nh phng trnh kch cho cc trig
nh sau:
87
Q2Q3
00
01
11
0
1
10
1
x
Q1
00
01
11
10
10
J1 = Q2Q3
K1 = 1
Q2Q3
Q2Q3
Q1
00
01
11
10
x
Q1
00
01
11
K 2 = Q3
J2 = Q 3
Q2Q3
Q2Q3
Q1
00
01
11
10
Q1
00
01
11
10
J3 = Q1
K3 = 1
Bng 5-11. Bng tm hm kch
K2 = Q3
J3 = Q1 ;
K3 = 1
88
Q2Q3
00
01
11
10
S1 = Q2Q3
00
01
11
10
x
R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3
Q2Q3
Q 2Q 3
Q1
Q1
00
01
11
x
10
Q1
00
01
11
10
1
x
01
11
10
R2 = Q2 Q3
S2 = Q 2 Q 3
Q2Q3
Q2Q3
Q1
00
01
11
x
10
Q1
00
x
R3 = Q 2 Q3
S3 = Q1 Q 3
Bng 5-12. Bng tm hm kch
; R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3
S2 = Q 2 Q3 ; R2 = Q2 Q3
S3 = Q1 Q 3
; R3 = Q 2 Q3
Cc bc thc hin:
89
Sk
Q2Q3
Qk
RS
JK
Q1
00
01
11
10
X0
0X
01
1X
10
X1
0X
X0
a) Bng chuyn
i trng thi
Q1
Q2
Q3
Qk 1
Qk2
Qk3
D1
D2
D3
T1
T2
T3
R1S1
R2S2
R2S3
J1K1
J2K2
J3K3
X0
X0
01
0X
0X
1X
X0
01
10
0X
1X
X1
X0
0X
01
0X
X0
1X
01
10
10
1X
X1
X1
10
X0
X0
X1
0X
0X
X XX XX XX XX XX XX
X XX XX XX XX XX XX
X XX XX XX XX XX XX
Bi ton phn tch l bi ton xc nh chc nng ca mt mch cho trc. Khi tin hnh
phn tch cn tun theo cc bc sau:
- S mch: T s cho trc cn xc nh chc nng tng phn t c bn ca s ,
mi quan h gia cc phn t .
- Xc nh cc u vo v ra, s trng thi trong ca mch: Coi mch nh mt hp en
cn phi xc nh cc u vo v ra ca mch, c im ca cc u vo, u ra. xc nh
c s trng thi trong ca mch cn phi xc nh xem mch c xy dng t bao nhiu phn
t nh (trig JK) t xc nh c s trng thi trong c th c ca mch.
Gi s trig l n th s trng thi c th c ca mch l 2n.
- Xc nh phng trnh hm ra, phng trnh hm kch ca cc trig.
- Lp bng trng thi, bng ra nh phn l bng biu din mi quan h trng thi k tip,
tn hiu ra nh phn vi trng thi hin ti v cc tn hiu vo tng ng .
Q0
J0 Q 0
>
>
1
K0 Q 0
Clock
J1 Q 1
X
Q0
K1 Q1
Q0
Q1
Hnh 5-17a)
Q0k = J 0 Q0 + K 0 Q0 = Q1 Q0
Q1k = J1 Q1 + K1 Q1 = Q0 Q1 + X + Q0 Q1 = Q0 Q1 + X Q0 Q1
T cc phng trnh trn ta lp c bng chuyn i trng thi
Trng thi
hin ti
S0
S1
S2
S3
Q0Q1
00
01
11
10
Tn hiu ra
X=1
Q0Q1
01
11
00
00
X=0
Z
0
0
1
0
X=1
Z
0
0
1
0
S0
S1
00
01
X
011
011
Tm li, mch cho s trn c chc nng kim tra dy tn hiu vo X dng chui c
di bng 3. Nu chui tn hiu vo c dng l 1 trong 4 dy: 010, 011, 110 v 111 mch s cho
tn hiu ra Z = 1 ti thi im c xung nhp th 3. rng ca tn hiu ra Z bng rng xung
nhp (Z = C Q1 Q0).
X
Clock
0
1
1
2
0
2
1
3
1
1
Z = C Q1 Q0
Z = Q1 Q0
Thit k mch tun t thc hin nhim v kim tra dy tn hiu vo dng nh phn c
di bng 3 c a vo lin tip trn u vo X. Nu dy tn hiu vo c dng l 010 hoc
011 hoc 110 hoc 111 th Z = 1. Cc trng hp khc Z = 0.
Bc 1: Xc nh bi ton. Mch c thit k c nhim v pht hin tn hiu vo. Khi
nhn c 1 trong cc dy tn hiu trn th mch s bo rng nhn c.
Mch phi thit k l mch ng b, nn s c cc li vo l X- tn hiu vo, Ck- xung nhp
iu khin, Z tn hiu ra.
Bc 2: Xy dng hnh trng thi, bng chuyn i trng thi
Gi s trng thi ban u l S0:
Khi tn hiu vo l X. Ck th mch s chuyn ti trng thi S1. Khi tn hiu vo l X . Ck
mch s chuyn n trng thi S2.
Tng t nh vy. Khi mch trng thi S1 th khi c tn hiu X. Ck mch chuyn n
trng thi S3 v chuyn n trng thi S4 khi c tn hiu X . Ck. Tng t ta xy dng c
hnh sau 5-18 a.
S0
S2
S1
S3
S4
X
S5
S6
Z=1
Z=1
Nu mch 1 trong 4 trng thi S3, S4, S5, S6: khi c tn hiu vo X. Ck hoc X . Ck th
mch s chuyn v trng thi ban u S0. Khi dy tn hiu vo l 110 hoc 111 (ng vi ng
chuyn i trng thi l S0 S1 S3 S0) hay khi dy tn hiu vo l 010 hoc 011 (ng vi
ng chuyn i trng thi l S0 S3 S5 S0) th mch s cho tn hiu ra Z = 1 ti thi im
xung th 3. Vi cc ng chuyn i khc Z = 0.
T hnh trng thi ta xy dng c bng chuyn i trng thi nh sau:
94
Sk
X=0
X=1
X=0
X=1
S0
S2
S1
S1
S4
S3
S2
S6
S5
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0
Trng thi Si c gi l trng thi tng ng vi trng thi Sj (Si Sj) khi v ch khi:
nu ly Si v Sj l hai trng thi ban u th vi mi dy tn hiu vo c th chng lun cho dy tn
hiu ra ging nhau.
Nu c nhiu trng thi tng ng vi nhau tng i mt th chng tng ng vi
nhau (tnh cht bc cu). kim tra mt nhm cc trng thi xem chng c tng ng vi
nhau khng, c th s dng bng trng thi v tn hiu ra nh sau:
-
Nhm cc trng thi tng ng phi c nhng hng trong bng tn hiu ra ging
nhau.
Nhm cc trng thi tng ng phi c nhng hng trong bng trng thi cng
mt ct (ng vi cng mt t hp tn hiu vo) l tng ng. Ngha l ng vi
cng mt t hp tn hiu vo cc trng thi k tip ca chng l tng ng.
Quy tc Caldwell:
Nhng hng (tng ng vi trng thi trong) ca bng chuyn i trng thi v tn hiu ra
s c kt hp vi nhau v c biu din bng mt hng chung - c trng (trng thi c
trng) cho chng nu nh chng tho mn hai iu kin sau:
1. Cc hng tng ng trong ma trn ra ging nhau.
2. Trong ma trn ra, cc hng tng ng phi tho mn 1 trong 3 iu sau:
-
Sau khi thay th cc trng thi tng ng bng mt trng thi chung c trng cho
chng, lp li cc cng vic tm cc trng thi tng ng khc cho n khi khng th tm c
95
S0
S1
S2
Z=0
S1
Z=0
Z=0
S0
S0
Z=0
Z=1
S46
Z=0
S35
S0
S0
Z=0
S35
S46
Z=0
Z=0
S35
Z=0
S12
S35
S46
S12
S12
Z=0
S35
S46
S2
S0
Z=1
S46
S0
S0
Z=1
Z=1
Z=0
Z=0
S0
S0
Z=0
Z=0
Bc 4: Sau khi gp hai trng thi S1 v S2 thnh trng thi chung S12 th mch ch cn 4
trng thi S0, S12, S35, S46. M ho 4 trng thi ny bng hai bin nh phn Q1 v Q0.
Q0
Q1
M ho S
S0
S12
S35
S46
Bc 5: Xc nh h phng trnh ca
mch.
C hai cch xc nh h phng trnh
00
S0
S12
01
X
X
S46
10
11
S35
Z=1
ny.
Cch 1:
Da vo bng chuyn i trng thi ta lp bng hm kch 5-13 cho hai trig Q0 v Q1.
96
Trng thi k
tip
Cc u vo ca trig
X=0
X=1
Q0Q1
Q0Q1
Q0Q1
J0
K0
J0
K0
J1
K1
J1
K1
00
01
01
Z=0
Z=0
10
11
Z=0
Z=0
00
00
Z=1
Z=1
00
00
Z=0
Z=0
01
11
10
X=0
X=1
X=0
X=1
Q0Q1
X
00
01
11
10
00
01
11
10
K0 = 1
J0 =Q1
Q0Q1
Q0Q1
00
01
11
00
01
11
10
10
K1 = X + Q 0
J1 = Q 0
Q0Q1
X
00
01
11
10
Z = X Q0Q1
97
JQ = T*
J 0 = Q1
K 0 =1
TonQ1 = S0 X = Q0 Q1
J1 = Q0
K1 = Q 0 X + Q 0 = X + Q 0
Q0
J0 Q 0
>
K0 Q 0
X
Q0
J1
Q1
>
K1 Q1
Q0
Q1
Clock
Bc 6: V s thc hin.
Sau y l ni dung ca tng phng php.
Cch 1: Da vo bng chuyn i trng thi.
99
Qk = S + R Q
Ak = S A + R A A
RN = 1N (A , N , X1, X2Xm )
SN = 2N (A , N , X1, X2Xm )
Z1 = 1 (A , N , X1, X2Xm )
Z2 = 2 (A , N , X1, X2Xm )
100
Li ra
X1
X2
Mch logic
X1 X 2
X1 X 2
S0
Trng
thi tnh
X1X2
X1 X 2
S3
X1 X 2
X1 X 2
X1 X 2
X1 X 2
X 1X 2
X1 X 2
Z=1
S2
ng vo
S4
ng ra
Hnh 5-19 c) hnh trng thi
Trng thi
hin ti
S0
X2
0
S0
X1
0
X1
1
Z=0
S0
S2
Z=0
S3
Z=0
S4
S1
Z=0
S3
S0
X2
0
Z=0
S2
S2
X1
1
S1
Z=0
S3
X2
1
S3
Z=0
S1
X2
1
Z=0
S1
Z=1
Z=0
S4
Z=0
S3
Z=0
S4
Z=0
S1
Z=0
Z=0
Trng thi
hin ti
S012
S34
X1 X2
1
1
S012
Z=0
Z=0
S34
S34
Z=0
Z=0
X1
0
S34
X2
1
X2
X1
1
0
S012
Z=0
S012
Z=0
X1 X 2
S012
S34
Z = X1X2
A=0
A=1
X2
RA = A X 2 + A X 1 X 2 + A X 1 X 2 = X 2
Cc cung [(0)], [(1)] c ly gi tr khng xc nh (x) v c dng ti thiu ho.
Phng trnh c trng ca trig RS
Q k = S A + RA QA
Thay gi tr ca RA, SA vo biu thc thu c kt qu:
Ak = X 1 X 2 + X 2 A = X 1 X 2 + X 2 A = X 1 X 2 . X 2 A
Phng trnh ra:
103
Z k= A XA1 X 2
X1
A
X2
X1
X2
X1
X2
S A = X1 X 2
RA = X 2
Si2
Si3
Sin
Trn bng trng thi hin tng chu k c th hin ch: ct ng vi t hp tn hiu vo
khng c trng thi no c khoanh trn (khng c trng thi no n nh).
104
X+X
S3
X+X
S2
S0
S2
S1
S1
S2
S2
S2
S3
S3
S3
S3
S0
S0
S1
S2
Hin tng chy ua trong mch khng ng b l hin tng: do tnh khng ng nht
ca cc phn t nh phn dng m ho trng thi, v mch hot ng khng ng b, khi mch
chuyn trng thi t Si Sj mch c th chuyn bin trng thi theo nhng con ng khc nhau.
Nu trng thi cui cng ca nhng con ng l n nh v duy nht th chy ua
khng nguy him. Ngc li, chy ua nguy him l nhng cch chuyn bin trng thi khc nhau
cui cng dn n cc trng thi n nh khc nhau, c th ti trng thi kho v khng thot
ra c.
V d: Chy ua khng nguy him: Mt mch tun t khng ng b c bng trng thi m
t hnh 5-22 .
Nhn vo bng ta thy nu mch ang trng thi S0 (AB = 00) tn hiu vo X thay i t 0
1 mch s chuyn trc tip ti trng thi S2 (AB = 01) v nu X vn bng 0 trng thi tip
theo ca mch s l S3, n s l trng thi n nh cui cng ca mch nu nh X vn bng 0.
Mch c th thay i trng thi theo nhng con ng khc nhau tu thuc vo th t thay
i (hay thi gian qu ) ca A v B
105
A thay i
trc B
AB S
00 S0
S2
S1
01 S1
S2
S2
11 S2
S3
S3
10 S3
S3
S0
B thay i
trc A
A, B cng
thay i
S0
X
AB
10
S3
11
X 01
S1
S2
S AB
S0
00
S0
S1
S2
01
S0
S2
S1
11
S2
S1
S3
10
S3
S3
B thay i trc
A, B thay i
ng thi
A thay i trc
Ti thiu ho trng thi l gim bt s trng thi (nu c th) mch thit k l n gin
v do vy tin cy hn.
i vi cc trng trong bng chuyn i trng thi (nhng ny ng vi t hp tn hiu
vo khng xut hin) c th ly gi tr tu chn kt qu ti thiu ho l ti gin.
5.7.3.2. M ho trng thi
S0
S1
AB
00
S0
11
S2
a) hnh trng thi ban u
S1
01
01
X
11
10
S3
S2
B m
H s m = M
Hnh 5- 25 S khi ca b m
X / 0
1
X / 0
X / 0
M-2
M-1
X / 1
Khi khng c tn hiu vo m (X) mch gi nguyn trng thi c, khi c tn hiu m th
mch s chuyn n trng thi k tip.
Tnh cht tun hon ca b m th hin ch: sau M tn hiu vo X th mch li quay tr
v trng thi xut pht ban u.
Tn hiu ra ca b m ch xut hin (Y = 1) duy nht trong trng hp: b m ang
trng thi M - 1 v c tn hiu vo X. Khi b m s chuyn v trng thi 0.
108
C nhiu cch phn loi b m. Hnh 5-27 l cch phn loi in hnh ca b m.
ng b
Phn theo cch hot ng
Khng ng b
m tin
m li
M = 2N
Phn theo h s m
B
m
M 2N
Khng lp trnh
Phn theo cc to M
Lp trnh
M nh phn
M NBCD
Phn theo m
Hnh 5-27. S phn loi b m
M Gray
M Johnson
M vng
5.8.1.2. Cc bc thit k b m
Xc nh s trig ca b m (n) M
ho trng thi theo m cho
S
Hnh 5-28. Cc bc thit k b m
109
Thit k b m nh phn ng b c M = 4.
Do M = 4 nn lp c hnh trng thi hnh 5-29.
S0
Q 1Q 0
S1
S2
S3
00
01
10
11
Hnh 5-29
n +1
Trig Q1
Trig Q0
Q1 Q0 Qk1 Qk0 R1 S1 J1 K1 T1 R0 S0 J0 K0 T0
0
Bng 5-16
Ti thiu ho hm kch ca cc trig, nhn c kt qu:
R0 Q0
R1 Q1
>
>
S0 Q 0
S1 Q 1
Clock
'1'
J0 Q 0
J1 Q 1
>
>
K0 Q 0
K1 Q 1
'1'
T0 Q0
T1 Q1
>
>
Q0
Clock
Clock
i vi trig Q0:
R0 = Q0; S0 = Q 0
110
Q1
Thit k b m ng b c M = 5.
Do M = 5 nn lp c hnh trng thi nh hnh 5-31.
S0
Q2 Q1Q0
S1
S2
S3
S4
000
0 01
010
011
100
n+1
Q2 Q1 Q0
Qk2
Qk1
Qk0
J2
K2
J1
K1
J0
K0
111
n+1
Q2
Q1
Q0
Qk2
Qk1
Qk0
'1'
J0 Q 0
J1 Q 1
J2 Q 2
>
>
K1 Q1
>
K0 Q 0
'1'
K2 Q 2
Clock
B. B m khng ng b.
B. 1. B m nh phn
Cc b m ny c s rt n gin vi c im:
- Ch dng mt loi trig T hoc JK. Nu dng trig T th li vo T lun c ni vi mc
logic '1', nu dng trig JK th J v K c ni vi nhau v ni vi mc '1'.
- u ra ca trig trc c ni vi li vo xung nhp ca trig sau k tip. Khi m tin
th ly u ra Q, khi m li th ly u ra Q (vi gi thit xung Clock tch cc ti sn m
).
- Tn hiu vo X lun c a ti li vo xung nhp ca trig c trng s nh nht.
V d i vi b m nh phn khng ng b M = 2n dng cc trig Q0, Q1 Qn-1 vi Q0
l bit c trng s nh nht, Qn-1 l bit c trng s ln nht, ta c:
- Khi m tin: CQo = X; CQ1 = Q0CQn-1 = CQn-2.
- Khi m li: CQo = X; CQ1 = Q 0 CQn-1 = C Qn 2
S ca b m nh phn khng ng b 3 bit (M = 8 - m tin) dng trig JK c cho
hnh 5-33
'1'
Clock
J0 Q 0
'1'
K0 Q 0
'1'
'1'
K1 Q1
J2 Q 2
>
>
>
'1'
J1 Q 1
'1'
K2 Q 2
112
V d: Thit k b m M = 5 khng ng b.
T yu cu bi ton ta xy dng s khi v hnh trng thi nh hnh 5-34.
Li ra
C
M = 5
Xung m
S0 S1 S2 S3 S4
a) S khi ca b m Mod 5
Q0
Q1
Q2
C1 = C ; C2 = Q0 ; C3 = C;
- Tm h phng trnh:
Q1Q0
Q1Q0
Q2
00
01
11
10
Q2
00
01
11
10
001
010
100
011
000
Qk0 = Q 2 Q 0
Q1Q0
Q1Q0
Q2
00
01
11
10
Q2
00
01
11
10
Qk1 = Q1
Qk2 = Q 2 Q1 Q0
113
n+1
Q2
Q1
Q0
Qk2
Qk1
Qk0
J0 Q 0
'1'
K0 Q 0
>
>
>
'1'
J2 Q 2
J1 Q 1
'1'
K1 Q1
'1'
K2 Q 2
Clock
D0 Q0
D1 Q1
D2 Q2
D2 Q2
>
>
>
>
Q1
Q0
Q2
Q3
Clock
Vo ni tip, ra song song: thng tin c a vo thanh ghi dch tun t tng bit
mt, s liu c a ra ng thi tc l tt c n trig ca thanh ghi c c cng
mt lc.
B ghi dch c s dng rng ri nh d liu, chuyn d liu t song song thnh ni
tip v ngc li. B ghi dch l thnh phn khng th thiu c trong CPU ca cc h vi x l,
trong cc cng vo/ra c kh nng lp trnh.
115
Trong phn ny ta gii thiu b ghi dch 4 bit np vo ni tip hoc song song, ra ni tip
v song song, dch phi.
S b ghi dch ny c trnh by trn hnh 5- 37.
B ghi dch ny c th np thng tin vo ni tip hoc song song. u ra ni tip c ly
ra trig cui cng, u ra song song c ly ra ng thi trn c 4 trig. Vic np thng tin
vo song song c thc hin bi mt trong hai u vo Preset 1 v Preset 2 (y l 2 li vo
ph). Trc khi lm vic cn phi xo tt c cc trig v trng thi '0' nh li vo Clear. Thng tin
trong b ghi dch ny c dch phi.
TM TT
Khc vi mch logic t hp, mch logic tun t c tn hiu u ra ph thuc khng nhng
tn hiu u vo thi im xt m c vo trng thi mch in sn c thi im . y l c
im chc nng logic ca mch tun t. nh trng thi mch in, mch tun t phi c phn
t nh - l cc trig.
1-
Trig l linh kin logic c bn ca mch s. Trig c hai trng thi n nh, di tc dng
ca tn hiu bn ngoi c th chuyn i t trng thi n nh ny sang trng thi n nh kia, nu
khng c tc dng tn hiu bn ngoi th n duy tr mi trng thi n nh vn c. V th, trig c
th c dng lm phn t nh ca s nh phn.
2-
Chc nng logic v hnh thc cu trc ca trig l hai khi nim khc nhau. Chc nng
logic l quan h gia trng thi tip theo ca u ra vi trng thi hin ti ca u ra v cc tn
hiu u vo. Do chc nng logic khc nhau m trig c phn thnh cc loi RS, D, T, JK. Cn
do hnh thc cu trc khc nhau m trig li c phn thnh loi trig thng v loi trig chnh
ph.
Mt trig c chc nng logic xc nh c th thc hin bng cc hnh thc cu trc khc
nhau. V d, cc trig cu trc loi chnh ph v loi thng u c th thc hin chc nng ca
mt trig khc. Ngha l cng mt cu trc c th m trch nhng chc nng khc nhau.
Mch tun t c th c rt nhiu chng loi. Chng ny ch gii thiu mt s loi
3mch tun t in hnh: b m, b ghi dchng thi vi vic nm vng cu trc, nguyn l
cng tc v c im ca cc mch tun t , chng ta cng phi nm vng c c im
chung ca mch tun t v phng php chung khi phn tch v thit k mch tun t.
CU HI N TP CHNG 5
1. Cho cc trig c bn loi RS, JK, D v T. Loi trig no trong s cc loi ny c th
thc hin c m khng cn tn hiu ng b.
a. Trig RS v trig D.
116
CC LI RA HOT
NG MC THP
CC LI VO PHT XUNG
HOT NG MC CAO
CC LI RA D LIU
HOT NG MC THP
CC LI VO D LIU
HOT NG MC CAO
HOT NG MC THP
Hnh 1
xo tt c 6 li ra ca IC.
b. lp tt c 6 li ra ca IC.
c.
Ch xo cc li ra t QD n QA.
d. Ch xo cc li ra CARRY v BORROW.
16. Nu cc li vo ca LS 193 c gi tr l 1010, th cc li ra ca b m s l:
a. hin th gi tr 1010 sau khi chc nng LOAD c kch hot.
b. hin th gi tr 0101 l gi tr o ca 1010 sau khi chc nng LOAD c kch
hot.
c. hin th gi tr 1010 sau mt xung clock.
d. s tng ln nhng khng th gim xung.
17. Cc li ra CARRY v BORROW ca b m LS 193:
a. bnh thng mc thp v s pht ra mt xung hot ng mc cao.
b. c th c a ln mc cao bng cch kch hot chc nng LOAD.
c. c th c a xung mc thp bng cch kch hot chc nng CLEAR.
d. bnh thng mc cao v s pht ra mt xung hot ng mc thp.
18. Trn b m LS 193, b m thc hin m tin:
a. nu chn DOWN c cp xung v chn UP ni ln VCC.
119
'1'
J0 Q 0
J1 Q 1
J2 Q 2
>
>
>
K0 Q
K1
K2 Q
Hnh 2
Clock
a. Mod 5.
b. Mod 6.
c. Mod 7.
d. Mod 8.
34. Cho b m hnh 3. Cho bit y l b m Mod my?
J0 Q 0
Clock
122
'1'
>
'1'
K0 Q 0
'1'
J1 Q 1
J2 Q 2
>
>
K2 Q 2
K1 Q1
'1'
Hnh 3
a. Mod 5.
b. Mod 6.
c. Mod 7.
d. Mod 8.
35. Cho b m hnh 4. Cho bit y l b m Mod my?
'1'
J0 Q 0
J1 Q 1
J2 Q 2
>
>
>
K0 Q
K1
K2 Q
Hnh 4
Clock
a. Mod 5.
b. Mod 6.
c. Mod 7.
d. Mod 8.
36. Thit k b m Mod 9 ng b.
37. Thit k b m Mod 9 khng ng b.
38. B ghi dch ca bn c reset. Sau 4 sn dng ca xung clock tt c 4 li ra u
mc cao. Kt lun ca bn v cc li vo d liu l:
a.
c t mc thp.
b.
c.
d.
c t mc cao.
39. Nu mch ca bn c thit k dch tri d liu vo ni tip, sau lung bit d
liu chuyn ng t:
a. Tri qua phi.
b. T phi qua tri.
123
124
B a hi n n (mt nhp).
NI DUNG
6.1. MCH PHT XUNG
6.1.1. Mch dao ng a hi c bn cng NAND TTL
Cng NAND khi lm vic trong vng chuyn tip c th khuch i mnh tn hiu u vo.
Nu 2 cng NAND c ghp in dung thnh mch vng nh hnh 6-1 ta c b dao ng a
hi.VK l u vo iu khin, khi mc cao mch pht xung, v khi mc thp mch ngng
pht.
Khi , cng I nhanh chng tr thnh thng bo ho, cng II nhanh chng ngt, mch bc
vo trng thi tm n nh. Lc ny, C1 np in v C2 phng in theo mch n gin ho c
th hin trong hnh 6-2. C1 np n khi Vi2 tng n ngng thng VT, trong mch xut hin qu
trnh phn hi dng nh sau:
126
V H2
V H2
R1
R f2
V L1
EC
R f2
R1
V i2
C1
V i2
EC
V L1
+
-
C1
C2
R f1
V H2
V H2
C2
V L1
V i1
V i1
R f1
V L1
V thi gian np in nhanh hn thi gian phng, nn thi gian duy tr trng thi n nh
tm thi ph thuc vo thi gian np in ca hai tu in C1 v C2. T hnh 6-2 ta c thi gian np
in ca tu C1 l 1 = (Rf2 // R1) C1, thi gian Vi2 np in n VT l:
t M 2 = (R f 2 // R 1 )C1 ln
T 2(R f // R 1 )C
T l chu k ca tn hiu a hi li ra.
127
Hnh 6-7a l mch dao ng a hi c bn s dng hai cng NOR CMOS v cc linh kin
nh thi tr v t. Gin xung ca mch c th hin trn hnh 6-7b. Chu k dao ng ca
mch c tnh gn ng nh sau:
128
ED
E
+ D
T = T1 + T2 = RC ln
E D VT VT
Nu gi thit VT = ED/2 th T1 = T2, khi T = RCln4 1,4RC.
EC
R1
Vi
R2 R4
D1
R5
T2
D0
u vo
R7
T4
D3
T1
Vo
T 3 D4
T5
R3
Mch Schmit
R6
u Ra
129
Kt qu mch in nhanh chng lt sang trng thi T1 ngt, T2 thng bo ho. Chng ta gi
gi tr in p u vo VI trong qu trnh tng ln ca n t n ngng lm lt mch schmit
u ra t mc cao xung mc thp l ngng trn VT+ v gi tr ngc li l ngng di ca
trig schmit VT-(hnh 6- 9). Hiu in p tng ng vi ngng trn v ngng di c gi l
chnh lch in p chuyn mch V = VT+ - VT-.
Trig schmit thc cht l mt b so snh hai ngng nn n c dng ng dng khc nhau
nh: Cc mch dao ng, cc mch so snh, lc nhiu v.v..
6.3. MCH A HI I
Mch a hi i c mt trng thi n nh v mt trng thi tm n nh. Khi c tc dng
ca xung ngoi, mch c th chuyn i t trng thi n nh sang trng thi tm n nh. Sau khi
duy tr mt thi gian, mch s t ng quay li trng thi n nh. Thi gian tm n nh ph
thuc vo cc thng s ca mch m khng ph thuc vo xung kch. Mch a hi c ng dng
trong cc mach nh thi, to dng xung, tr v.v..
6.3.1. Mch a hi i CMOS
1. Mch a hi i kiu vi phn
ED
R
Vo1
VI
V i2
Vo
130
ED
VI
ED
VO1
ED
VT
VI2
ED
VO2
TW
Hnh 6-10 l s nguyn l ca mach a hi i kiu vi phn. Ti trng thi n nh, VI=0
th VO1=ED, VI2=ED, VO2=0. Khi c mt xung kch thch li vo lm cho cng 1 nhanh chng cm
v li ra bng 0, xem gin 6-11. Mch in RC s np in cho t in C. Trong qu trnh np,
in p VI2 tng dn n ngng VT v lm cng 2 ng, in p VO2=0. Khi , cng 1 nhanh
chng chuyn v trng thi cm v lm cho mch a hi i tr v trng thi n nh.
rng xung ti u ra ca mch c xc nh bng cng thc sau:
TW = ( R + R0 ) C ln
ED
ED VT
131
ED
VI
VO1
VI2
VT
VO
TW
Hnh 6-12 biu din s nguyn l ca mch a hi i kiu tch phn. Ti trng thi n
nh, VI=1 th VO1=0, VI2=0, VO2=0. Khi li vo VI chuyn t 1 xung 0 li ra VO2 nhy t trng
thi 0 ln 1 v ng thi mch RC bt u tch in cho t in C, khi in p VI2 = VT in p li
ra VO2 chuyn xung trng thi 0. Sau khi khi ht xung li vo t in phng in thng qua tr R
v mch tr v trng thi n nh.
rng xung li ra ca mch a hi i c tnh theo cng thc:
TW = ( R + R0 ) C ln
ED
ED VT
TW = RC ln
ED
ED VT+
nu VT=ED/2 th TW = 0, 7 RC
VI
ED
R
VI
Vo
VT+
Vo
TW
132
P'
V1
V2
V3
V in p trn t C khng tng t bin nn khi V1 t mc cao 3,6 V t bin xung 0,3 V
th V2 t mc 0,7 V t bin xung -2,6 V. Bt u qu trnh np in ca t in C. V2 tng dn
ln. Khi V2 Tng ln n ngng thng 0,6 V th sinh ra qu trnh phn hi dng sau:
V2 V3 V1 Q
133
V1
V2
V3
t (t pd )
Hnh 6-16. Gin xung ca mch dao ng a hi i TTL vi gi thit tr ca cc
cng l tpd.
6.4. IC NH THI
B nh thi 555 c s dng rt rng ri trong cc b dao ng a hi, a hi i, v cc
b so snh v.v Hnh 6-17 l s khi nguyn l ca IC nh thi ny, trong chc nng ca
cc chn c ch ra trong bng sau:
Chn
Chc nng
Chn
Chc nng
t - GND
in p iu khin
Chn ngng
u ra
u phng in
Xo - Reset
Ngun - Vcc
TRIG
X
1
> EC
3
1
> EC
3
1
> EC
3
R
L
OUT
DIS
Thng
Thng
H
H
Khng i Khng i
H
Ngt
8
5K
So snh 1
B iu
khin
Trig
5K
+
2
So snh 2
Tng
cng sut
li ra
5K
E C1
E C2
R4
R1
VI
R2
R3
VO2
VO1
135
Hnh 6-19 l s nguyn l v gin thi gian ca mch a hi i dng IC 555, trong
RC l mch nh thi. ko di xung li ra c xc nh bng cng thc
TW RC ln 3 1,1RC . Mch dao ng a hi i ny yu cu rng xung li vo nh hn
rng xung li ra, nu n ln hn th yu cu dng thm mch vi phn li vo.
VI
VC
VO
EC
2E C / 3
EC
TW
2E C / 3
EC
VC
R1
2E C / 3
EC
0,01 F
R2
VO
VC
VO
TM1
TM2
T
Hnh 6-20. Mch a hi dng IC 555 v dng sng
TM 1 = ( R1 + R2 ) C ln 2 = 0, 7 ( R1 + R2 ) C
TM 2 = R2C ln 2 = 0, 7 R2C
T = TM 1 + TM 2 = 0, 7 ( R1 + 2 R2 ) C
f = 1/ T =
1, 43
( R1 + 2 R2 )C
EC
8
0,01 F
R1
555
3
VO
1
R2
VC
C
TM TT
Trong chng ny chng ta tm hiu cc mch to xung. Mch dao ng xung t kch
khng cn tn hiu ngoi a vo; sau khi c cp ngun mt chiu mch t ng sinh ra xung
vun. Thuc loi dao ng t kch ny c cc mch: b dao ng a hi c bn cng NAND h
TTL, b dao ng vng, b dao ng thch anh, b dao ng a hi c bn CMOS.
Mch to dng xung khng t ng pht xung nhng c th bin tn hiu u vo hnh dng
khc thnh xung vung theo yu cu ca mch s. Trong s mch to dng xung, chng ta tm
hiu: trig Schmit v n n.
Cch mch pht xung v to dng xung trn y, ngoi dng lm xung ng h ra cn c
ng dng vo cng rng ri trong cc h thng xung - s. B dao ng a hi thng dng lm b
to xung chun thi gian v chun tn s. Mch n n thng dng nh thi v lm tr xung.
Trig Schmit ngoi ng dng to dng xung cn ng dng so snh mc v gim st mc
CU HI N TP
1. Trong mch dao ng a hi c bn dng cng NAND h TTL, hnh 6-1, nu gi tr
tr in tr Rf1 = 5*Rf2 = 10 k, gi tr C1 = C2 = 1 F th mch c hot ng
khng? ng tn hiu tng i li ra s nh th no?
137
a. f = 28 Hz
b. f=28 Hz
d. f=0 Hz
a. Bin tn hiu li ra n nh
b. Tn s tn hiu li ra n nh
c. Bin li ra c th iu chnh c
d. Tn s li ra c th iu chnh c
4. Trong mch dao ng a hi dng thch anh nh hnh 6-6, nu khng c t C1, li
ra ca thch anh c ni trc tip vi du vo ca cng NAND th hai th mch:
a. Tn s hot ng cao
b. Tnh chng nhiu cao v n hot ng nh b so snh hai ngng
c. Cng sut tiu th thp
d. L b so snh mt ngng
6. Mch c s nguyn l nh hnh sau c chc nng nh th no?
V+
a. B so snh mt ngng
b. Trig Schmitt
Vi
Opam
c. Mch dao ng a hi
Vo
+
d. Mch dao ng a hi i
VR
Hnh a.
-V/2
-V
+V
+V/2
+V
+V/2
-V/2
-V
-V/2
-V
+V
+V/2
-V/2
-V
Hnh c
Hnh b
+V
+V/2
-V/2
-V
Hnh d
139
a. Hnh a.
b. Hnh b.
c. Hnh c.
d. Hnh d.
8. Chc nng ca mch a hi i l g?
140
Chng 7: B nh bn dn
CHNG 7: B NH BN DN
GII THIU
B nh bn dn thay th cc loi b nh bng vt liu t. Cc tin b mi ca cng ngh
bn dn trong thi gian gn y cung cp nhiu mch nh loi MSI v LSI c tn cy cao v
gi thnh h. Vo u thp k 60 ca th k 20, gi thnh thng phm ca mt bit nh vo
khong 2 USD. n nay (nhng nm u th k 21), gi thng phm ca 128 Mbyte vo khong
20 USD. Nh vy gi thnh thng phm ca mt bit nh sau khong 40 nm gim i khong
105.106 ln. B nh bn dn in hnh c cc t bo nh sp xp theo hnh ch nht, gn trong
khi hp nh bng nha dng DIP (Dual in line package). T bo nh c bn l mt mch trig,
transistor hay mch c kh nng tch tr in tch, t bo nh ny dng lu tr mt bit tin.
Trong phn ny gii thiu mt s b nh bn dn c bn.
NI DUNG
7.1. KHI NIM CHUNG
7.1.1. Khi nim
141
Chng 7: B nh bn dn
Truy cp lin tip (serial access) hay cn gi l kiu truy cp tun t. Cc a t, bng t,
trng t, thanh ghi dchc kiu truy cp ny. Cc bit thng tin c a vo v ly ra mt cch
tun t.
7.1.2.3. Tc truy cp thng tin.
B nh c nh
ROM
MROM
PROM
B nh bn c
nh
EPROM
EEPROM
B nh c/vit
SRAM
DRAM
Chng 7: B nh bn dn
ngt. Do vy cc chng trnh dng cho vic khi ng PC nh BIOS thng phi np trn cc
b nh ROM.
7.1.4. T chc ca b nh
Cch t chc n gin nht l t chc theo t (word organized) vi s chn tuyn tnh. Mt
ma trn nh nh vy c di ca ct bng s lng t W v di ca hng bng s lng bit B
trong mt t. B chn t phi gii m 1 t W, ngha l gii m c mt u ra duy nht cho mt
t trong b nh. Phng php ny c thi gian truy nhp ngn nhng cn mt b gii m ln khi
tng s t ln, do lm tng gi thnh sn phm.
Kch thc ca phn gii m a ch s gim i khi t chc ma trn nh v phn logic chn
t cho php gii m hai bc. Ma trn nh s dng gii m hai bc ng vi t vt l v t logic.
T vt l bao gm s lng bit trong mt hng ca ma trn. T logic bao gm s lng bit tng
ng vi mt t logic c nhn bit v gi ra cng mt lc. Cn hai b gii m: mt b gii m
hng chn mt t vt l v mt b gii m ct gm c mt vi mch hp knh chn mt t
logic t mt t vt l chn. Mt t vt l c chia thnh S t logic. B gii m hng l b gii
m chn 1 t W m B = W/S v b chn ct cha B b hp knh mt ng t S.
V d s ROM dung lng 2048 x 8 (2048 t, mi t cha 8 bit) t chc gii m hai
bc nh hnh 7- 1.
Ma trn nh l 128 x 128, nh vy c 128 = 27 t vt l. Mt t vt l c chn bi 7
ng a ch t A0 n A6. B gii m hng chn 1 hng t 128 hng. Mt t vt l c chia
thnh 128/8 = 16 nhm 8 bit. Nhm th nht cha nhng bit c trng s cao nht ca 16 t logic.
Nhm th hai cha cc bit cao tip theo ca 16 t logicNhm cui cng cha nhng bit thp
nht ca 16 t logic, do S = 16. Nh vy, nhng b gii m ct gm 8 b hp knh mt ng
t 16 ng cung cp mt t locgic ra 8 bit. Nhng a ch t A7 n A10 iu khin cc b
gii m ct. Trng hp c bit khi s phn t trong mt t vt l bng sos bit trong mt t vt
l th l b nh t chc theo bit c ngha l mi t logic c di 1 bit.
143
Chng 7: B nh bn dn
7
A0-A6
m
vo
Gii m hng
1 t 128
128
Ma trn ROM
128 x 128 bit
128
4
A7-A10
8 b gii m ct
1 t 16
8
m ra
CS
8
07,,,00
Hnh 7-1. Mt v d v gii m hai bc cho ma trn ROM 128 x 128
7.2. DRAM
7.2.1. Cu to ca DRAM
Transistor
Ca
in cc
Lp
xit
n- Ngun
n- Mng
Lp
xit
Tra
Vng lu gi
in tch
bn dn loi p
WL
BL
144
BL
Chng 7: B nh bn dn
Transistor hot ng nh mt cng tc, cho php np hay phng in tch ca t khi thc
hin php c hay vit. Cc ca (Gate) ca transistor c ni vi dy hng (cn gi l dy tWL-Word Line) v cc mng (Drain) c ni vi dy ct (cn c gi l dy bit BL hoc BL Bit Line), cc ngun (Source) c ni vi t in. in p np trn t tng i nh, v th cn
s dng khuch i nhy trong mch nh. Do dng r ca transistor nn nh cn c np li
trc khi in p trn t thp hn mt ngng no . Qu trnh ny c thc hin nh mt chu
k lm ti (refresh), khi in p trn t
c xc nh ( trng thi 0 hay 1) v mc in
p logic ny c vit li vo nh.
Mt s loi chip DRAM thng gp l:
TMS 4116: c dung lng 16k x 1 bit; 41256 c
dung lng 256k x 1 bit. Thi gian truy cp
thng tin khong 150 nsec, cng sut tiu th
khong 280 mW khi lm vic (khi ch = 28 mW)
Hnh 7-3 l v ca IC 41256 dung lng
256k x 1 bit. Mch cn 18 bit a ch m ho
cho cc a ch hng v ct; nhng trn v ch c
Hnh 7-3. IC 41256
9 ng a ch t A0 n A8. Hai chn RAS,
CAS hot ng mc cao, dng iu khin 9 bit a ch trn chip ti b gii m a ch hng
hay ct.
7.3. SRAM
Mt nh ca SRAM gi thng tin bi trng thi ca mch trig. Thut ng tnh ch ra
rng khi ngun nui cha b ct th thng tin ca nh vn c gi nguyn. Khc vi nh
DRAM, y nh trig cung cp mt tn hiu s mch hn nhiu v c cc transistor trong
cc nh, chng c kh nng khuch i tn hiu v do c th cp trc tip cho cc ng bit.
Trong DRAM, s khuch i tn hiu trong cc b khuch i cn nhiu thi gian v do thi
gian truy nhp di hn. Khi nh a ch trong cc trig SRAM, cc transistor b sung cho cc
trig, cc b gii m a chcng c i hi nh DRAM.
VCC
Tra
Tra
Tra
WL
BL
Trs Trs
WL
BL
BL
BL
Chng 7: B nh bn dn
ni vi cc ng bit v cc tn hiu c truyn ti b khuch i cui ng dy ny. V in
th chnh lch ln nn x l khuch i nh vy s nhanh hn trong DRAM (c 10 ns hoc ngn
hn), do chip SRAM cn a ch ct sm hn nu thi gian truy nhp khng c gim. Nh
vy SRAM khng cn thc hin phn knh cc a ch hng v ct. Sau khi s liu n nh, b
gii m ct chn ct ph hp v cho ra tn hiu s liu ti b m s liu ra v ti mch ra.
Vit s liu c thc hin theo cch ngc li. Qua b m vo v b gii m ct, s liu
vit c t vo b khuch i ph hp. Cng lc b gii m hng kch hot ng dy t v
lm transistor T dn. Trig a s liu c lu tr vo cp dy bit. Tuy vy, b khuch i nhy
hn cc transistor nn n s cp cho cc ng bit mt tn hiu ph hp vi s liu vit. Do ,
trig s chuyn trng thi ph hp vi s
liu mi hoc gi gi tr c lu tr ph
thuc vo vic s liu vit trng vi s liu
lu tr hay khng.
Mt s IC DRAM thng gp l 2148,
2114-2 ca hng Intel. Dung lng 1k x 4
bit. Thi gian truy cp thng tin khong 200
ns, cng sut tiu th 525 mW.
IC TMS 4016 dung lng 2k x 8 bit.
IC HM 6116, h CMOS, dung lng
2kbyte, thi gian truy cp l 120 nsec, cng
sut tiu th khi lm vic l P = 180 mW
(khi ch W). Hnh 7-5 gii thiu IC
6264, dung lng 8 kbyte, v bng iu kin
thao tc ca n.
CS
CS
WE
OE
Khng c chn
Ghi
7.3. B NH C NH - ROM
Cc chip RAM khng thch hp cho cc chng trnh khi ng do cc thng tin trn b
mt khi tt ngun. Do vy phi dng n ROM, trong cc s liu cn lu tr c vit mt ln
theo cch khng bay hi nhm gi c mi.
7.3.1. MROM
146
Chng 7: B nh bn dn
ROM lp trnh theo kiu mt n c gi l
MROM. N c ch to trn mt phin silic theo
mt s bc x l nh quang khc v khch tn
to ra nhng tip gip bn dn c tnh dn in theo
mt chiu (nh diode, transistor trng). Ngi thit
k nh r chng trnh mun ghi vo ROM, thng
tin ny c s dng iu khin qu trnh lm mt
n. Hnh 7-6 l mt v d n gin v s MROM
dng diode.
Cc
dy hng (i
Cc dy bit
7.4. B NH BN C NH
7.4.1. EPROM (Erasable PROM)
Chng 7: B nh bn dn
t c kch hot th cng khng th pht ra trng u mnh vi cc ca iu khin lm
thng transistor. Lc ny ng bit khng c ni vi ngun chun v nh coi nh c gi
gi tr 0.
Ngun
Mng
Ca
hv
hv
ID
0
1
Xo
Ca iu khin
Ca ni
Lp xit
n- Ngun
- - - - -
Lp xit
Lp trnh
n- Mng
bn dn
loi p
v0
v1
vGS
148
Chng 7: B nh bn dn
Cc chip ROM hin nay c thi gian truy nhp t 120 ns n 150 ns di hn nhiu thi gian
trong cc chip nh RAM.
7.4.3. a cng silicon- B nh FLASH
149
Chng 7: B nh bn dn
VPP
Chuyn mch in th
xo
iu khin
WE
CE
OE
B nh thi
Chuyn mch in th
chng trnh
Gii
m
hng
m
a
ch
a
ch
Ma trn t bo nh
Gii
m
ct
D liu vo
Ca vo ra
m vo ra d liu
Vi cc my tnh c tc nhanh (trn 33MHz), cn phi xen cc trng thi i khi truy
xut d liu ti cc DRAM r tin nhng c thi gian thm nhp chm (60-120ns). iu ny lm
gim hiu sut ca my. C th gii quyt bng cch dng cc SRAM c thi gian thm nhp
ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc
li im nhanh ca SRAM v r ca DRAM. Gia CPU v b nh chnh bng DRAM, ngi ta
xen vo mt b nh SRAM nhanh c dung lng nh bng 1/10 hoc 1/100 ln b nh chnh gi
l cache; di s iu khin ca mch iu khin cache, b nh ny s lu tr tm thi cc s liu
thng c gi v cung cp n cho CPU trong thi gian ngn.
Cache cha cc thng tin mi va c CPU s dng gn y nht. Khi CPU c s liu n
s a ra mt a ch ti b iu khin cache. Sau mt trong hai qu trnh sau s xy ra:
150
Chng 7: B nh bn dn
-
Nh vy, cache hit t l vi truy xut thng tin c sn trong b nh cache SRAM, cn
cache miss li t l vi truy xut thng tin c trong b nh chnh l cc DRAM.
SRAM Cache
DRAM trong b
nh chnh
CPU
B iu khin CACHE
7.5.1 M rng di t
R/W
RAM
CS
RAM
R/W
CS
II
D0
BUS d liu
Dn-1
BUS d liu
151
Chng 7: B nh bn dn
R/ w c ni song song. Mt phn dung lng c tr vo mi chp. S phn chia ny da
trn c s t hp a ch vo v li vo iu khin. Hnh 7-11 l mt s v d.
A0
A0
IC 1
A1
2k
A11
A12
A13
A0
IC 2
A1
2k
A0
IC 3
A1
2k
CS2
CS 1
A0
IC 4
A1
2k
CS3
B gii
m vo
2 ra 4
CS4
thc hin php m rng ta phi s dng mt s li vo a ch dnh ring cho b gii
m (thng l cc a ch c trng s cao). s trn ta chn 2 a ch A12 v A13 gii m.
Do ta c th nhn c 4 gi tr ra tng ng. Cc gi tr ny tc ng ln cc li vo CS
m tun t cc IC nh. Cc IC nh ny c th lm ROM hoc RAM hoc c hai l ty chn. Tun
t m cc IC theo A12, A13 nh ch ra bng hot ng sau.
A13
A12
CS
IC m
Khong a ch
IC I
000016 - 0FFF16
IC II
100016 - 1FFF16
IC III
200016 - 2FFF16
CS1
CS2
CS3
CS4
IC IV
300016 - 3FFF16
TM TT
Trong chng ny chng ta trnh by nguyn l cu to, cc tnh nng c bn ca cc loi
b nh bn dn: ROM, PROM, EPROM, EEPROM, SRAM, DRAM, FLASH, CACHE.
Cc chip RAM khng thch hp cho cc chng trnh khi ng do cc thng tin trn b
mt khi tt ngun. Do vy phi dng n ROM, trong cc s liu cn lu tr c vit mt ln
theo cch khng bay hi nhm gi c mi.
Trong nhng nm gn y, mt loi b nh khng bay hi mi xut hin trn th trng,
thng c s dng thay th cho cc a mm v cng trong nhng my tnh. l b nh
flash. Cu trc ca chng c bn nh EEPROM, ch c lp knh xit cc nh mng hn.
Vi cc my tnh c tc nhanh (trn 33MHz), cn phi xen cc trng thi i khi truy
xut d liu ti cc DRAM r tin nhng c thi gian thm nhp chm (60-120ns). iu ny lm
gim hiu sut ca my. C th gii quyt bng cch dng cc SRAM c thi gian thm nhp
152
Chng 7: B nh bn dn
ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc
li im nhanh ca SRAM v r ca DRAM.
Trong chng ny cn gii thiu cch m rng dung lng v di t ca b nh bn dn.
CU HI N TP
1. B nh ROM l b nh:
a.
Ch c th c.
b.
Ch c th vit.
c.
C th va c va vit.
d.
2. B nh RAM l b nh:
a.
Ch c th c.
b.
Ch c th vit.
c.
C th va c va vit.
d.
Transistor.
b.
Trig.
c.
T in.
d.
Diode.
Transistor.
b.
Trig.
c.
T in.
d.
Diode.
Lng cc.
b.
MOS.
c.
Lng cc v MOS.
d.
Ch lp trnh c mt ln.
b.
Chng 7: B nh bn dn
c.
Lp trnh c v xo c.
d.
b.
Transistor trng.
c.
T in.
d.
Diode.
To cc nh mang gi tr 0.
b.
To cc nh mang gi tr 1.
c.
To cc nh mang gi tr 0 v 1.
d.
Ch lp trnh c mt ln.
b.
Lp trnh c v xo c mt ln.
c.
d.
b.
c.
d.
b.
c.
d.
154
a.
a mm.
b.
a cng.
c.
d.
NI DUNG
8.1. GII THIU CHUNG V LOGIC KH TRNH (PLD)
Vi mch lp trnh, vit tt l PLD (Programmable Logic Device), l loi cu kin in t c
nhiu u im v hin nay ang c pht trin rt mnh. V nguyn l, chng c cu to rt
ging vi PROM. Vic lp trnh cho PLD c th c thc hin bng cc cng ngh khc nhau,
da trn c s b cu ch hoc chuyn mch. Tuy nhin, ng dng ca PLD li rt khc vi
PROM. Mt PLD, c to thnh bng mt s cng AND, OR, XOR hoc c cc trig, c th
thc hin nhiu hm Boole khc nhau.
156
8.2 SPLD
SPLD - cu kin logic kh trnh n gin. y l loi cu kin s c nhiu u im v cng
c pht trin rt mnh. V nguyn l, chng c cu to rt ging vi PROM. Vic lp trnh
cho SPLD c th c thc hin bng cc cng ngh khc nhau, da trn c s thc hin cc kt
ni bng cch s dng cu ch hoc chuyn mch. Mt SPLD, c to thnh bng mt s mng
cng AND, OR, XOR hoc c cc triger, c th thc hin nhiu hm Boole khc nhau.
Cc SPLD u c cu to da trn mt trong hai dng cu trc chnh: mng logic kh trnh
PLA (Programmable Logic Array) v logic mng kh trnh PAL (Programmable Array Logic).
u vo
PAL
u vo
PLA
u ra
u ra
157
Interconnect
IO/Registers/Logic
nng vo hoc ra hoc va l chn vo va l chn ra, ngoi ra cn c th thit lp cc chn I/O
ny lm vic cc mc logic khc nhau, c in tr pull-up hoc pull-down ...
Vi cu trc ng nht, gi thnh r, tnh nng kh mnh, d s dng CPLD v ang
c s dng rt rng ri trong thc t, gip cho nh sn xut pht trin nhanh sn phm ca
mnh vi gi thnh r. c bit hin nay cc hng pht trin cc h CPLD vi tnh nng rt
mnh, cng sut tiu th thp, chng ang c s dng rt nhiu pht trin cc sn phm in
t, vin thng, cng ngh thng tin, nht l trong cc thit b cm tay, di ng
Trong thc t rt c nhiu loi CPLD khc nhau, ca cc hng khc nhau, v c pht
trin vi nhiu chng loi, th h CPLD khc nhau. Cu to, dung lng, tnh nng, c im,
ng dng ca mi loi CPLD cng rt khc nhau. Trong gio trnh ny khng i su trnh by
cu to c th ca cc h CPLD, m ch trnh by kin trc chung n gin nht ca CPLD. Khi
s dng c th loi CPLD no, ngi hc nn tham kho cc ti liu khc, nht l tham kho cc
ti liu k thut c cung cp km theo cu kin do cc hng a ra. Cc hng in t ni ting
trn th gii ang s hu, pht trin, cung cp cc loi cu kin CPLD l Xilinx, Altera
8.4. FPGA
FPGA (Field Programmable Gate Array - Ma trn cng lp trnh c theo trng): c cu
trc v hot ng phc tp hn CPLD. N c th thc hin nhng chc nng phc tp u vit hn
CPLD. Nm 1985, cng ty Xilinx a ra tng hon ton mi, l kt hp thi gian hon
thnh sn phm v kh nng iu khin c ca PLD vi mt v u th v chi ph ca
GateArray. T , FPGA ra i. Hin nay, Xilinx vn l nh sn xut chip FPGA s mt trn th
gii.
Cu trc FPGA n gin gm cc t bo logic (Logic Cell), cc khi cch u nhau, lin kt
nh cc ng kt ni c th thay i c theo yu cu ca ngi thit k. Ngha l ngi thit
k c quyn thit k, lp trnh v thay i mch in. Hin nay, FPGA c mt kh cao, ln ti
hng trm t cng v cu trc cng a dng, phc tp hn. Nhiu chc nng phc tp c tch
hp sn tng hiu qu s dng FPGA. V d nh ngoi nhng khi t bo logic, nhiu h
FPGA c tch hp thm cc khi chc nng nh cc b nhn cng, khi nh, PLL, thm ch
c mt b vi x l mnh
C hai loi FPGA c bn: loi lp trnh li c, da trn cng ngh SRAM v loi lp
trnh mt ln.
159
SRAM xc nh cc kt ni
Kt ni dng b cu ch
Bng LUT 4 u vo
nh iu
khin im
kt ni
im kt ni
Hai dng ny khc nhau v quy trnh thc hin t bo logic v c ch c s dng to
kt ni trong thit b.
Chip FPGA lp trnh mt ln s dng phng php b cu ch (kt ni c to ra bng
cch ng cu ch) to kt ni tm thi trong chip, do khng cn SPROM hoc cc phng
tin khc np chng trnh vo FPGA. Tuy nhin, mi ln thay i thit k, phi b hon ton
chip c i. T bo logic OTP tng t nh PLD vi cc cng v cc trig nh trc.
Dng FPGA quan trng hn v c dng ph bin hn c l dng lp trnh li c, da
trn SRAM. Trn thc t, FPGA SRAM c lp trnh li mi khi bt ngun, v FPGA l dng
chip nh tm thi. Do , mi chip FPGA u cn c mt b nh PROM ni tip hoc mt b
nh h thng.
Trong t bo logic SRAM, thay v cc cng thng thng, ngi ta s dng bng nh x
(LUT). Bng ny xc nh cc gi tr u ra da trn cc gi tr u vo, s dng xy dng cc
hm logic t hp. Trong s T bo logic SRAM minh ho hnh v 8-3, 16 t hp khc
nhau ca 4 u vo s xc nh gi tr ca u ra). Cc cc nh SRAM cng c s dng
iu khin kt ni .
160
FPGA
- Cu trc da vo LUT
- Mng kt ni trung tm
- Mt tch hp cao
S lng chn vo/ra: phi xc nh vi mch thit k cn bao nhiu u vo, bao nhiu u
ra.
161
162
dng cng c 3rd part boundary scan, cc gii php phn mm km theo, cp ISP, thit b kim tra
t ng ATE v h tr lp trnh cng nh cc thit b lu tr cu hnh.
Gii php cu hnh hin i nht l nhm cu hnh System ACE. Vi gii php System
ACE, ngi thit k c th d dng s dng giao din vi x l trong System ACE trc tip phi
hp cu hnh FPGA theo cc yu cu ca h thng. Gii php u tin trong nhm ny l System
ACE CF, cung cp cng ngh iu khin a Microdrive kch thc mt inch v CompactFlash
cng nh b lu tr cu hnh c dung lng 8 gigabits. Ngoi ra, System ACE CF cng c
thit k trc, cung cp cc c tnh hin i tn dng kh nng cu hnh li linh hot ca
FPGA, bao gm:
- Cu hnh multi-board t mt ngun duy nht
- Qun l bitstream a cu hnh
- Nng cp cu hnh qua mng (IRL)
- Hot-swapping
- Khi to trung tm x l v lu tr phn mm
- M ha
Vi System ACE CF, ngi thit k c th thc hin c gn nh ton b cc yu cu cu
hnh cho FPGA. Cc kh nng b tr h thng ny cho php ngi thit k s dng FPGA tha
mn cc yu cu nh trc v mt thit k v thi gian x l li. Ngoi ra, cc cng vi x l v
cng kim tra JTAG cn cho php tch hp System ACE trong mi h thng.
Mt s c im ca gii php cu hnh System ACE:
- linh hot: Vi System ACE CF, c th s dng mt thit k cho nhiu ng dng khc
nhau, nh gim ng k thi gian hon thnh sn phm. Thay v thit k vi bo mch tng t
nhau ph hp vi cc chun khc nhau, gi y ngi thit k ch phi thit k mt bo mch duy
nht vi nhiu cu hnh c lu tr trong b nh System ACE CF. Mi bo c th chn cc cu
hnh ph hp vi cc chun khc nhau bng cch khi to gi tr mc nh tng ng c lu
trong b nh ACE. H thng cn cho php lu nhiu cu hnh cho mt thit k trong mt System
ACE CF n. V d nh trong qu trnh thit k mu, ngi thit k c th lu cc cu hnh hot
ng, cu hnh kim tra v cu hnh g ri trong b nh ACE, ng thi c th chn cc cu hnh
khc chy th bn thit k ca mnh.
163
Xilinx cung cp cc cng c thit k in t hon chnh, cho php thc hin thit k trn
cc thit b logic kh trnh ca Xilinx. Cc cng c ny kt hp cng ngh tin tin vi giao din
ha linh hot, d s dng ngi thit k c c thit k ti u. B cng c phn mm hin
ang c s dng rng ri l ISE vi phin bn mi nht l 7.0 (nm 2005).
Xilink cng cung cp ISE di dng cc gi phn mm c cu hnh khc nhau vi gi thnh
khc nhau:
+ ISE WebPACK - bn min ph c th dng thit k cho tt c cc h CPLD ca Xilinx
+ Gi phn mm c bn BASEX: c th thit k cho cc loi chp sau:
Virtex-4, FPGA LX15, LX25, SX25, FX12, Spartan-3 FPGA ln n 1500 ngn cng v
tt c cc h CPLD.
+ Gi phn mm Foundation: c th thit k cho tt c cc loi FPGA v CPLD ca Xilinx
Ngoi ra Xilinx cn pht trin cc b cng c phn mm tin ch khc nh System
Generator h tr cho cc thit k DSP (Digital Signal Processor: B x l tn hiu s), hay EDK
(Embbleded Dvelopment Kit: B phn mm pht trin h thng) h tr cho cc thit k nhng.
ISE c dng kt hp vi phn mm m phng ModelSim ca Mentor Graphics phin bn
XE c pht trin ring h tr cho cc h CPLD/FPGA ca Xilinx.
8.6.2 Lu thit k cho CPLD ca Xilinx
Qu trnh thit k cho CPLD ch yu l thc hin trn cc cng c phn mm, lu thit
k chung cho CPLD (V d s dng phn mm ISE) nh hnh v sau, bao gm cc bc nh sau:
+ Nhp thit k (Design Entry):
y l bc u tin v quan trng nht ca qu trnh thit k cho CPLD. Cc cng c thit
k cho php nhp thit k cho php nhp thit k theo cc cch sau:
- Nhp thit k theo s nguyn l Schematic, ngi thit k s dng cc modul c sn
trong th vin Schematic ghp ni chng vi nhau to thnh bn thit k theo yu cu, cch
ny c th thc hin thit k nhanh nhng s rt kh khn v khng ti u ti nguyn ca CPLD
164
khi thit k phc tp, v thit k khng th s dng sang cng c thit k CPLD ca cc hng
khc. T s nguyn l thit k c cng c phn mm s chuyn i sang file ngn ng m
t phn cng HDL, m ph bin l VHDL hoc Verilog.
- Nhp thit k s dng ngn ng m t phn cng HDL (VHDL, Verilog, ABEL,
AHDL...), Ngi thit k c th s dng chng trnh son tho thc hin vic m t ton b
bn thit k ca mnh di dng ngn ng HDL no m cng c thit k c th tng hp c.
C rt nhiu phng php m t, mc tru tng khc nhau khi thit k, mi cch m t khc
nhau c th to ra mt cu trc mch khc nhau trong CPLD mc d chng c cng chc nng.
Design Entry
Schematic
ECS
HDL
Verilog/VHDLL
State Machines
StateCad
Design Verification
Functional Simulation
ModelSim XE
Design Synthesis
Xilinx Synthesis Tool
XST
Design Implementation
Translate
Map
Timing Simulation
Static Timing Analysis (ECS)
ModelSim XE
Configuration
Download (iMPACTE)
165
Do ngi thit k cn thc hin phn tch bi ton, tm hiu ti nguyn, cu trc ca
CPLD, yu cu v thi gian thit k s dng kiu m t. Mc tru tng trong khi m t
ph hp va m bo yu cu v thi gian thit k va ti u c vic s dng ti nguyn ca
CPLD.
- Nhp thit k di dng s : Cng c thit k cn cho php nhp thit k vo di dng
s m in hnh l hnh trng thi, sau chng cng c chuyn i sang HDL.
Vic nhp thit k rt linh hot, c th s dng c 3 cch trn thc hin cc phn khc
nhau ca thit k.
+ Kim tra, m phng thit k (Design Verification): Thc hin kim tra, m phng chc
nng hot ng ca thit k HDL to ra trn. Cc cng c thit k u h tr vic m phng
chc nng hot ng ca bn thit k HDL theo m hnh hot ng (Behavioral Model), mc
m phng ny c lp vi loi CPLD c la chn. Bc ny c th khng cn phi thc
hin trong khi thit k.
+ Tng hp thit k (Design Synthesis): Sau khi hon thnh m phng thit k, bc tng
hp tip theo c nhim v chuyn thit k di dng file vn bn HDL thnh dng file netlist,
thc hin m t mch thc mc thp di dng cng logic v kt ni gia chng vi nhau. C
th s dng cc cng c tng hp ca cc hng khc nhau.
Mi cng c c th to ra file netlist theo nh dng ring (v d ca XST ca Xilinx XNFXilinx Netlist Format) nhng c th t la chn to ra file netlist di dng nh dng chun
EDIF (Electronic Digital Interchange Format) m tt c cc cng c c th hiu c.
U1A
U1A
U3A
U2A
U2A
U3A
Chn cc cng
A
B
U4A
U1A
Thc hin kt ni
U4C
U4B
U2A
U3A
U4D
Component AND G1
Component OR G
Component NOT G3
Net N1: A. G1:a. G3:a
Net N2: B. G1:b. G2:a
Net N3: G1:c. P
Net N4: G3:b. G2:b
Net N5: G2:c. Q ;
Ghp cc b m v/ra
To Netlist
166
Place and Route l qu trnh phc tp, do n chim thi gian nhiu nht. Tuy nhin,
bc ny ch c th hot ng tt nu chip chn p ng cc tuyn lin kt cho thit k.
Nu khng, ngi thit k s phi chn chip c dung lng ln hn. Sau bc ny to ra c file
cu hnh *.jed c th c np vo cho CPLD.
+ Timing Simulation (M phng c tham s thi gian): Sau bc Place and Route ngi
thit k c th thc hin m phng thit k mc cng logic c nh v tr v nh tuyn
trn CPLD, phn mm s dng file cu hnh c to ra v kt hp vi th vin v m hnh
thi gian ca cc h CPLD (V d ISE ca Xilinx th dng th vin VITAL), thc hin m
phng hot ng ca thit k m c tnh n cc tham s thi gian tr, thi gian thit lp ca
cc cng logic trong CPLD. Bc ny rt quan trng vi nhng thit k phc tp, tc ln.
167
Configuration
Create Bit file
Download (iMPACTE)
TM TT
Trong chng ny trnh by cc khi nim c bn ca logic lp trnh. Vi s pht trin ca
cc thit b logic lp trnh ta c th thit k cc h thng k thut s phc tp. Cc k thut thit
k cp cao v cc cng c tr gip my tnh cn thit to nn chc nng thc thi PLD v
FPGA hiu qu. Vic th nghim tnh thc thi ca PLD v FPGA cng yu cu phi c cc cng
c th nghim v s tr gip ca my tnh.
168
NI DUNG
9.1. GII THIU NGN NG M T PHN CNG VHDL
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt loi ngn
ng m t phn cng c pht trin dng cho trng trnh VHSIC( Very High Speed Itergrated
Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m
phng phn cng tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng
nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn ng VHDL c ba
cng ty Intermetics, IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm
1983. Phin bn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chc
IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL( tiu chun
IEEE-1076-1987).
VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti
liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu m t. c th vn
hnh bo tr sa cha mt h thng ta cn tm hiu k lng ti liu . Vi mt ngn ng m
phng phn cng tt vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th
c thc thi m phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t
ca h thng hot ng trong mt m hnh thng nht.
VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php
thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c th t do la chn cng
ngh, phng php thit k trong khi ch s dng mt ngn ng duy nht. V khi em so snh vi
cc ngn ng m phng phn cng khc k ra trn ta thy VHDL c mt s u im hn hn
cc ngn ng khc:
+ Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v
hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b cng
nh nhiu nh cung cp cng c thit k m phng h thng.
+ Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL cho php
thit k bng nhiu phng php v d phng php thit k t trn xung, hay t di ln da
vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng c xy dng mch nh s dng
cng ngh ng b hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu
nhin.
+ Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to
phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc
bn tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n c th c
p dng ngay cho cc h thng thit k .
170
171
Trong ngn ng VHDL gm c 3 i tng l: tn hiu - signal, bin - variable, hng constant, mi i tng c khai bo da vo t kha tng ng v chng c mc ch s dng
nh sau:
+ Tn hiu Signal: l i tng biu din ng kt ni cc gia cc cng vo/ra ca
thc th, gia cc cng vo/ra ca cc khi thnh phn phn cng xut hin trong thc th
Chng l phng tin truyn d liu ng gia cc thnh phn ca thc th.
Tn hiu c tnh ton cc rt cao, chng c th c khai bo trong package (tn hiu ton
cc, c s dng bi mt s thc th), khai bo trong thc th - Entity (tn hiu ni b dng
trong thc th, c th c tham chiu bi bt k kin trc no ca thc th ), khai bo trong
kin trc Architecture (tn hiu ni b dng trong kin trc, c th c s dng trong bt c
cu trc lnh no trong kin trc). Cc tn hiu c th c s dng nhng khng c khai bo
trong tin trnh process, trong chng trnh con. V tin trnh v chng trnh con l thnh phn
c s ca m hnh v chng c coi nh cc hp en. C php khai bo tn hiu nh sau:
Signal tn_tn_hiu {,tn_tn_hiu}:kiu_d_liu [:=gi_tr_khi_to];
V d: Signal a,b,c: Bit:=1;
Signal y, reg: std_logic_vector(3 downto 0):=0000;
172
Cc i tng khi khai bo phi c xc nh kiu d liu tng ng. VDHL nh ngha
nhiu kiu d liu khc nhau ph hp vi vic m t, thit k, m phng cc h thng s khc
nhau trong thc t.
9.2.2 Kiu d liu trong VHDL
Kiu ghp: cc d liu di dng mt nhm cc thnh phn nh mng, bng ghi
(record). Bit_logic_vector, std_logic_vector v String u l nhng dng d liu ghp
c nh ngha sn.
VHDL Subtypes: dng d liu con do ngi dng t nh ngha da trn nhng dng
c sn.
Cc kiu d liu c nh ngha trong gi Standard cha trong th vin chun Standard
Library ca VHDL l: bit, boolean, integer, real, physical, character, std_logic and std_ulogic,
Bit_logic_vector, std_logic_vector v String v mt s kiu d liu con. C php chung nh
ngha kiu d liu nh sau:
Type Tn_kiu is gii_hn_gi_tr_ca_kiu
a. Kiu v hng
- Kiu Bit : Kiu lit k vi 2 gi tr 0 v 1. Kiu Bit c nh ngha nh sau: Type
Bit is (0, 1);
P : PROBABILITY := 0.5 ;
units
fs; -- n v c bn
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
V d s dng:
constant Tpd : time := 3ns ;
...
Z <= A after Tpd ;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
End Units;
174
type
std_ulogic
( U,
X,
is
-- Uninitialize
-- Forcing Unknown
type
std_logic
( U,
X,
is
-- Uninitialize
-- Forcing Unknown
0,
--
Forcing Zero
0,
--
Forcing Zero
1,
--
Forcing One
1,
--
Forcing One
Z,
--
High Impedance
Z,
--
High Impedance
W,
-- Weak Unknown
W,
-- Weak Unknown
L,
--
Weak Zero
L,
--
Weak Zero
H,
--
Weak One
H,
--
Weak One
--
Dont Care
--
Dont Care
) ;
) ;
Hai kiu d liu std_logic v std_ulogic tng t nhau, chng ch khc nhau ch l kiu
std_ulogic khng c hm phn di (unresolved) hm quyt nh gi tr tn hiu, do s c li
khi cc tn hiu kiu std_ulogic c ni chung vo 1 im. Th vin cng cung cp hm pht
hin li ny ca cc tn hiu kiu std_ulogic.
signal
A,B,C,Res_Out : std_logic ;
signal
Out_1 : std_ulogic ;
Out_1 <= A ;
Res_Out <= A;
Out_1 <= B ;
Res_Out <= B;
Out_1 <= C ;
B
Out_1
C li
Res_Out <= C;
B
C
Res_Out
Thc hin c
(K hiu <= dng trn l lnh gn tn hiu, lnh gn tn hiu thc hin c vi 2 d liu
cng kiu, cng ln, gi tr ca tn hiu bn phi s c gn cho tn hiu bn tri).
- Kiu d liu lit k t nh ngha: Kiu d liu lit k, do ngi s dng t nh ngha,
cho php m t rt sng sa, v linh hot cho cc m hnh phn cng s vi mc tru tng
cao. Kiu d liu ny dng nhiu m t hnh trng thi, cc h thng phc tp
Tng t cc ngn ng lp trnh, VHDL cng c cc kiu d liu ghp l nhm cc phn t
d liu theo dng mng (array) hoc bng ghi (record).
+ Mng Array:
175
State2;
3
My_BusA
My_BusA
My_BusB
My_BusB
Cch biu din s liu bit_vector v std_logic_vector: B|O|X gi_tr (dng du nhy kp).
Trong B : Binary -Kiu nh phn, O: Octal - kiu bt phn, X: hexadecimal.
X1AF=B0001_1010_1111= B000_110_101_111=O0657
- Php gp ( ): cho php nhm c d liu v hng v d liu mng thun tin cho cc
php gn cho mng:
176
: std_logic;
Bng ghi l nhm nhiu phn t c kiu d liu khc nhau thnh i tng duy nht.
-
: bit;
ADDRESS : std_logic_vector ( 0 to 3 );
DATA_BYTE : std_logic_vector ( 7 downto 0 );
NUM_VALUE : integer range 0 to 6;
STOP_BITS : bit_vector (1 downto 0);
end record ;
. . .
signal
PARITY
TX_PACKET, RX_PACKET
ADDRESS
: OPCODE;
DATA BYTE
177
Mng 2 chiu l kiu d liu mng ca cc phn t mng mt chiu hay bng ghi. Mt s v
d nh ngha v khai bo kiu d liu mng 2 chiu nh sau:
type Mem_Array is array (0 to 3) of std_logic_vector (7 downto 0);
type
Data_Array is array ( 0 to 2 ) of
OPCODE ;
...
signal My_Mem:Mem_Array ;
signal My_Data:Data_Array ;
F
Z
H
Y
G
V d: Z <= A and B;
178
Y <= G or ( F and H ) ;
signal
A_vec,
B_vec,
C_vec :
bit_vector(7 downto 0 ) ;
...
C_vec <= A_vec
and
B_vec ;
A_vec (7)
B_vec (7)
C_vec (7)
A_vec (6)
B_vec (6)
C_vec (6)
A_vec (5)
B_vec (5)
C_vec (5)
.
.
.
+ Php ton logic thc hin vi tng phn t ca mng v A_vec (0)
theo th t t tri sang phi.
B_vec (0)
C_vec (0)
signal
FLAG_BIT : boolean ;
signal
A, B : integer ;
A_vec : bit_vector
( 7 downto 0 ) := 11000110 ;
signal
B_vec : bit_vector
( 5 downto 0 ) := 111001 ;
...
if ( A_vec
> B_vec )
then
State <=
Normal;
State <=
Code_Red;
else
end if;
179
2;
D_vec =00011000
2;
D_vec =11110001
3;
D_vec =11011000
2;
D_vec =00110001
D_vec =00011000
Ton t ghp ni: ton t & cho php ghp ni mt cch linh hot cc d liu n v d liu
dng mng thnh cc mng ln hn.
Ton t thuc tnh: Xc nh thuc tnh d liu ca i tng bin v tn hiu. C php
chung:
i_tngthuc_tnh
- Cc thuc tnh c nh ngha trc cho kiu d liu mng trong VHDL l:
+ left, right: tr li ch s ca phn t bn tri nht hoc bn phi nht ca d liu mng.
+ high, low : tr li ch s ca phn t cao nht hoc thp nht ca kiu d liu mng.
+ range, reverse_range : xc nh khong ca ch s ca mng.
+ length : tr v s lng cc phn t ca mng.
+ event, stable : thuc tnh ch dng cho i tng l tn hiu, tr v gi tr boolean, ch ra
rng trn ng tn hiu ang xt c xut hin s kin thay i hay gi tr trn ng tn hiu n
nh ti thi im hin ti. Cc thuc tnh ny dng nhiu vi lnh wait v if. V d s dng ton
t thuc tnh nh sau:
signal a : std_logic:=0;
...
PROCESS(a)
TYPE bit4 IS ARRAY(0 TO 3) of BIT;
TYPE bit_strange IS ARRAY(10 TO 20) OF BIT;
VARIABLE len1, len2 : INTEGER;
BEGIN
If (aevent and a=1)then - s kin c xn dng ca a.
len1 := bit4LENGTH; -- returns 4
180
Entity: (Thc th) - cho php khai bo cc giao din ca mt khi thit k s no
: nh khai bo cc chn vo/ra, cc tham s ca khi mch...
Khai bo thc th trong VHDL phn nh ngha cc ch tiu pha ngoi ca mt phn t hay
mt h thng. Thc cht ca vic khai bo thc th chnh l khai bo giao din ca h thng vi
bn ngoi. Ta c th c tt c cc thng tin kt ni mch vo mch khc hot thit k tc nhn
u vo phc v cho mc ch th nghim. Tuy nhin hot ng tht s ca mch khng nm
phn khai bo ny. C php khai bo chung ca mt Entity nh sau:
entity Tn_thc_th is
generic(--Khai bo danh sch cc tham s generic
Tn_tham_s : [Kiu_d_liu] [:=gi_tr_khi_to];
...
);
port(-- Khai bo danh sch i tng cc port vo ra
Tn_cng : [mode] [Kiu_d_liu] [:=gi_tr_khi_to];
...
);
end Tn_thc_th;
181
A
B
PLD
Logic_AND
Phn khai bo kin trc c th bao gm cc khai bo v cc i tng signal, constant, kiu
d liu, khai bo cc phn t bn trong h thng (component), hay cc hm (function) v th tc
(proceduce) s dng m t hot ng ca h thng. Tn ca kin trc l nhn c t tu theo
ngi s dng
VHDL cho php to ra nhiu m t Architecture cho mt thc th, cho php thc hin
nhiu cch m t hot khc nhau cho mt thc th. Mi cch m t hot ng s ti u v mt
thi gian thit k hay tin cy hay ti u v ti nguyn s dng khi tng hp
C 3 cch chnh m t kin trc ca mt phn t (hoc h thng s) l m hnh hot
ng (Behaviour), m t theo m hnh cu trc logic (Structure), v m hnh lung d liu. Tuy
nhin m t cho mt h thng, trong mt kin trc c th kt hp s dng 2 hoc c 3 m hnh
m t trn thc hin cho tng thnh phn con tng ng ca h thng s. Trong phn sau ca
ti liu ny s trnh by chi tit hn cc phng php m t ny.
182
entity Half_Add is
. . .
end Half_Add;
architecture
BEH of
Half_Add
is
-- Kin trc m t
theo m hnh hot ng
RTL of
Half_Add
is
-- Kin trc m t
theo m hnh lung d
liu
XLX of
Half_Add
is
-- Kin trc m t
theo m hnh cu trc
logic
. . .
end
BEH ;
architecture
. . .
end
RTL ;
architecture
. . .
end XLX ;
+ Package v Package Body
183
package My_Pack is
constant. . .
. . .
function bv_to_integer (BV: bit_v..
return integer
. . .
component . . .
. . .
subtype. . .
end package My_pack;
use IEEE.std_logic_1164.all ;
. . .
-- Trong phn mm thit k ISE
gi d liu do ngi s dng
to ra thng c t chc mc
nh trong th vin work
use work.My_Pack.all;
entity . . .
184
library My_Lib ;
use My_Lib.Fast_Counters.all ;
entity Mod1 is
port ( . . .
V d:
a1:alu
configuration ttl.sn74ls181;
for;
m1,m2,m3: mux
entity multiplex4 (behavior);
for;
all: latch -- use defaults
for;
for;
configuration v4_27_87;
185
CPLD/FPGA
entity
architecture
process
Variables
Signals
Input Ports
Output Ports
186
...
{ Vit cc m t dng cu trc lnh song song hay process khc }
...
End Tn_kin_trc;
Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tra mt m hnh
VHDL c thc hin bng cch quan st hot ng ca n trong khi m phng v cc gi tr thu
c c th em so snh vi yu cu thit k.
Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kim tra sinh ra cc
tc ng ln bn thit k v cho php quan st hoc so snh kt qu hot ng ca bn m t thit
k. Thng thng th cc bn m t u cung cp chng trnh th. Nhng ta cng c th t xy
dng chng trnh th (testbench). Mch th thc cht l s kt hp ca tng hp nhiu thnh
phn. N gm ba thnh phn. M hnh VHDL qua kim tra, ngun d liu v b quan st. Hot
ng ca m hnh VHDL c kch thch bi cc ngun d liu v kim tra tnh ng n thng
qua b quan st. Hnh 9-2 l s tng qut ca mt chng trnh th (Testbench).
Testbench c m t nh mt Entity khng c u vo u ra, ch c tn hiu bn trong
c ghp ti khi DUT cn c kim tra theo kiu cu trc. Ngi thit k s m t cc tn
hiu bn trong ny to ra tn hiu kch thch cho cc u vo ca DUT v c kt qu ra quan
st...
Testbench Entity
Generics
Data
Source
(stimuli
Generator
DUT
Observer
187
;
A
M t to
kch thch
A
B
DUT
Logic_AND
Quan st
std_logic:='0';
SIGNAL B :
std_logic:='0';
SIGNAL Y :
std_logic;
BEGIN
-- Ni chn cng vo ra ca DUT vi cc tn hiu ca Test_bench
uut: Logic_AND PORT MAP(
a => a,
b => b,
y => y
);
tb : PROCESS
BEGIN
-- Vit m t to kch thch
188
END;
Trong cc phn mm thit k sau khi hon thnh cc m t cho Test_bench, ngi thit k
s chy cng c m phng, cc tn hiu u ra ca DUT s c mc tnh c ra v cho php
ngi thit k quan st d dng di dng gin thi gian, hay cc file s liu
Ngi thit k c th d dng vit cc m t kch thch to ra cc yu cu kim tra ty
cho bn thit k ca mnh. Nhiu chc nng m phng, kim tra c h tr rt mnh bi cc
phn mm thit k.
9.2.7 Cc cu trc lnh song song
Process trong mt thit k c thc hin song song. Tuy nhin, ti mt thi im xc nh
ch c mt cu lnh tun t c thc hin trong mi cu trc Process. Cu trc tng qut:
Trong cc phn t trong du [ ] c th c hoc khng.
189
entity Logic_AND is
Port ( A,B : in std_logic;
C
: out std_logic);
end Logic_AND;
architecture Behavioral of Logic_AND is
begin
Process(A,B)
begin
C<= A and B;
end Process;
end Behavioral;
190
Process 1
A
B
G1
C<=A and B
...
G2
Process 2
If C = 1
then
...
C
C
Process 3
G3
process (C,..)
begin
Process n
C<=A and B
...
Process n1
C
C
Process n4
If C = 1
then
...
Sig1
Sig2
process (...
Process n2
process n
process (C,..)
begin
Process n3
Rst
Php gn tn hiu song song s dng bn trong cc Architecture nhng bn ngoi Process.
Dng n gin nht ca php gn tn hiu song song c c php nh sau:
<tn_hiu_ch> <= <biu_thc> [after <biu_thc_thi_gian>];
Trong <tn_hiu_ch> nhn gi tr ca <biu_thc>, ch l lnh after ch dng cho
m phng cn khi tng hp mch n s c b qua. Php gn song song tng ng mt
Process cha 1 php gn tn hiu.
V d m t mch AND v OR c cng 4 u vo nh sau:
...
architecture Behavioral of logic1 is
signal I1, I2, I3, I4, AND_out, OR_out: std_logic;
begin
...
AND_out<= I1 and I2 and I3 and I4;
OR_out<= I1 or I2 or I3 or I4;
...
end Behavioral;
191
Php gn tn hiu c iu kin l cu trc lch song song thc hin php gn gi tr ca cc
biu thc cho mt tn hiu ch ty theo cc iu kin t ra. C php chung:
<tn_hiu_ch> <= <biu_thc>[after <biu_thc_thi_gian>] when <iu_kin> else
<biu_thc>[after <biu_thc_thi_gian>] when <iu_kin> else
...
<biu_thc>[after <biu_thc_thi_gian>];
Cu trc php gn tn hiu c iu kin c th coi l cu trc song song ca lnh tun t If
c thay th tng ng vi Process cha lnh tun t if.
V d m t cu trc chn knh nh sau:
architecture ...
begin
Z <= A when Sel=00 else
B when Sel=10 else
C when Sel=11 else
X ;
end architecture;
192
architecture ...
begin
process(A,B,C, SEL )
begin
case (SEL) is
when 00 =>Z <= A;
when 10 =>Z <= B;
when 11 =>Z <= C;
when others =>Z<= X;
end case;
end process;
architecture ...
begin
process (A,B,C, SEL)
begin
case SEL is
when 00 => Z <= A
when 10 => Z <= B
when 11 => Z <= C
when others => Z <=
end case;
end process;
end architecture;
;
;
;
X;
e. Khi (Block)
Block bao gm tp hp cc cu trc lnh song song. Mt kin trc c th phn tch thnh
mt s c cu trc logic. Mi khi biu din mt thnh phn ca m hnh v thng c s dng
t chc mt tp hp cc cu trc song song phn cp. C php chung:
<nhn>: Block
{<phn_khai_bo>}
begin
{<cu_lnh_song_song>} c trnh t bt k
end block;
Khai bo b danh.
Khai bo component.
Lut use.
193
Php gi chng trnh con song song tng ng vi cc process bao gm cc php gi
chng trnh con tun t tng ng. Mi php gi chng trnh con tng ng vi mt process
khng cha dy danh sch cc tn hiu kch thch, phn khai bo rng v phn thn cha mt php
gi chng trnh con, tip theo l mt cu lnh wait.
9.2.8 Cu trc lnh tun t
Cu lnh if.
Cu lnh case.
Cc lnh lp.
a. Php gn bin
194
Clk
...
process( Clk )
variable
B, C, D : bit := 1;
begin
If ( Clkevent and Clk =1 ) then
D := C;
A
C := B;
B := A;
end if;
end process ;
Clk
bit := 1;
Begin
process( Clk )
begin
If (Clkevent and Clk =1) then
A
B <= A ;
C <= B ;
D <= C ;
Clk
end if ;
end process ;
End Behavior;
c. Lnh if
Lnh ny cho php cc php ton c thc hin trn mt iu kin no . C ba dng c
bn l:
+ Dng 1:
if (iu_kin) then
<Cc_cu_lnh_tun_t>;
end if;
+ Dng 2:
195
(iu_kin_2) then
<Cc_cu_lnh_tun_t>;
elsif
(iu_kin_3) then
<Cc_cu_lnh_tun_t>;
else
<Cc_cu_lnh_tun_t>;
end if;
(Sel =
Z <= A ;
elsif (Sel =
Z <= B ;
elsif (Sel =
Z <= C ;
elsif (Sel =
Z <= D ;
end if;
end process ;
then
A
B
01)
then
C
D
10)
then
11)
then
00)
Sel
d. Lnh case:
Lnh case c s dng trong trng hp c mt biu thc kim sot nhiu r nhnh
trong chng trnh VHDL. Cc lnh tng ng vi mt trong cc la chn s c thc hiu nu
biu thc kim sot c gi tr bng gi tr tng ng ca la chn . C hai dng c bn:
Dng 1:
Case (biu_thc_kim_sot) is
When <gi_tr_la_chn> =>
<Cc_cu_lnh_tun_t>;
When <gi_tr_la_chn> =>
196
(A, B, C, D, Sel )
case Sel is
when 00
when 01
when 10
when 11
=>
=>
=>
=>
Z
Z
Z
Z
<=
<=
<=
<=
A
B
C
D
A
B
;
;
;
;
C
D
end case ;
end process ;
Sel
Trong VDHL khi chng trnh m phng gp cu lnh Null n s b qua lnh ny v thc
hin lnh tip theo sau. Thng thng lnh Null dng ch trng hp khng thc hin ca lnh
mt cch tng minh khi c cc iu kin tr li gi tr true. Do lnh Null thng c dng
trong cc cu lnh case i vi nhng gi tr la chn khng cn thao tc. V d:
197
process
begin
(A, B, C, D, Sel )
case Sel is
when 00 =>
Z <= A ;
when 01 =>
Z <= B ;
when 10 =>
Z <= C ;
when others => Null;
B
C
end case ;
end process ;
Sel
f. Cc lnh lp
Lnh lp loop cha thn vng lp bao gm dy cc cu lnh s c thc hin khng hoc
nhiu ln. C php ca lnh lp nh sau:
[<nhn>:] [<s__lp>] loop
{<lnh_tun_t>}|
{next [<nhn>] [when <iu_kin>];}|
{exit [<nhn>] [when <iu_kin>];}
end loop [nhn];
- <nhn>: nhn ca vng lp v thng c dng xy dng nhng vng lp lng nhau,
trong mi vng lp c kt thc bi t kha end loop.
- <s__lp>: vng lp vi s lp for hoc vng lp while, v vng lp khng cha
cc s lp.
Vi nhng vng lp khng cha [<s__lp>], cc lnh trong dy lnh tun t s c
thc hin cho ti khi c ngt bi cu lnh exit. Trong cu lnh next cng c dng thay
i trnh t thc hin thn ca vng lp.
V d vng lp khng cha s lp:
Count_down: Process
Variable Min,Sec: integer range 0 to 60;
Begin
L1: loop
L2: loop
exit L2 when (Sec=0);
wait until CLKevent and CLK=1;
Sec:=Sec-1;
End loop L2;
Exit L1 when (Min=0);
Min:=Min-1;
Sec:=60;
End loop L1;
End process Count_down;
198
C_bus (7)
B_bus (7)
A
B_bus (6)
end process;
hoc:
C_bus (6)
.
..
process ( A, B_bus )
begin
for i in 0 to 7 loop
C_bus (i) <= A and
end loop ;
C_bus (0)
B_bus (0)
B_bus (i);
end process;
A
A
and
B_bus (i);
B_bus (6)
i:=i+1;
end loop ;
end process;
C_bus (7)
B_bus (7)
C_bus (6)
..
.
C_bus (0)
B_bus (0)
Behavioral
- Nhp thit k v m
phng nhanh hn.
RTL
AND_OR2
- M t chi tit hn v
ti u vi cng ngh.
- Nhp thit k v m
phng chm hn
DFF
Logic
Layout
CLB_
R5C5
CLB_
R5C6
200
Reset
201
D_in(2)
D_in(1)
REG_4
DFF
U3
DFF
U2
DFF
U1
DFF
U0
Q_out(3)
Q_out(2)
Q_out(1)
Q_out(0)
Rst
202
Keypad
Security_1
Front_Door
Rear_Door
Alarm_Siren
Window
Clk
Reset
entity Security_1 is
port (Clk, Reset : in std_logic ;
Keypad : in std_logic_vector (3 downto 0) ;
Front_Door, Rear_Door, Window: in boolean ;
Alarm_Siren : out boolean ) ;
end Security_1 ;
architecture Behavioral of
Security_1 is
constant Delay_Period : time := 20 s;
begin
process (Keypad,Front_Door,Rear_Door,Window)
begin
if (Front_Door or Rear_Door or Window ) then
If (Keypad = 0011) then
Alarm_siren <= false ;
else
Alarm_Siren <= true after Delay_Period ;
end if ;
end if ;
end process ;
end Behavioral;
H thng c biu din theo m hnh RTL bao gm tp cc thanh ghi v cc php ton
c thc hin trn d liu s nh phn c lu trong cc thanh ghi. Lung d liu v vic x l
d liu thc hin trn s liu c cha trong cc thanh ghi c coi nh l hot ng chuyn i
gia cc thanh ghi. V d m hnh RTL ny c s dng biu din cu trc b vi x l. H
thng s c biu din theo m hnh RTL khi chng c xc nh bi 3 thnh phn nh sau:
-
Combinatorial process
9.3.3.1. M t mch t hp
Clocked process
Mch logic t hp c th m t bng cc cu trc lnh song,
tuy nhin thng dng cc process t hp. Trong cc process t hp tt c cc tn hiu vo ca
mch t hp phi c a vo danh sch tn hiu kch thch.
begin
-- gn mc nh u ra
D
En
Q <= 0;
if
En = 1 then Q <= D ;
end if ;
end process ;
204
Q <= D ;
En
Tin trnh hot ng theo clock c th c m t thnh tin trnh ng b (danh sch tn
hiu kch thch ch c duy nht tn hiu clock, mi bin i ca mch c ng b theo sn
clock) hoc thnh tin trnh khng ng b.
V d m t hot ng ca Triger D lm vic theo sn dng vi cc tn hiu Reset khng
ng b nh sau:
process ( Clk, reset )
begin
if reset = 1 then
Q <= 0 ;
elsif (Clk`event and
Q <= D ;
end if ;
end process ;
D
Clk = 1)
then
Clk
Reset
end
reset =
elsif
then
end if ;
end if ;
process ;
D
and
Clk = 1) then
then
Q <= D ;
Q <= 0 ;
Clk
Reset
205
Tm li biu din h thng s theo m hnh RTL cn s dng cc cu trc thanh ghi
(Registers) v mch t hp (combinational logic), v d t datapath theo m hnh RTL nh hnh
v 9-5 sau:
206
Registe
rs
process (CLK)
-- Registers
begin
if (CLK'event and CLK = '1') then
Combinational Logic
X2 <= F(X1);
X3 <= G(X2);
X1 <= Y0;
end if;
end process;
9.3.4 Phng php m t theo m hnh hnh trng thi (my trng thi State Machine)
Yu cu m t
- Process t hp
- Xc nh u ra
- Process t hp
- nh gi mi trng thi
- Lnh Case
- nh gi cc iu kin u vo
- Lnh if/else
Inputs
Next State
Logic
Current
State
Register
Output
Logic
Outputs
Clock
207
Inputs
Next State
Logic
Output
Logic
Current
State
Register
Outputs
Clock
Inputs
Next State
Logic
Current
State
Reg
Moore
Mealy
Output
Logic
Clock
: My_State
: My_State
: My_State
Next_State
begin --architecture
208
:= 111000 ;
:= 101010 ;
:= 000011 ;
: My_State ;
( CLK , RST)
+ Tin trnh kim tra iu kin chuyn i trng thi (tin trnh Comb).
Comb: process
begin
. . .
209
UP='0'
S0
RESET
if UP='0' then
Z='1'
else Z='0'
UP='0'
S1
S2
Z='0'
Z='0'
UP='1'
UP='1'
UP='0'
UP='1'
UP='1'
UP='0'
S3
S9
Z='0'
if UP='0' then
Z='0'
else Z='1'
UP='1'
UP='0'
UP='1'
UP='0'
S4
S8
Z='0'
Z='0'
UP='0'
UP='1'
UP='1'
S7
S6
S5
Z='0'
Z='0'
Z='0'
UP='0'
UP='0'
UP='1'
UP='1'
UP='0'
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FSM IS
PORT (CLK,RESET,UP: IN std_logic;
Z : OUT std_logic);
END;
ARCHITECTURE BEHAVIOR OF FSM IS
SIGNAL sreg : std_logic_vector (3 DOWNTO 0);
SIGNAL next_sreg : std_logic_vector (3 DOWNTO 0);
CONSTANT S0 : std_logic_vector (3 DOWNTO 0) :="0000";
CONSTANT S1 : std_logic_vector (3 DOWNTO 0) :="0001";
CONSTANT S2 : std_logic_vector (3 DOWNTO 0) :="0010";
CONSTANT S3 : std_logic_vector (3 DOWNTO 0) :="0011";
CONSTANT S4 : std_logic_vector (3 DOWNTO 0) :="0100";
CONSTANT S5 : std_logic_vector (3 DOWNTO 0) :="0101";
CONSTANT S6 : std_logic_vector (3 DOWNTO 0) :="0110";
CONSTANT S7 : std_logic_vector (3 DOWNTO 0) :="0111";
CONSTANT S8 : std_logic_vector (3 DOWNTO 0) :="1000";
CONSTANT S9 : std_logic_vector (3 DOWNTO 0) :="1001";
SIGNAL next_Z : std_logic;
BEGIN
Sync: PROCESS (CLK)
BEGIN
IF CLK='1' AND CLK'event THEN
210
if RESET='1' then
sreg<= S0;
else
sreg <= next_sreg;
end if;
END IF;
END PROCESS;
Comb: PROCESS (sreg,UP)
BEGIN
CASE sreg IS
WHEN S0 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S9;
next_sreg<=S1;
END IF;
WHEN S1 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S0;
next_sreg<=S2;
END IF;
WHEN S2 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S1;
next_sreg<=S3;
END IF;
WHEN S3 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S2;
next_sreg<=S4;
END IF;
WHEN S4 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S3;
next_sreg<=S5;
END IF;
WHEN S5 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S4;
next_sreg<=S6;
END IF;
WHEN S6 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S5;
next_sreg<=S7;
END IF;
WHEN S7 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S6;
next_sreg<=S8;
211
END IF;
WHEN S8 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S7;
next_sreg<=S9;
END IF;
WHEN S9 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S8;
next_sreg<=S0;
END IF;
WHEN OTHERS => next_sreg<=S0;
END CASE;
END PROCESS;
Outputs: PROCESS (sreg,UP)
BEGIN
IF UP='1' THEN
if sreg=S9 then
Z<= '1';
else
Z<= '0';
end if;
ELSE
if sreg=S0 then
Z<= '1';
else
Z<= '0';
end if;
END IF;
END PROCESS;
END BEHAVIOR;
TM TT
Thit k vi s tr gip ca my tnh ca cc h thng k thut s c dng rng ri trong
cng nghip. Do , ta cn phi hiu cc khi nim khc nhau trong qu trnh thit k. Ngn ng
m t phn cng ph bin VHDL l loi ngn ng c trnh by trong chng ny. y l mt
ch rt rng nn chng ti khng th trnh by chi tit ca VHDL. Tuy nhin cc khi nim c
bn c trnh by y s gip cho chng ta hc nhng chi tit v ngn ng t nhng quyn sch
vit v VHDL
212
CU HI N TP CHNG 8 V CHNG 9
1.
2.
3.
4.
5.
6.
B.
C.
D.
B.
C.
Thiu tnh bo mt
D.
CPLD
B.
FPGA
C.
Vi x l
D.
SPLD
Mt tch hp cao.
B.
Bo m tnh bo mt ca thit k
C.
D.
B.
Ma trn kt ni
C.
B nh RAM
D.
Triger
B.
7.
8.
9.
10.
11.
12.
214
C.
Ma trn kt ni trung tm
D.
Vi x l
B.
C.
D.
Cu trc vo/ra.
B.
C.
D.
Nhp thit k, kim tra thit k, tng hp thit k,m phng nh thi, thc hin
thit k, cu hnh.
B.
Nhp thit k, kim tra thit k, thc hin thit k, tng hp thit k, m phng
nh thi, cu hnh.
C.
Nhp thit k, tng hp thit k, kim tra thit k, thc hin thit k, m phng
nh thi, cu hnh.
D.
Nhp thit k, kim tra thit k, tng hp thit k, thc hin thit k, m phng
nh thi, cu hnh.
File m t VHDL
B.
File cu hnh
C.
File netlist
D.
File s mch
File m t VHDL
B.
File cu hnh
C.
File netlist
D.
File s mch
13.
14.
15.
16.
17.
A.
B.
C.
D.
Lp trnh hp ng
B.
Lp trnh bc cao
C.
Lp trnh mng
D.
M t phn cng
B.
C.
D.
Lu cc kt qu trung gian
B.
C.
Lu nhng gi tr c nh
D.
Lu cc kt qu trung gian
A.
C.
Lu nhng gi tr c nh
D.
A:=1;
B.
A<=1;
C.
A<=1;
D.
A<=true;
215
18.
19.
A.
A<=true;
B.
A:=1;
C.
A<=1;
D.
A:=1;
A.
D
C
216
B.
D
C
C. D
C
D. C
D
20.
21.
D.
CLR
CLR
CLR
CLR
A.
D
C
B.
D
C
C.
D
C
D.
Q
217
22.
A.
23.
218
B.
C.
D.
Data Input
Positive Gate
CLR
Data Output
A.
B.
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '1';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='0') then
Q <= '0';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
24.
C.
D.
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '0';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '0';
elsif (G='0') then
Q <= D;
end if;
end process;
end archi;
Inverted Gate
PRE
A.
B.
219
25.
C.
D.
220
A.
B.
C.
D.
Z;
end archi;
Z;
end archi;
26.
A.
B.
downto 0);
begin
process (Clk, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (Clk'event and Clk='1')
then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='1')then
C.
D.
then
Q <= Q + 1;
end if;
end process;
end archi;
if (CLR='1') then
tmp <= "0000";
else tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='0')then
if (CLR='1') then
tmp <= "0000";
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
221
27.
222
28.
A.
B.
downto 0);
downto 0);
begin
process (Clk,ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='1')
begin
process (Clk,D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
C.
D.
downto 0);
begin
process (Clk,ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
downto 0);
begin
process (Clk)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
223
29.
224
30.
u vo d liu 4 bit
Clock sn dng
PRE
CE
Q[3:0]
u ra d liu 4 bit
A.
B.
C.
D.
225
31.
226
32.
A.
B.
downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
downto 0);
begin
process (C)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
C.
D.
227
33.
Clk
>
K
A.
C.
entity JKFF is
entity JKFF is
Port(J,K,Clk:in std_logic;
Port(J,K,Clk:in std_logic;
Q, notQ:out std_logic);
Q, notQ:out std_logic);
end JKFF;
end JKFF;
signal JK:std_logic_vector(0 to
1);
signal JK:std_logic_vector(0 to
1);
begin
begin
JK<=(J,K);
JK<=(J,K);
process(Clk)
process(Clk)
begin
begin
when "00"
=>
Null;
when "00"
=>
when "01"
=> Qtemp<='0';
when "01"
=> Qtemp<='0';
when "10"
=> Qtemp<='1';
when "10"
=> Qtemp<='1';
when others=>Qtemp<=not
Qtemp;
end case;
end if;
Null;
when others=>Qtemp<=not
Qtemp;
end case;
end if;
end process;
end process;
Q<=Qtemp;
Q<=Qtemp;
notQ<=not Qtemp;
notQ<=not Qtemp;
end Behavioral;
228
end Behavioral;
B.
D.
entity JKFF is
entity JKFF is
Port(J,K,Clk:in std_logic;
Port(J,K,Clk:in std_logic;
Q, notQ:out std_logic);
Q, notQ:out std_logic);
end JKFF;
end JKFF;
begin
begin
process(Clk)
process(Clk)
begin
begin
Q<=J; notQ<=K;
Q<=J; notQ<=K;
end if;
34.
end if;
end process;
end process;
end Behavioral;
end Behavioral;
'1'
J0 Q 0
J1 Q 1
J2 Q 2
>
>
>
K0 Q 0
K1 Q1
K2 Q 2
Clk
A.
architecture Behavioral of cau33 is
begin
notQ<=not Q;
J(0)<=Q(1) nand Q(2); K(0)<='1';
J(1)<=Q(0);
229
B.
architecture Behavioral of cau33 is
signal Clk: std_logic;
signal J,K,Q,notQ: std_logic_vector(0 to 2);
signal JK0,JK1,JK2: std_logic_vector(0 to 1);
begin
JK0 <=(J(0),K(0));JK1 <=(J(1),K(1));
JK2 <=(J(2),K(2));
notQ<=not Q;
J(0)<=Q(1) nand Q(2); K(0)<='1';
J(1)<=Q(0);
C.
architecture Behavioral of cau33 is
begin
process(Clk)
begin
if(Clk'event and Clk='1') then
case JK0 is
when "00"
=>
Null;
when "01"
=> Q(0)<='0';
when "10"
=> Q(0)<='1';
230
D.
architecture Behavioral of cau33 is
signal Clk: std_logic;
signal J,K,Q,notQ: std_logic_vector(0 to 2);
signal JK0,JK1,JK2: std_logic_vector(0 to 1);
begin
JK0 <=(J(0),K(0));JK1 <=(J(1),K(1));
JK2 <=(J(2),K(2));
process(Clk)
begin
if(Clk'event and Clk='0') then
case JK0 is
when "00"
=>
Null;
when "01"
=> Q(0)<='0';
when "10"
=> Q(0)<='1';
=>
Null;
when "01"
=> Q(1)<='0';
when "10"
=> Q(1)<='1';
=>
Null;
when "01"
=> Q(2)<='0';
when "10"
=> Q(2)<='1';
231
35.
C.
entity BCDto7seg is
entity BCDto7seg is
Port( BCD:in
Port ( BCD:in
std_logic_vector(3 downto
0);
std_logic_vector(3 downto
0);
Seg : out
Seg : out
std_logic_vector(6 downto
std_logic_vector(6 downto
0));
0));
end BCDto7seg;
end BCDto7seg;
begin
begin
--abcdefg"
Seg<= "1111110" when x"0",
end Beh;
232
--abcdefg"
Seg<= "1111110" when
x"0",
B.
D.
entity BCDto7seg is
entity BCDto7seg is
Port ( BCD:in
Port ( BCD:in
std_logic_vector(3 downto
0);
std_logic_vector(3 downto
0);
Seg : out
Seg : out
std_logic_vector(6 downto
std_logic_vector(6 downto
0));
0));
end BCDto7seg;
end BCDto7seg;
begin
begin
--abcdefg"
Seg<= "1111110" when x"0",
end Beh;
--abcdefg"
Seg<=
233
36.
C.
entity Mux is
end Mux;
signal I :
std_logic_vector(7 downto
0);
signal SEL:
std_logic_vector(8 downto
0);
std_logic_vector(2 downto
signal SEL:
std_logic_vector(4 downto
0);
0);
signal Y :std_logic;
begin
signal Y :std_logic;
begin
process
begin
case SEL is
--abcdefg"
Y <=
234
B.
D.
entity Mux is
end Mux;
signal I :
std_logic_vector(7 downto
0);
signal SEL:
std_logic_vector(7 downto
0);
std_logic_vector(2 downto
signal SEL:
std_logic_vector(2 downto
0);
0);
signal Y :
std_logic;
begin
signal Y :std_logic;
begin
process(I)
begin
case SEL is
--abcdefg"
Y <=
end Behavioral;
235
p n v hng dn tr li
P N V HNG DN TR LI
CHNG 1
1.
2.
3.
4.
5.
6.
CHNG 2
Bi 1.
1. a
2. b
Bi 2.2
1. c
2. b
Bi 2.3
d
Bi 2.4
d. Do u bng A+AB
Bi 2.5
- Mc logic v phn tch
- Tr truyn lan v phn tch
- Cng sut tiu th v phn tch
- H s ghp ti v phn tch
- phng v nhiu v phn tch
- Mt s tham s khc
Bi 2.6
c
Bi 2.7
c
Bi 2.8
- Nu c khi nim v ti u ho mch in cc h cng
236
p n v hng dn tr li
- Cng c ti u ho
- a ra v d v phn tch hiu qu k thut, kinh t ca vic ti u ho
Bi 2.10
a
Bi 2.11
d
Bi 2.12
c
CHNG 3
1.d
2.a
3.d
4.b
5.c
6.a
7.b
8.c
9.d
10.b
11.a
12.d
13.d
14.a
1.a
2.d
3.c
4.c
5.c
6.d
7.b
8.c
9.a
10.c
11.a
12.d
13.c
14.a
15.b
16.b
17.a
18.b
19.c
20.d
1.a
2.c
CHNG 4
CHNG 5
237
p n v hng dn tr li
3.c
4.b
5.d
6.a
7.c
8.d
9.d
10.c
11.a
12.b
13.d
14.c
15.c
16.a
17.d
18.b
19.a
20.a
21.b
22.d
23.b
24.a
25.b
26.c
27.c
28.d
29.c
30.a
31.b
32.d
33.c
34.a
35.c
38.d
39.b
40.a
1.c
2.a
3.b
4.d
5.b
6.b
7.c
8.c
9.a
10.d
1.a
2.c
3.c
4.b
5.c
6.a
CHNG 6
CHNG 7
238
p n v hng dn tr li
7.b
8.a
9.c
10.c
CHNG 8 V CHNG 9
1.C
2.D
3.C
4.D
5.C
6.D
7.B
8.D
9.D
10.C
11.B
12.B
13.D
14.D
15.B
16.A
17.C
18.D
19.A
20.D
21.D
22.A
23.C
24.B
25.D
26.A
27.B
28.C
29.C
30.C
31.B
32.A
33.C
34.D
35.A
36.B
239
Mc lc
240
Mc lc
MC LC
LI GII THIU ................................................................................................................................................. 1
CHNG 1: H M ......................................................................................................................................... 2
GII THIU ...................................................................................................................................................... 2
NI DUNG........................................................................................................................................................ 2
1.1. BIU DIN S....................................................................................................................................... 2
1.2. CHUYN I C S GIA CC H M ....................................................................................... 6
1.3 S NH PHN C DU........................................................................................................................ 8
1.4. DU PHY NG............................................................................................................................... 9
TM TT.......................................................................................................................................................... 9
CU HI N TP.......................................................................................................................................... 10
CHNG 2: I S BOOLE V CC PHNG PHP BIU DIN HM............................................ 11
GII THIU CHUNG..................................................................................................................................... 11
NI DUNG...................................................................................................................................................... 12
2.1 I S BOOLE ........................................................................................................................................ 12
2.2 CC PHNG PHP BIU DIN HM BOOLE ............................................................................. 12
2.3 CC PHNG PHP RT GN HM.............................................................................................. 14
2.4 CNG LOGIC V CC THAM S CHNH ....................................................................................... 16
TM TT........................................................................................................................................................ 26
CU HI N TP.......................................................................................................................................... 26
CHNG 3: CNG LOGIC TTL V CMOS................................................................................................ 29
GII THIU .................................................................................................................................................... 29
NI DUNG...................................................................................................................................................... 30
3.1. CC H CNG LOGIC ...................................................................................................................... 30
3.2. GIAO TIP GIA CC CNG LOGIC C BN TTL-CMOS V CMOS-TTL.............................. 40
TM TT........................................................................................................................................................ 43
CU HI N TP.......................................................................................................................................... 43
CHNG 4: MCH LOGIC T HP ........................................................................................................... 48
GII THIU CHUNG..................................................................................................................................... 48
NI DUNG...................................................................................................................................................... 49
4.1 KHI NIM CHUNG............................................................................................................................ 49
4.2 PHN TCH MCH LOGIC T HP ................................................................................................. 50
4.3 THIT K MCH LOGIC T HP..................................................................................................... 50
4.4 HAZARD TRONG MCH T HP .................................................................................................... 51
4.5. MCH M HO V GII M .......................................................................................................... 59
4.6 B HP KNH V PHN KNH....................................................................................................... 64
4.7. MCH CNG....................................................................................................................................... 66
241
Mc lc
4.8. MCH SO SNH. ................................................................................................................................67
4.9. MCH TO V KIM TRA CHN L. ............................................................................................68
4.10. N V S HC V LOGIC (ALU). ...............................................................................................70
TM TT ........................................................................................................................................................70
CU HI N TP..........................................................................................................................................71
CHNG 5: MCH LOGIC TUN T..........................................................................................................75
GII THIU. ...................................................................................................................................................75
NI DUNG ......................................................................................................................................................75
5.1. KHI NIM CHUNG V M HNH TON HC ............................................................................75
5.2. PHN T NH CA MCH TUN T ...........................................................................................76
5.3. PHNG PHP M T MCH TUN T. .....................................................................................81
5.4. CC BC THIT K MCH TUN T. .......................................................................................83
5.5 MCH TUN T NG B...............................................................................................................90
5.6. MCH TUN T KHNG NG B ..............................................................................................98
5.7. HIN TNG CHU K V CHY UA TRONG MCH KHNG NG B ..........................104
5.8. MT S MCH TUN T THNG DNG ...................................................................................108
TM TT ......................................................................................................................................................116
CU HI N TP CHNG 5...................................................................................................................116
CHNG 6: MCH PHT XUNG V TO DNG XUNG.......................................................................125
GII THIU ..................................................................................................................................................125
NI DUNG ....................................................................................................................................................126
6.1. MCH PHT XUNG .........................................................................................................................126
6.2. TRIG SCHMIT.................................................................................................................................129
6.3. MCH A HI I ..........................................................................................................................130
6.4. IC NH THI....................................................................................................................................134
TM TT ......................................................................................................................................................137
CU HI N TP........................................................................................................................................137
CHNG 7: B NH BN DN...................................................................................................................141
GII THIU ..................................................................................................................................................141
NI DUNG ....................................................................................................................................................141
7.1. KHI NIM CHUNG.........................................................................................................................141
7.2. DRAM .................................................................................................................................................144
7.3. SRAM..................................................................................................................................................145
7.3. B NH C NH - ROM ................................................................................................................146
7.4. B NH BN C NH ...................................................................................................................147
7.5. M RNG DUNG LNG B NH...............................................................................................151
TM TT ......................................................................................................................................................152
CU HI N TP........................................................................................................................................153
CHNG 8: LOGIC LP TRNH (PLD)......................................................................................................155
GII THIU ..................................................................................................................................................155
242
Mc lc
NI DUNG.................................................................................................................................................... 156
8.1. GII THIU CHUNG V LOGIC KH TRNH (PLD) ................................................................... 156
8.2 SPLD ................................................................................................................................................... 157
8.3. CPLD (Complex PLD)....................................................................................................................... 157
8.4. FPGA................................................................................................................................................... 159
8.5. SO SNH GIA CPLD V FPGA.................................................................................................... 161
8.6. QUY TRNH THIT K CHO CPLD/FPGA..................................................................................... 161
TM TT...................................................................................................................................................... 168
CHNG 9: NGN NG M T PHN CNG VHDL ........................................................................... 169
GII THIU .................................................................................................................................................. 169
NI DUNG.................................................................................................................................................... 170
9.1. GII THIU NGN NG M T PHN CNG VHDL ............................................................... 170
9.2. CU TRC NGN NG CA VHDL ............................................................................................. 171
9.3. CC MC TRU TNG V PHNG PHP M T H THNG PHN CNG S.... 199
TM TT...................................................................................................................................................... 212
CU HI N TP CHNG 8 V CHNG 9....................................................................................... 213
P N V HNG DN TR LI............................................................................................................ 236
CHNG 1 ................................................................................................................................................... 236
CHNG 2 ................................................................................................................................................... 236
CHNG 3 ................................................................................................................................................... 237
CHNG 4 ................................................................................................................................................... 237
CHNG 5 ................................................................................................................................................... 237
CHNG 6 ................................................................................................................................................... 238
CHNG 7 ................................................................................................................................................... 238
CHNG 8 V CHNG 9 ....................................................................................................................... 239
TI LIU THAM KHO................................................................................................................................. 240
MC LC.......................................................................................................................................................... 241
243
IN T S
M s : 497DTS210
Chu trch nhim bn tho
TRUNG TM O TO BU CHNH VIN THNG 1