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UPC PLL200 PON PRESSON CACUTS{T. SERIAL INPUT PLL FREQUENCY SYNTHESIZER ™ General Description ‘The PLL2001 is a CMOS LSI for PLL Frequency Synthesizer. 16bit Programmable divide -by~R counter and divide- by -N counter are set by serial data. ™ Features + 200MHz input capability GV.typ.FN) a +20MHz input capability GV.typ.Xw) = Pin Asignment R range = 5 to 65535 N range = 272 to 65535 + Lock Detect signal + Both Active and Passive filter can be use + FV and FR signal output terminals + Package 16PIN Dual — Inline ~ Plastic 16PIN Smal 1 — Outline — Plastic ™ Package Dimension ™ Block Diagre 1 = TE a xv SUBS] ere oom x oo Ls TYTPTTP TTT Tt yr ] ; 4 ‘16-BIT LATCH —p-berecror} — po TET Tt | para 10 | Hesse CLK 17-BIT SHIFT REGISTER PUMP t Ri TTT TTT rrr iit iW Tog, TTTTITT TTT ri rrr ry 201 _J 16-BIT-N COOTER Jt __s Rago BO -1 UPC PLL200° NPFON PREOSON CUTS ™ PIN Description (1 of 2) PIN name Funetion Xin (1) [These pins are connected to terminals of an external Xour (2) | pallarel resonant crystal. XIN may also serve as input for an externaly-generated reference signal, It has feed back resistor, so that can use capacitance coupling KOUT can be use for external circuit, FV @ There are buffered outputs from compare-divider (FY) FR (13) _ | and reference-divider (FR), Voo_@__| Power supply @.7~5.5)) Dor (5) | There are terminals for low pass filter. Doa (12) | Dor and Doa are tri-state outputs. OV (15) | These four outputs can be selected as follors. oP (16) Dor : Passive filter Doa : Active filter OV, OR : Differential filter Vss_©)__| Ground Fn @) Fin is a input for compare-divider. RANGE (14} It has feed back resistor, so that can use capacitance coupling. A input frequency range can be selected as follors, L.RANGE is_high A input range is SWHiz to 250Miiz (typ @ 5, 0¥) 1.0V p-p sine wave. 2.RANGE is low A input range is DC to 2Mllz (typ @ 5. 0¥) 1.5V p-p sine wave, MPC ron PeCSOn coca Ta PLL2001 ™ PIN Description @ of 2) PIN name | Function DATA (10) | There are a data and a clock inputs to a sift register. CLK (9) A serial data sifts when CLK changes low to high. The structure of sift register and input data format refer to Fig 1. LE (11) This is a write signal to latch. When LE is held high, write mode is active. The sift register is cleared at the falling edge of LE. LD (7) This is a unlock detect terminal. When PLL is unlocked, tone oe Divide ratio of Compare — Divider and Reference ~ Divider BQ A TEI sift direction data (RANGE Low l valid data (RANGE = High)- This is a selecting bit for latch of divide ratio CONTROL =High — set a Reference ~ Divider CONTROL = Low -> set a Compare — Divider When the all bits of N—latch (Compare-Divider) is cleared, stops count, thus current consumption decreases. When the all bits of R—latch (Reference ~ Divider) is cleared, the oscllator stops. The result of clear all bits of both N and R latch, |. a current consumption is within 10 uA. Figl MPC PLL2001 ®™ Setting a Divide Ratio data “A serial data must be input from MSB. +A serial data is latched at the rising edge of CLK, thus data must change at falling edge of CLK. + LE must be low while data are written to sift register. Data is trans — fer from sift register to Reference ~ Divider or Compare — Divider, when LE is held high. +A sift register is cleared at the falling edge of LE. It is applicable to save a current consumption. (all bits are 0) (see fig2) LE ® ®@ ol ®) @Set CONTROL = High @Clear sift register Set another bits = Low @Set all bits of Reference @Set all bits of Compare Divider = Divider = Low Fig2 ™ Phase Comparator = Low Pass Filter timing chart wey © Tee oy Som Eg Passive filter Active filter Differential filter MPC PLLe2001 = Typical Specification © Fiw Maximum Operating Frequency's © Fry Frequency-Input Sensitivity's Specification cation * specification (i)) /RANGE =H | — (ap S00 [Paves E (veer) ' A Hee wave hese Zh “| { z 80t Eiypiviae by 2120 5 | ee #4 rte, 700 700 TY Vo Pi OX1y Maxima operating Prequency's @ Supply Voltage(¥da)~ Guerent Consuaption's Syeetflcetion Specification XiVer ix: oats 1¥p cate (2 \LR Co (ea Mat 188 vol [eine eave } sphstbe wave ' =r a) +4 Xin veo 4 s2iviae by aloo a i wae oa) — ven ® Fru Input Frequency- Current Consumption ® Xw Input Frequéncy- Current Consumption's Specification Specification tam] [Yoo=ssv 1 Vop=s5v \! (Of pea aVe-r o~ Xin = 1Ve- 1y—| east 1 nha 1 sine wave) {|p | Fine wave Ip oy ° 100 200 Geis oa 0 ae) Fi Xw— UPC PLL200' PON EDSON OUTS TB. @ Electrical Characteristics Vas = 0V PARROT TABS ToT TORS — Tae Tae [wor ain] Op [ma [Supply Vol tage vpD - - at - |55 v Garrent Tol | 2T~S3| FHCOOME, VPP sine wave Consumption ‘XIN=10Miiz, 1YP-P sine wave -|- [13 | ma “L555 | FIN-IO0MIz, 1VP-P sine wave Aive1taa, WP-? sine vave | - | - | 25 | ma [Stand-by Current | IDD2 | 2.7~5.5| R-Latch,N-Latch is all “0” -]- |W) aa Maximum Operating | fmaxl| 2.7~3 3] PIN=IVP-P sine wave 60 | 140 | - | MHz [Frequency FIN T5 5| EMTGT 130 | 0] —_[ Mie Faax2| 2. 1~8.3| FINI, 5VP-P sine wave 10 [a | - | ee 4535.5 | RANGE-LOW 15 | 2 | - | woe faaxa| 2.1~3.3| XINIVP-P sine wave nie | = [re 45-55 15 | 22 | - | mz itiniman Operating Tain | 27~5.5| FIPIVE? sine vave MNGEHTG| ~ | -_| 5 | Miz Frequency FLIP? sine wave ENGE-LON| ~ | -_| 00 | Miz Taput Voltage | VIN 5 [XIN and FIN RANGE-HIGHD 7) ee Range FIN, XIN FIN (RANGE*LOW) 15] - | wo] Vv Toput Voltage | VI woos] -|-| Vv Range CL, DATA, LE Ww] —] = vit =T= [ey v == [eo ¥ aout Current Xun | TTR —[- fae [ax = |= fas [aa ML - - | 10] wa = [saa Tapat Current FIN [TTR T= ar ax ez Tit ~ [| - |e, aa = |= fio | wa Output Current 10H . 0.2) - - |] mA FV, DOP, LD, DOA aay = | mA FR O¥, 08 To [2 7~3.3] TOOT aap fe 75-55 [WOO aa - | | ma [Set-up Time tsul | 27~5.5 300] = = nS DATA-CLK, CLE—-LE | tsu2_| 2.7~5.5 see Fig3(next page) 300 | - - nS Hold Tine i [27s] wo [- [- | as UPC PON FRCSIN CEES UD. m Absolute Maximum Ratings PLL2001 Paraneter [abel] Value hits ones Suplly vo [~ -a.3~0.7 v Tapat Vol age rn oR VoRT |v —| [erating Teaperature]| VOR | —-a0~v80 e [storage Temperatve [STG | _—W0~eIes e [Soldering Teaperature] TS | __250:25 c [Soldering Time ts] 10.5205

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