R

FDR

FDR
D Flip-Flop with Synchronous Reset
Architectures Supported
FDR
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDR

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and
data output (Q). The synchronous reset (R) input, when High, overrides all other
inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data
on the D input is loaded into the flip-flop when R is Low during the Low-to-High
clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X3718

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDR should be placed
-- after architecture statement but before begin keyword
component FDR

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

453

FDR

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDR
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDR_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDR should be placed

-- in architecture after the begin keyword
FDR_INSTANCE_NAME : FDR
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R);

Verilog Instantiation Template

FDR FDR_instance_name (.Q
.C
.D
.R

(user_Q),
(user_C),
(user_D),
(user_R));

defparam FDR_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

454

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i