NED UNIVERSITY OF ENGINEERING AND TECHNOLOGY MASTER OF ENGINEERING (ELECTRONIC) SPRING SEMESTER, EXAMINATION- 2012 Dated: 28-05-2012 ‘Time: 3 Hours ‘Max Marks: 60 ADVANCED DIGITAL ELECTRONICS AND INTERFACING ‘TECHNIQUES— EL-503 Instructions: 1, Attempt all Questions 2, Open book, open notes Examination, The exchange of material during exam is strictly prohibited. Use of laptop/electronic gadgets is not allowed. Q41, a, “Complexity for minimum component costs has increased at a rate of roughly a factor of two per year.” Critically comment upon Gordon Moore’s Law stated above. Specifically comment upon: i, Challenges in the design of digital ICs , Control parameters in digital IC design Q1,b, The process flow for the CMOS digital IC design has not changed drastically. Critically comment upon the following in the light of above statement. Justify your argument by providing the solid evidences for each of the following: 1, Oxidation 2, Diffusion vs. ion implantation 3, Chemical vapor deposition Q2, The device and system performance trends for the interconnect levels and the multichip modules have evolved significantly. Critically comment on the following keeping in view the digital IC: 1, Interconnect level 1 (Die to package substrate) 2, Interconnect level 2 (Package Substrate to board) 3, Multichip modules (Die to board) 4, Interconnect delay Q3,a, Discuss the emergence of secondary effects due to device scaling. What is the consequence of device scaling on the performance of digital integrated circuits? Q3;b, What are the trends in the scaling down of digital electronic circuits? ProQ4, Discuss the impact of following parameters on the performance of traditional CMOS logic design approach: a, switching threshold b, Noise Margins ¢, Propagation delay d, dynamic power consumption e, Technology scaling and its impact on the inverter metrics How the modern digital IC design has evolved vis a vis the above parameters. Q5,a, Define the regenerative and non-regenerative circuits. Classify the high level logic circuits as well. Discuss the main elements of the complementary logic approach. Justify the use of NMOS as PDN and PMOS as a PUN. Implement the following gates using complementary logic: i, Inverter , AND iii, OR iv, NAND y,NOR vi, XOR Q5,b, Discuss the following in detail: i, Human machine interaction ii, Microcontroller and microprocessor architecture iii, A/D and D/A converter iv, International Technology Roadmap for Semiconductors (ITRS) ee I