Powerful
schematic
and layout
capabilities
for custom
IC design
platform
Key Benefit
* Fits into industry-standard analog and mixed-signal flows
Key Features
+ Powerful schematic editing
+ Integrated mixed-signal design environment
+ Pycell™-based schematic-driven layout
+ Powerful layout editor
+ Mixed-signal router
Aether™
Custom IC Design Platform
Introduction
Aether delivers a complete, integrated
solution for custom IC designs using
Openaccess™ as the native database. This
platform has several built-in modules such
as design manager (Aether-DM), technology
manager (Aether-TM), schematic editor
(Aether-SE), layout editor (Aether-LE),
schematic-driven layout (Aether-SDL),
mixed-signal simulation environment
(Aether-MDE), mixed-signal router (Aether-
MSR), etc
Aether also has tight integration with other
design tools such as the Aeolus™ SPICE
simulator, iWave™ waveform viewer,
Argus™ physical verification tool, and
RCExplorer™ parasitic RC extraction tool,
which complete Aether as a platform. While
these tools are seamlessly integrated with
Aether, each tool is available for standalone
use as well
Re
extraction
SDL
Figd, Aether Custom Design Platform
The platform supports iPDK (Interoperable
PDK) and other industrial standards. Aether
offers the ability to easily integrate to third-
party SPICE simulators as well as physical
verification tools, and hence, it fits into
current design environments. Italso offers
an easy-to-use design, implementation, and
verification environment with individual
tools designed for accuracy and faster
turnaround times.
Aether Schematic Editor
Aether-SE is a full-function schematic and
symbol editor. It supports many advanced
functions such as real-time ERC run,
inherited connection, etc. In addition,
Aether-SE supports import and export
standard formats like EDIF, CDL, HSPICE®,
and Spectre®. Other key features include:
+ Hierarchical schematic editing
+ iParand pPar to transfer parameters in
hierarchical schematics
+ Inherited connections for global nets
+ Advanced functions like No-ERC, Patch-
cord, etc.
+ High-performance net-tracing
+ Quick generation of symbol view from
schematic
+ Find and replace function for hierarchical
schematics
‘+ Smart EDIF-IN interface to migrate
legacy designs into Aether-SE@ 8 Avtar dane
Fig. Aether Mixed-Signal Design Environment
Aether Mixed-Signal Design Environment
‘Aether-MDE is seamlessly integrated with
Aeolus SPICE simulator and iWave, the
waveform viewer. This allows users to easily
set up pre-and post-layout simulation
environments and simulation control, check
simulation results through iWave, back
annotate voltage and current to schematics,
and perform cross probing between
schematics and waveform viewer.
Aether-MDE is designed to be easy to use
and significantly improves designer
productivity. Where needed, third-party
simulators can be seamlessly integrated to
Aether-MDE.
Aether Layout Editor
Aether-LE is a full-function layout editor,
offering the capability to easily create and
edit shapes such as rectangle, polygon,
path, bus, circle, arc, ete. It supports
parameterized cells such as Pycell, allowing
users to create and modify a device layout
easily and quickly. The system supports
advanced functions such as real-time DRC.
The integrated parasitic resistance and
capacitance extraction engine allows users
to extract point-to-point, pin-to-pin, or
whole net resistance on the fly.
The in-house Argus silicon-proven physical
verification tool is integrated into Aether,
and other third-party physical verification
tools can be seamlessly integrated as well,Fig5. Cross Probing: Layout Editor Analysis Results
Key features of Aether-LE include:
+ Hierarchical layout design
+ Parameterized cells, Veell, and Pycell
+ Automatic creation of labels
+ Real-time DRC
+ Automatic via drop
+ Creation and editing of guard rings
+ Automatic dummy metal fill
+ Metal slotting
+ Hierarchical tracing of nets and shorts
+ Hierarchical layout probing
+ Hierarchical shape alignment
+ Find and replace function
+ ESD path routing
+ Easy integration to popular physical
verification tools
+ Customization using TCL scripting
Aether Schematic-Driven Layout
The Aether-SDL capability is based on Pycell.
It can efficiently create the design layout for
flat or hierarchical design, SDL maintains
connectivity relationships between devices
or cells using fly lines as well as ensures DRC
and LVS clean layout. Aether-SDL features:
Fat and hierarchical SDL
Device and cell relative locations based
con schematic
ross probing among schematic, layout,
and device tree
Schematic-based guidelines for
placement of devices and routing of its
corresponding nets
Powerful ECO checking, device matching,
folding/unfolding, etc.
Real-time warning for shorts
Generation of DRC/LVS clean layoutFast and
accurate
SPICE
simulator
Aeolus™
Fast, High-Capacity Parallel SPICE Simulator
* Higher productivity without sacrificing accuracy
Key Features
‘Accuracy—as accurate as true SPICE
Capacity—large designs with over 10 million devices
Performance—up to 10X faster than true SPICE
RC reduction for post-layout simulation
Seamlessly works with leading custom design platforms
Introduction
Aeolus delivers SPICE-level accuracy with
excellent performance and capacity for the
most challenging analog and mixed-signal
designs. The tool can simulate the design of
10 million components.
Compared to traditional SPICE tools, Aeolus
has significant performance speedup and
gained additional speedup with its advanced
parallel technique.
Bee on
ed Aeolus
tow High”
Capacity & Performance
Fig. Aeolus Market Position
‘Accuracy
‘Aeolus has consistently shown the ability to
produce waveforms that are identical to the
leading “golden” SPICE simulators.
The tool is also architected to solve full-
circuit matrix using precise device equations
to produce accurate results for each time
step.
‘Simulation Result from a Leading SPICE
‘Simulation Result from Aeolus
Fig2. Simulation ResultsFast, visual
display
and
analysis of
simulation
results
Fast, High-Capacity Waveform Viewer and Analyzer
Benefits
+ Fast, easy-to-use analog and mixed-signal waveform viewer and analyzer
+ Protects investments
+ High capacity—over 100 GB of simulation data
+ Supports a variety of data formats and flows
+ Fits into users’ design environment, including Virtuoso™
Key Features
+ Powerful set of context-sensitive measurement tools
* Calculator
* Dynamic A-D and D-A evaluations
+ Eye diagram and histogram
* Cross probe—iWave and schematic
Introduction
Wave is a fast, high-capacity, easy-to-use
analog and mixed-signal waveform viewer
and analyzer. It supports:
+ Formats: tri, FSDB, MSO, VCD, etc.
+ High capacity (over 100 GB)
+ Measurement tools
+ Cross probing with schematics
+ Eye diagrams and histograms
+ A-Dand D-A conversions
Measurement Tools
Wave's measurement capabilities include:
+ General: Width, Difference, Data (X,Y),
Ydiff, etc
Figh. Wave Measurement Tools
iWave™
+ Time domain: Rise/Fall, Frequency,
Delay, ete
* Frequency domain: Highpass, Lowpass,
and Stopband functions
+ Statistics: Mean, Std_dev, Yield, etc
+ Level: Topline, Baseline, Amplitude, ete
* Sdomain: Frequency Value, etc.
Calculator
iWave supports more than 60 functions
including the following:
Basic: +, -, In, sqrt, etc.
+ Trigonometry: sin, cos, tan, etc.
+ Wave: max, xmax, avg, etc
+ Magnitude: real, img, phase, etc.
Fig. Calculator FunctionFast,
and
accurate
DRC/LVS
Argus™
Fast and Accurate DRC/LVS
Benefits
* Cost-effective, in-design DRC/LVS
+ Minimal learning curve
* Growing foundry support
Key Features
* High-performance dimensional, density and antenna checking
* User selectable region-based DRC
* Works with GDSII, OASIS and OpenAccess™
* Large layout verification
* Efficient short-finding
* Integrated debug environment—PVE physical verification debug and analysis
Introduction Argus DRC
‘Argus is a fast and accurate physical The key DRC features include:
verification system. Its multi-threaded
architecture is used to process commands
and data in parallel and makes it one of the
highest performing DRC/LVS tools. It uses
TCL-based language for rules—consistent + Interactive DRC
with industry standard run-sets. With the :
capability to support any angle layout, Argus
is an ideal solution for analog and mixed-
signal designs. Its built-in graphical debug
environment enhances user productivity + Support for fundamental DFM rules
and allows users to debug the output from
other leading third-party DRC tools. Argus
works with GDSII, OASIS, and OpenAccess
layout formats.
+ Graph and edge-based any angle DRC
High-performance dimensional, density,
and antenna checking
User selectable IP/block and region-
based DRC analysis
+ Select/unselect design rule checking
=
an
Fig. Argus DRC Flow Fig2. Argus LVS FlowAccelerate
design
closure with
fast
interconnect
analysis
RCExplorer™
Accelerate Interconnect Closure
Benefits
* Shortens design cycles using in-design, pre-LVS parasitic analysis
* Reduces post-extraction parasitic analysis from days to minutes
Highlights
DSPF/SPEF-based interconnect analysis and comparisons
Pin-to-pin interconnect analysis—resistance, capacitance, and delay
Layout based point-to-point resistance analysis
Handles large RC networks like power mesh
Interconnect calculator for RC estimation
Introduction DSPF/SPEF-Based Interconnect Analysi
RCExplorer offers fast interconnect analysis
using batch and interactive modes, This
includes DSPF/SPEF-based and layout-based
Using DSPF/SPEF data from third-party
layout parasitic extraction tools, RCExplorer
offers fast, batch mode interconnect
pin-to-pin and point-to-point analyses.
=a)
analysis of resistance, capacitance, and
delay on a pin-to-pin basis for one or more
selected nets (Fig2). RCExplorer can
compare resistance, capacitance, and delay
values between two different revisions of a
given design using the corresponding DSPF
or SPEF files.
With pre-defined threshold levels, users can
control the reporting of differences in R, C,
and delay numbers such that only the
values greater than the corresponding
threshold value are reported.
Figh. RCExplorer Usage Model
Fig2. Point-to-Point Analysis