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ISO5500 2.5-A Isolated IGBT, MOSFET Gate Driver: 1 Features 3 Description
ISO5500 2.5-A Isolated IGBT, MOSFET Gate Driver: 1 Features 3 Description
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ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
3 Description
2 Applications
PACKAGE
SOIC (16)
10.30 mm 7.50 mm
VREG
VCC1
VCC2
VIN+
UVLO
+
ISO - Barri er
V INDELAY
FAULT
Gate
Drive
VC
DESAT
DESAT
-
12 .3V
and
7.2 V
Fault
Logic
Q1b
Q1a
Q4
VOUT
Q S
VE
RESET
GND1
Q3
Q2b
Q2a
VEE-P
VEE-L
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
36
36
36
36
4 Revision History
Changes from Revision C (June 2013) to Revision D
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Page
Added the Thermal Information table inside the data sheet below the Absolute Maximum Ratings table ............................ 5
Changed row VIORM and VPR specification from VIORM of 1200Vpk to 680 Vpk....................................................................... 17
Changed 1200 VPK in the Regulatory Information table from 1200 VPK to 680 VPK ............................................................. 17
Page
Changed the REGULATORY INFORMATION table, VDE Column From: File Number: pending To: File Number:
40016131.............................................................................................................................................................................. 17
Changed the REGULATORY INFORMATION table, CSA Column From: File Number: pending To: File Number:
220991.................................................................................................................................................................................. 17
Page
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VIN+
16
VE
VIN-
15
VEE-L
14
DESAT
13
VCC2
12
VC
11
VOUT
3
4
RESET
FAULT
NC
10
VEE-L
GND1
VEE-P
ISOLATION
VCC1
GND1
Pin Functions
PIN
NO.
1
NAME
VIN+
I/O
DESCRIPTION
VIN
VCC1
Supply
4,8
GND1
Ground
Input ground
RESET
FAULT
NC
NC
VEE-P
Supply
Most negative output-supply potential of the power output. Connect externally to pin 10.
10, 15
VEE-L
Supply
Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected.
Connect at least pin 10 externally to pin 9. Pin 15 can be floating.
11
VOUT
12
VC
Supply
13
VCC2
Supply
14
DESAT
16
VE
Ground
Not connected
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1
Total output supply voltage, VOUT(total)
(VCC2 VEE-P)
(VCC2 VE)
(VE VEE-P)
MIN
MAX
UNIT
0.5
0.5
35
0.5
35
(VE VEE-P)
V
V
0.5
VCC2
VE 0.5
VCC2
0.5
Vo(peak)
0.5
VCC2
0.5
VCC2
2.8
20
mA
170
150
DESAT
Voltage at
Peak gate drive output voltage
Collector voltage, VC
Output current , IO
(1)
65
(1)
(2)
Electrostatic discharge
(1)
UNIT
4000
1500
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Supply voltage
VOUT(total)
NOM
MAX
UNIT
5.5
15
30
VOUT+
15
30 (VE
VEE-P)
VOUT
15
VC
Collector voltage
VEE-P + 8
VCC2
tui
0.1
tuiR
0.1
VIH
VIL
fINP
Input frequency
VSUP_SR
TJ
Junction temperature
40
TA
Ambient temperature
-40
(1)
(2)
s
s
VCC
0.8
(2)
25
V
V
520 (1)
kHz
75
V/ms
150
125
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76
JCtop
34
JB
36
JT
JB
TSHDN+
TSHDN-
UNIT
DW (SOIC) 16
PINS
C/W
35
Thermal Shutdown
185
173
TSHDN-HYS
12
PD
592
mW
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
TEST CONDITIONS
Quiescent
MIN
TYP
MAX
5.5
8.5
5.7
8.7
8.4
12
14
ICC1
Supply current
ICC2
Supply current
ICH
ICL
IEH
0.5
0.3
IEL
0.8
0.53
IIH
IIL
IFH
IFL
VIT+(UVLO)
VIT(UVLO)
VHYS
(UVLO)
IOH
300 kHz
Quiescent
300 kHz
IOL
IOF
VOH
1.3
1.9
IN from 0 to VCC
10
12
11.6
12.3
13.5
11.1
12.4
0.7
1.2
1.6
2.5
90
140
VC-1.5
VC-0.8
VC-0.15
VC-0.05
ICHG
IDSCHG
mA
A
A
mA
mA
2.5
mA
mA
10
10
mA
mA
10
See Figure 32
VOL
(1)
(2)
0.4
UNIT
1.8
A
230
mA
0.2
0.5
180
270
380
20
45
mA
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
TEST CONDITIONS
VDSTH
CMTI
MIN
TYP
MAX
6.7
7.2
7.7
25
50
UNIT
V
kV/S
TEST CONDITIONS
tPLH, tPHL
Propagation Delay
tsk-p
tsk-pp
tsk2-pp
tr
tf
tDESAT
RG = 10 , CG = 10 nF,
50 % duty cycle, 10 kHz input,
VCC2 VEE = 30 V,
VE VEE = 0 V, See Figure 16
through Figure 19, Figure 26,
Figure 47, Figure 49, and
Figure 50
(90%)
tDESAT
(10%)
tDESAT
(FAULT)
tDESAT
(LOW)
tRESET
(FAULT)
tUVLO
tUVLO
MAX
UNIT
200
300
ns
1.7
10
ns
45
ns
50
ns
50
55
ns
10
RG = 10 , CG = 10 nF,
VCC2 VEE-P = 30 V,
VE VEE-P = 0 V, See Figure 20
through Figure 25, Figure 48 and
Figure 51
ns
300
550
ns
1.8
2.3
290
550
ns
180
3
8.2
ns
13
(OFF)
2.8
tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN to VOUT) between two devices
operating at the same supply voltage, same temperature, and having identical packages and test circuits.
i.e. max
(2)
TYP
150
(ON)
tFS
(1)
MIN
(
(
))-
(
(
)
)
tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN to VOUT)
between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits.
i.e.
min = tPHL-min (VCC1, VCC2,TA ) - tPLH-max (VCC1 ,VCC2 ,TA )
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7
6
5
4
3
2
VCC1 = 4.5 V
VCC1 = 5 V
VCC1 = 5.5 V
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 3.6 V
1
0
-40
-20
40
20
60
80
100
120
6
5
4
3
2
VCC1 = 3.3 V
VCC1 = 5 V
1
0
140
100
50
Ambient Temperature ( C)
250
300
12
No Load
11
200
12
10
9
8
7
6
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
5
4
-40
-20
40
20
60
80
100
120
11
10
9
8
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
7
6
0
140
100
50
Ambient Temperature ( C)
250
300
fINP = 20 kHz
50
40
30
20
10
VCC2 = 15 V
VCC2 = 30 V
-0.1
-0.2
-0.3
-0.4
-0.5
IEH, VE - VEE = 0 V
IEH, VE - VEE = 15 V
IEL, VE - VEE = 0 V
IEL, VE - VEE = 15 V
-0.6
-0.7
-0.8
200
RG = 10 W
60
150
70
150
20
40
60
80
100
-20
-40
20
40
60
80
100
120
140
Ambient Temperature ( C)
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
VOUT = VC - 4 V
VOUT = VC - 15 V
-4.5
-5
-40
-20
40
20
60
80
100
120
VOUT = 2.5 V
VOUT = 15 V
7
6
5
4
3
2
1
0
-40
140
-20
140
130
120
110
100
TA = -40oC
TA = 25oC
TA = 125oC
10
15
20
25
30
28
27.5
27
26.5
26
25.5
25
0.2
0.4
0.6
0.8
140
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
IOUT = -650 mA
IOUT = -100 mA
-1.3
-1.5
-40
-20
20
40
60
80
100
120
140
1.2
1.4 1.5
28.5
120
TA = -40oC
TA = 25oC
TA = 125oC
29
100
Ambient Temperature ( C)
80
0.1
29.5
60
150
80
40
Ambient Temperature ( C)
160
90
20
Ambient Temperature ( C)
0.3
0.25
0.2
0.15
0.1
-40
-20
20
40
60
80
100
120
140
Ambient Temperature ( C)
ISO5500
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6
5
4
3
2
TA = -40oC
TA = 25oC
TA = 125oC
1
0
0
0.5
1.5
-0.21
-0.23
-0.25
-0.27
-0.29
-0.31
-0.33
-0.35
-40
2.5
-0.17
-0.19
-20
60
240
7.7
Propagation Delay (ns)
7.5
7.3
7.1
6.9
40
20
60
140
CL = 10 nF
220
210
200
tPLH at VCC1 = 3.3 V
tPHL at VCC1 = 3.3 V
tPLH at VCC1 = 5 V
tPHL at VCC1 = 5 V
190
6.7
-20
120
RG = 10 W,
230
6.5
-40
100
80
7.9
40
80
100
120
180
-40
140
-20
40
20
60
100
80
120
140
Ambient Temperature ( C)
Ambient Temperature ( C)
225
230
RG = 10 W,
225
CL = 10 nF
220
20
Ambient Temperature ( C)
215
210
205
tPLH
tPHL
CL = 10 nF
220
215
210
205
tPLH at VCC1 = 3.3 V
tPHL at VCC1 = 3.3 V
tPLH at VCC1 = 5 V
tPHL at VCC1 = 5 V
200
195
200
3
RG = 10 W,
3.5
4.5
5.5
190
14
16
18
20
22
24
26
28
30
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
1200
1000
800
600
400
200
0
0
10
20
30
40
50
60
70
80
90
1400
100
CL = 10 nF
350
300
250
200
VCC2 = 15 V
VCC2 = 30 V
150
-40
-20
60
80
100
120
140
RG = 10 W
1400
1200
1000
800
600
400
VCC2 = 15 V
VCC2 = 30 V
200
0
10
20
30
40
50
70
60
80
90
100
RG = 10 W,
CL = 10 nF
1.5
0.5
VCC2 = 15 V
VCC2 = 30 V
0
-40
-20
20
40
60
80
100
120
140
Ambient Temperature ( C)
18
RG = 10 W
15
40
Ambient Temperature ( C)
14
12
10
8
6
4
VCC2 = 15 V
VCC2 = 30 V
2
0
0
10
20
30
40
50
60
70
80
90
100
400
350
300
250
200
150
-40
VCC2 = 15 V
VCC2 = 30 V
-20
20
40
60
80
100
120
140
Ambient Temperature ( C)
10
20
1600
RG = 10 W,
400
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CL = 10 nF
8.5
8
7.5
7
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 3.6 V
VCC1 = 4.5 V
VCC1 = 5 V
VCC1 = 5.5 V
6.5
6
5.5
5
-40
-20
20
40
60
100
80
120
5 V / div
9.5
140
Ambient Temperature ( C)
3
2.5
2
1.5
ICH, IOUT = -500 mA
ICH, IOUT = -1 mA
ICL, IOUT = -1 mA
ICL, IOUT = -2 mA
1
0.5
0
-40
-20
20
40
60
80
100
120
140
Ambient Temperature ( C)
11
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
5.5 V
2
3
4
5
6
7
8
VE 16
VIN+
5.5 V
VEE-L 15
VINVCC1
FAULT
VOUT 11
VEE-L 10
NC
GND1
VEE-P 9
5V
2
3
4
5
6
7
8
VIN-
VEE-L
VCC1
GND1
DESAT
VCC2
15
14
12
RESET
VC
FAULT
VOUT
NC
VEE-L 10
GND1
VEE-P
VIN+
VE
VIN-
VEE-L
VCC1
GND1
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
ICC2
5V
0.1
F
2
3
4
5
6
7
8
VIN+
VE
VIN-
VEE-L
VCC1
GND1
RESET
DESAT
VCC2
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
VCC2
30 V
11
0.1
F
IOUT
16
15
14
0.1
F
5.5 V
0.1
F
13
0.1
F
12
11 VOUT
2
3
V1
Sweep
0.1
F
VEE-L 15
DESAT 14
VCC2 13
RESET
VC 12
FAULT
VOUT 11
NC
VEE-L 10
GND1
VEE-P 9
16
15
14
ICC2
13
IC
12
11
0.1
F
30 V
10
9
V2
5.5 V
6
IFAULT
10
12
DESAT
IC
VIN-
16
13
VE 16
GND1
VC 12
VIN+
VCC1
VCC2 13
RESET
VE
DESAT 14
GND1
VIN+
0.1
F
0.1
F
ICC1
0.1
F
ICC1
VIN+
VE
VIN-
VEE-L
VCC1
GND1
DESAT
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
12
11
30 V
0.1
F
10
9
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3V
2
3
4
5
0.4 V
6
IFAULT
7
8
VE
VIN+
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
FAULT
VC
16
15
NC
VEE-L
GND1
VEE-P
5V
13
12
5
6
0.1
F
30 V
10
VE
VIN+
VEE-L
VCC1
GND1
RESET
VC
FAULT
VOUT
NC
VEE-L 10
GND1
VEE-P
DESAT
VCC2
5V
0.1
F
1
5V
2
3
4
5
6
7
8
VIN+
VINVCC1
GND1
VIN-
VEE-L
GND1
VOUT
NC
VEE-L
GND1
VEE-P
4
5
12
VPULSE
0.1
F
4.7
F
IOUT
7
8
VE
VEE-L
DESAT
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
15
5V
0.1
F
14
4
0.1
F
5
30 V
11
10
2
3
13
12
16
15
14
13
VPULSE
12
30 V
11
10
0.1
F
4.7
F
IOUT
VIN+
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
0.1
F
12
11
10
IOUT
30 V
14 V
16
VOUT
VC
FAULT
13
11
VCC2
RESET
30 V
DESAT
VCC1
14
VE
15
VIN-
VIN+
16
14
11
VOUT
1
0.1
F
6
7
IOUT
VIN+
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
12
100
mA
0.1
F
30 V
11
VOUT
10
9
13
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SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
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5V
2
3
4
5
6
7
8
VIN+
VE
VIN-
VEE-L
GND1
15
0.1
F
0.1
F
5V
2
3
V1
VCC2
RESET
IE
14
DESAT
VCC1
16
VC
13
12
0.1
F
11
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
0.1
F
V2
10
1
5V
0.1
F
2
3
4
5
6
7
8
VE
VIN+
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
15
0.1
F
5V
0.1
F
2
3
14
13
V1
IDESAT
0.1
F
12
3k
V2
0.1
F
11
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
IE
15
0.1
F
14
V1
13
0.1
F
12
0.1
F
11
V2
10
9
16
SWEEP
VIN+
SCOPE
10
100 pF
VIN+
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
12
0.1
F
11
10
9
4.7
F
30 V
4.7
F
30 V
10 W
10
nF
VCM
0.1
F
2
3
4
3k
5
6
SCOPE
100 pF
7
8
VIN+
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
5V
0.1
F
14
13
12
11
10
9
3k
0.1
F
4.7
F
30 V
6
7
100 pF
10 W
10
nF
VCM
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
12
SCOPE
0.1
F
11
10
9
10 W
10
nF
VCM
14
VIN+
ISO5500
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5V
2
3
4
5
3k
6
7
100 pF
VIN+
VE
VIN-
VEE-L
DESAT
VCC1
GND1
VCC2
RESET
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
VIN
15
GND1
14
13
12
5V
SCOPE
0.1
F
11
10
4.7
F
3k
10
nF
VEE-L
DESAT
VCC2
RESET
10 W
VIN-
GND1
30 V
VE
VCC1
4
0.1
F
VIN+
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
14
13
VOUT
12
0.1
F
V1
4.7
F
11
10 W
10
10
nF
VCM
2
3
4
5
6
5V
3k
0.1
F
7
8
VIN+
VE
VIN-
VEE-L
VCC1
GND1
RESET
DESAT
VCC2
VC
FAULT
VOUT
NC
VEE-L
GND1
VEE-P
16
15
100
pF
12
0V
VIN+
50 %
0.1
F
14
0.1
F
V1
DESAT
13
VIN-
50 %
tr
tf
VOUT
0.1
F
4.7
F
90%
V2
11
10
50%
10 W
10
nF
VOUT
10%
tPLH
tPHL
A.
VIN-
tDESAT (FAULT )
tDESAT (10%)
50 %
50 %
7.2V
VDESAT
VIN+
VCC1
tDESAT (LOW)
50%
tDESAT (90%)
tr
VOUT
tf
90%
10%
90%
FAULT
50 %
50 %
50%
VOUT
10%
tPLH
tRESET (FAULT )
RESET
50%
tPHL
15
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
8 Detailed Description
8.1 Overview
The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE
= 600 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2), isolation
barrier.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
inputs, and FAULT alarm output. The power stage consists of power transistors to supply 2.5 A pullup and
pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection
circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core
consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to
convert the resulting low-swing signals into CMOS levels. The ISO5500 also contains undervoltage lockout
circuitry to prevent insufficient gate drive to the external IGBT, and soft turnoff feature which ensures graceful
reduction in IGBT current to zero when a short-circuit is detected.
ISO5500
VREG
VCC1
VCC2
VIN+
UVLO
+
ISO - Barri er
V INDELAY
FAULT
Gate
Drive
VC
DESAT
DESAT
-
12 .3V
and
7.2 V
Fault
Logic
Q1b
Q1a
Q4
VOUT
Q S
VE
RESET
Q3
Q2b
Q2a
VEE-P
GND1
VEE-L
16
ISO5500
www.ti.com
TEST CONDITIONS
(1)
UNIT
8.1
mm
0.012
mm
L(I02)
Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1
400
(2)
RIO
Isolation resistance
CIO
CI
(2)
MAX
mm
(1)
TYP
8.3
L(I01)
CTI
MIN
V
12
1.25
pF
pF
>10
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.space
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation
glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification.
All pins on each side of the barrier tied together creating a two-terminal device
TEST CONDITIONS
SPECIFICATION
679/480
After Input/Output safety test subgroup 2/3,
VPR = 1.2 x VIORM, t = 10 sec,
Partial discharge < 5 pC
816/576
VPR
VIOTM
VISO
RS
Insulation resistance
UNIT
1088/768
VPEAK/
VRMS
1275/900
6000/4243
6000/4243
7200/5092
> 109
Pollution degree
CSA
UL
Basic Insulation
Maximum Transient Overvoltage, 6000 VPK
Maximum Working Voltage, 680 VPK
(1)
(1)
17
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
TEST CONDITIONS
SPECIFICATION
Material Group
Installation Classification
II
I-IV
I-III
LIFETIME
SPECIFICATION
20 years
679/480
25 years
657/465
50 years
601/425
UNIT
VPEAK/VRMS
TEST CONDITIONS
MIN
TYP
MAX
530
347
64
Case Temperature
150
UNIT
mA
C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
600
500
VCC1 = 3.6V
400
300
VCC1 = 5.5V
200
VCC2 - VEE-P = 30 V
100
0
0
50
100
150
200
Case Temperature - oC
Figure 52. DW-16 JC Thermal Derating Curve per DIN V VDE V 0884-10 (VDE V 0884-10)
18
ISO5500
www.ti.com
ISO5500
DESAT
1 VIN+
PWM
DIS
ISO
CBLK
7.2V
270 A
2 VIN-
3 VCC1
DELAY
3.3V
to
5V
VCC2
UVLO
ISO - Barrie r
13
VREG
12.3V
VC 12
Q1b
15V
Q1a
VOUT 11
6 FAULT
I/P
14
FAULT
Q S
VE
16
Q3
Q2b
4,8 GND1
VREG
Q2a
15V
VEE-P
VCC2
LOAD
5 RESET
O/P
VEE-L 10,15
-HV
Normal Operation
Fault Condition
Reset
VIN+
Normal Operation
ISO
4
7.2V
VDESAT
VOUT
FAULT
lay
De
2
DIS
FAULT
RESET
6
19
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
ISO5500
VCC2
VCC1
VCC2
+15 V
15V
VC
VCC1
+15 V
VC
15 V-30 V
GND1
Power Device
Common
VE
0 V-15 V
GND1
ISOLATION
3 V - 5.5 V
ISOLATION
3 V - 5.5 V
Power Device
Common
VE
0 V-15 V
-15 V
0-(-15 V)
VEE-P
VEE-P
VEE-L
VEE-L
ISO5500
3 V - 5.5 V
VCC1
PWM
VIN+
VIN+
VCC1
VIN+
VCC1
3 V - 5.5 V
GND1
GND1
VIN+
PWM
VIN-
ISOLATION
VIN-
ISOLATION
VINVIN-
GND1
VOUT
VOUT
20
ISO5500
www.ti.com
ISO5500
VC
VIN+
Q1b
15V
Q1a
30V
On
VOUT
VOUT
Gate
Drive
Q1
Q3
Q2
VE
Q3
Slow
Off
Q2
0V
VGE
Off
Q1
Q2b
+15V
Q2a
15V
VE
VEE-P
VE
VGE
-15V
VEE-L
21
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
VCC2
VCC2
UVLO
On
11.1V
2V
VC
12.3V
15V
VIN+
Gate
Drive
12.3V
Q1b
Q1a
VOUT
VGE
VE
VOUT
Failsafe
Low
Q1
Q2
Q1
Q2
Q1
0V
R PD Q2
Off
Q2b
15V
Q2a
VEE-P
ISO5500
VE
+15V
VE
VGE
VEE-L
-15V
22
ISO5500
www.ti.com
VCC2
VC
ISO5500
15V
DESAT
VIN+
DESAT
-
CBLK
On
Gate
Drive
7.2V
Q4
Q1a
Q1b
VOUT
Dschg
7.2V
VDESAT
VCE
Q4
VOUT
VE
Fault Off
Slow
Off
Q3
Q2b
15V
Q2a
Fault
VEE-P
VEE-L
CBL K VDSTH
ICHG
100 pF 7.2 V
270 A
= 2.7 s
(1)
The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking capacitor
and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients at DESAT,
CBLK values smaller than 100 pF are not recommended. The nominal blanking time also represents the ISO5500
maximum response time to a DESAT fault condition.
If a short circuit condition exists prior to the turn-on of the IGBT, (causing the IGBT switching into a short) the soft
shutdown sequence begins after approximately 3 s. However, if a short circuit condition occurs while the IGBT
is already on, the response time is significantly shorter due to the parasitic parallel capacitance of the DESAT
diode. The recommended value of 100 pF however, provides sufficient blanking and fault response times for
most applications.
Submit Documentation Feedback
23
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault
condition. The use of VIN+ as control input implies non-inverting input configuration.
During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of
the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector
has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through
the IGBT.
In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and
the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of
the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and
also produces a Fault signal that is fed back to the input side of the ISO5500.
8.3.13 FAULT Alarm
The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the
gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and
a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed.
Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain
output, it requires a pull-up resistor, RPU, in the order of 3.3 k to 10 k. The internal signals DIS, ISO, and
FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.
VCC1
3.3V
ISO5500
VIN+
DIS
ISO
ISO
ISO - Barrier
VINRPU
FAULT
Q S
Sh
oc ort
cu
rs
FAULT
lay
De
DELAY
I/P
VIN+
PWM
IGBT
On
2
1
DIS
FAULT
O/P
RESET
GND1
FAULT
RESET
24
ISO5500
www.ti.com
VIN-
UVLO
(VCC2 VE)
DESAT DETECTED ON
PIN 14 (DESAT)
PIN 6 (FAULT)
OUTPUT
VOUT
Active
Low
Yes
Low
Low
Low
Low
High
Low
High
Low
Not active
No
High
High
25
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
PWM
3-PHASE
INPUT
1
2
3
4
5
6
ISO
5500
ISO
5500
ISO
5500
ISO
5500
ISO
5500
ISO
5500
FAULT
26
ISO5500
www.ti.com
3.3V
3.3
k
0.1
F
4
5
6
330 pF
7
8
ISO5500
V IN+
V IN-
VE
VEE -L
DESAT
V CC1
GND1
V CC2
RESET
FAULT
VC
VOUT
NC
VEE -L
GND1
V EE-P
16
15
100 0.1
pF F
0.1
F
DS (opt.)
100
14
D DESAT
+
13
12
Q1
4.7
F
15V
VCE
Rg
11
10
VF
0.1
F
Q2
15V
3-PHASE
OUTPUT
+
VCE
-
27
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
3.3
kW
0.1
F
4
5
6
330 pF
7
8
ISO5500
VIN+
VINVCC1
GND1
RESET
FAULT
NC
GND1
C
RF
4
5
6
7
8
VIN+
ISO5500
VIN-
VCC1
C
GND1
RF
4
5
RESET
FAULT
NC
GND1
VIN+
ISO5500
VINVCC1
GND1
RESET
FAULT
NC
GND1
Figure 64. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
9.2.2.5 Global-Shutdown and Reset
When configured for inverting operation, the ISO5500 can be configured to shutdown automatically in the event
of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open drain FAULT outputs of
multiple ISO5500 devices can be wired together forming a single, common fault bus for interfacing directly to the
micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FAULT
output disables all six gate drivers simultaneously; thereby, providing protection against further catastrophic
failures.
28
ISO5500
www.ti.com
4
5
6
7
8
to other
RESETs
to other
FAULTs
VIN+
ISO5500
VINVCC1
GND1
RESET
FAULT
NC
GND1
4
5
6
7
8
VIN+
ISO5500
VIN-
VCC1
C
GND1
4
5
RESET
FAULT
NC
GND1
VIN+
ISO5500
VINVCC1
GND1
RESET
FAULT
NC
GND1
Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration
9.2.2.7 Resetting Following a Fault Condition
To resume normal switching operation following a fault condition (FAULT output low), the gate control signal
must be driven into a 'gate low' state before asserting RESET low. This can be accomplished with a microcontroller, or an additional logic gate that synchronizes the RESET signal with the appropriate input signal.
29
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
4
5
6
7
8
VIN+
ISO5500
VIN-
VCC1
C
GND1
RESET
FAULT
NC
GND1
VIN+
ISO5500
VINVCC1
GND1
RESET
FAULT
NC
GND1
Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration
9.2.2.8 DESAT Pin Protection
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes
of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100 to 1 k resistor is connected in
series with the DESAT diode. The added resistance neither alters the DESAT threshold nor the DESAT blanking
time.
Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of
the DESAT input to VE potential at low voltage levels.
ISO5500
VE
VEE-L
DESAT
VCC2
VC
VOUT
16
15
100
pF
DS (opt.)
RS
14
DDESAT
13
12
15V
Rg
11
VEE-L 10
VEE-P
+
VFW
VFW-inst
+
15V
Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode
9.2.2.9 DESAT Diode and DESAT Threshold
The DESAT diodes function is to conduct forward current, allowing sensing of the IGBTs saturated collector-toemitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the
short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the
IGBT. This results in a charging current ICHARGE = CD-DESAT x dVCE/dt, charging the blanking capacitor.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ CBLANK / CD-DESAT.
Table 3 lists a number of fast-recovery diodes suitable for the use as DESAT diodes.
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 7.2 V n x VF (where n is the number of DESAT
diodes).
30
ISO5500
www.ti.com
MANUFACTURER
trr (ns)
VRRM-max (V)
PACKAGE
STTH112
STM
75
1200
MUR100E
Motorola
75
1000
MURS160T3
Motorola
75
600
UF4007
General Semi.
75
1000
BYM26E
Philips
75
1000
BYV26E
Philips
75
1000
BYV99
Philips
75
600
(2)
(3)
(4)
(5)
With:
and:
then:
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
POL-WC = 0.5 fINP QG
(VCC2
ron-max
roff-max
- VEE-P )
+
r
+
R
r
+
R
on-max
G
off-max
G
where
(6)
Once RG is determined, Equation 6 is to be used to verify whether POL-WC < POL. Figure 69 shows a simplified
output stage model for calculating POL-WC.
31
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
ISO5500
VCC2
VC
15 V
ron-max
RG
VOUT
QG
roff-max
15 V
VEE-P
ISO5500
VCC2
VCC2
VC
VC
15 V
15 V
V CC2 - VEE-P
VOUT
V CC2 - VEE-P
Ion
VOUT
RG
RG
CG
VE
CG
VE
15 V
VEE-P
Ioff
15 V
VEE-P
In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of VEE-P with
respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RG results
in a peak charge current of ION-PK = (VCC2 VEE-P)/RG. Solving for RG then provides the necessary resistor value
for a desired on-current via:
V
- VEE-P
RG = CC2
ION-PK
(7)
9.2.2.11.2 On-to-Off Transition
When turning the power device off, the current and voltage relations are reversed but the equation for calculating
RG remains the same.
Once RG has been calculated, it is necessary to check whether the resulting, worst-case power consumption,
POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5).
32
ISO5500
www.ti.com
9.2.2.12 Example
The example below considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = 5 V
Applying Equation 7, the value of the gate resistor is calculated with
15V - ( - 5V)
RG =
= 10
2A
(8)
Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields
4
2.5
(9)
Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG =
10 is fully suitable for this application.
9.2.2.13 Determining Collector Resistor, RC
Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall
times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it
might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK.
Reducing ION-PK is accomplished by inserting an external resistor, RC, between the VC- pin and the VCC2- pin of
the ISO5500.
ISO5500
ISO5500
VCC2
VC
VCC2
RC
VC
15 V
VOUT
C2 -
VC
VE
15 V
E- P
Ion-pk
VOUT
RG
VCC2 - VEE-P
Ioff-pk
RG
CG
VE
CG
VE
15 V
15 V
VEE-P
VEE-P
VCC2 - VEE-P
IOFF-PK
(11)
RC = R G OFF-PK - 1
ION-PK
(12)
33
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
9.2.2.13.1 Example
Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RC value of:
2A
RC = 10
- 1 = 3.33
1.5 A
(13)
VE
VEE-L
DESAT
VCC2
VC
16
15
13
12
11
VOUT
VEE-L
VEE-P
100 pF
14
MJD44H11
or
D44VH10
15 V
4.5 W
10 W
10
2.5 W
MJD45H11
or
D45VH10
15 V
5 V / div
CL = 10 nF
34
ISO5500
www.ti.com
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 74). Layer stacking should
be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and
low-frequency signal layer.
Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output VOUT and DESAT should be routed in the top
layer.
Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use VE as the ground plane.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2. On the gate-driver VEE-P and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing etc. see Application Note SLLA284, Digital Isolator Design Guide.
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
35
ISO5500
SLLSE64D SEPTEMBER 2011 REVISED JANUARY 2015
www.ti.com
12.3 Trademarks
All trademarks are the property of their respective owners.
36
www.ti.com
14-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
ISO5500DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO5500DW
ISO5500DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO5500DW
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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value exceeds the maximum column width.
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Addendum-Page 1
Samples
www.ti.com
14-Oct-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
14-Oct-2014
Device
ISO5500DWR
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
14-Oct-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO5500DWR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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