Ki Thua T VI Xu Ly PDF

I HC THI NGUYN
KHOA CNG NGH THNG TIN
Nguyn Trung ng
Bi Th Mai Hoa
GIO TRNH
K THUT VI X L
THI NGUYN, THNG 11 NM 2006
Gio trnh K thut Vi x l
LI NI U
Cng ngh thng tin ang c ng dng rng ri trong nhiu lnh vc khoa hc
cng ngh v cuc sng thng nht. Bn cnh khi lng phn mm h thng v ng
dng s, cng ngh phn cng cng pht trin v cng nhanh chng. C th ni
cc h thng my tnh c ci thin trong nhng khong thi gian rt ngn, cng
ngy cng nhanh hn, mnh hn v hin i hn.
Nhng kin thc c bn v v phn cng ca cc h thng my tnh lun lun l
i hi cp thit ca nhng ngi chn cng ngh thng tin lm nh hng cho ngh
nghip v s nghip khoa hc trong tng lai.
Gio trnh K thut Vi x l ny c vit trn c s nhng bi ging theo st
cng mn hc c thc hin ti Khoa Cng ngh thng tin trc thuc Trng
i hc Thi Nguyn t khi thnh lp n nay, v lun lun c sa cha b sung
p ng nhu cu kin thc ca sinh vin hc tp ti Khoa.
Gio trnh c chia thnh 5 chng:
Chng I gii thiu nhng kin thc tng quan c s dng trong k thut Vi x
l cc h m cch thc biu din thng tin trong cc h Vi x l v my tnh, cng
nh nhn nhn qua v lch s pht trin ca cc trung tm Vi x l.
Chng II gii thiu cu trc v hot ng ca cc n v x l trung tm t
P8085 n cc cu trc ca Vi x l h 80x86, cc cu trc RISC v CISC. Do
nhng ng dng thc t rng ln trong i sng, trong chng II c gii thiu thm
cu trc v chc nng ca chip Vi x l chuyn dng C8051.
Chng III cung cp nhng kin thc v t chc b nh cho mt h Vi x l k
thut v cc bc xy dng vi nh ROM, RAM cho h Vi x l.
Chng IV i su kho st mt s mch chc nng kh lp trnh nh mch iu
khin vo/ra d liu song song, mch iu khin vo/ra d liu ni tip, mch nh
thi v mch iu khin ngt.
Chng V gii thiu cc cu trc v cch xy dng phi ghp mt s thit b
vo/ra c bn cho mt h Vi x l nh bn phm Hexa, h thng ch th 7 thanh, bn
phm my tnh v mn hnh.
Cun gio trnh chc chn c nhiu thiu st, rt mong c s gp ca cc c
gi. Mi kin ng gp xin gia theo a ch.
B mn k thut my tnh Khoa Cng ngh Thng tin
i hc Thi Nguyn
Thi Nguyn
Hoc theo a ch Email dongnt@hn.vnn.vn
Nhm bin son
B mn K thut my tnh
CHNG 1. TNG QUAN V CC H VI X L

I.1. Cc h m
H m thng dng nht trong i sng l h m c s 10 (thp phn - Decimal),
s dng 10 k t s t 0 n 9. Ngoi ra, trong sn xut, kinh doanh cn c khi s
dng h m c s 12 (t - dozen).
Trong cc h thng my tnh, x l, tnh ton, ta s dng h m c s 2 (nh
phn - Binary), h c s 8 (bt phn - Octal), h c s 16 (Hexa). Tuy nhin, vic nhp
d liu hay a kt qu x l ta li dng h m c s 10.
Mt s N trong mt h m bt k c n +1 ch s, trong gm n ch s thuc
phn nguyn v l ch s thuc phn thp phn, c trin khai theo cng thc tng
qut:
R l c s ca h m
ak l trng ca ch s v tr th k (O < ak < R)
{ak}R = {0, 1, 2, 3,..., R - 1}
l, n l s nguyn
N = anan-1a1a0,a-1a-2a-1
Theo cng thc trn, cc s c biu din trong cc h m khc nhau s nh
sau:
I.1.1. H m thp phn (R = 10 - Decimal)
{ak}D
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}
123,45D = 1 x 102 + 2 x 101 + 3 x 100 + 4 x 10-1 + 5 x 10-2

I.1.2. H m nh phn (R = 2 - Binary)
{ak}B
= {0, 1}
11011.01B = 1 x 24 + 1 x 23 + 0 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2 =

= 16 + 8 + 0 + 2 + 1 + 0 + 0,25 = 27,25D
I.1.3. H m bt phn (R = 8 - Octal)
{ak}O = {0, 1, 2, 3, 4, 5, 6, 7}
653,12O = 6 x 82 + 5 x 81 + 3 x 80 + 1 x 8-1 + 2 x 8-2 =
= 384 + 40 + 3 + 0, 125 + 0,03125 = 427,1562D
Lu : Cc ch s trong h ny c th biu din nh 3 k t s ("0" v "1")
B mn K thut my tnh
trong h m nh phn theo bng sau:

Oct
Binar
Oct
Binar
Oct
Binar
Oct
Binar
al
al
al
al
0O
000B
2O
010B
4O
100B
6O
110B
1O
001B
3O
011B
5O
101B
7O
111B
I.1.4. H m 16 (R = 16 - Hexa)
{ak}H
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}
3A7,C H = 3 x 162 + 10 x 161 + 7 x 160 + 12 x 16-1=

= 768 + 160 + 7 + 0,75 = 935,75D
Lu : Mt gi tr k t s Hexa c th biu din thng qua 4 k t s h nh
phn theo bng sau:
Hex
Binarr Hex
Binarr Hex
Binarr Hex
Binarr
0H
0000B 4H
0100B 8H
1000B CH
1100B
1H
0001B 5H
0101B 9H
1001B DH
1101B
2H
0010B 6H
0110B AH
1010B EH
1110B
3H
0011B 7H
0111B BH
1011B FH
1111B
Nhn xt:
1. Trong cc h m va c nu, h m c s 2 c rt nhiu u im khi x l
trong my tnh. Th nht, vic m phng gi tr ca mt k t s l rt n gin: ch
cn mt phn t c hai trng thi khc bit. S dng bn cht vt l ca vt mang
thng tin biu din hai trng thi ny rt d thc hin. Trn dy dn in l cc
trng hp c dng in (tng ng vi trng s l 1) hoc khng c dng in
(tng ng vi trng s l 0).
2. Vic chuyn i gia hai gi tr 0 hoc 1 c th thc hin thng qua mt cng
tc, trong thc t l cc phn t logic in t thc hin cc chc nng ca kho in
t: ng (dng in i qua c) hoc m (dng in khng i qua).
I.2. Chuyn i ln nhau gia cc h m
I.2.1. H nh phn v h thp phn
a) T nh phn sang thp phn. S dng biu thc trin khai tng qut nu, cng
tt c cc s hng theo gi tr s thp phn, tng s l dng thp phn ca s nh
B mn K thut my tnh
phn cho.
V d. 11011.11B= 1 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2
= 16 + 8 + 0 + 2 + 1 + 0.5 + 0.25 = 27.75D
b) T thp phn sang nh phn:
Phn nguyn: Ta c ng thc sau (v tri l s thp phn, v phi l biu din nh
phn ca s ):
= kn2n + kn-12n-l + kn-22n-2 +... k121 + k020 + =
SD
= 2(kn2n-l + kn-l2n-2 + kn-22n-3 +... + k1) + k0

V Ki = {0, 1}, ng phn vi s 0, 1 trong s thp phn, nn ta c th vit:
SD-K0
2
=kn2n-1 + kn-12n-2 + kn-22n-3 + + k1 = 2(kn2n-2 + kn-12n-3 + + k2) + k1
Thy rng: K t u tin ca s nh phn l k0, ng vi s d khi chia SD cho 2,

k t tip theo, k1 chnh l s d khi chia thng cho 2, v. v... nn ta c th tm tt c
cc k t khc nh sau:
V d: i s l73D ra s nh phn
Vy 173D = 10101101B
Phn phn s: ng thc quan h gia s thp phn v s nh phn (phn phn s)
(v tri l s thp phn, v phi l s nh phn) nh sau:
SD
= k-12-1 + k-22-2 + k-32-3 + k-m+12-m+1 + k-m2-m
2SD
= k-1 + (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)
Thy rng k-1 tr thnh phn nguyn ca v phi, vy:

2SD k-1
= (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)
2(2SD - k-1)
= k-2 + (k-32-1 + k-m+12-m+3 + k-m2-m+2)
k-2 l phn nguyn tip theo ca v phi c th bng 0 hoc bng 1. Tip tc
tng t, thu c cc k t s ca cc phn t cn li.
V d: Chuyn i s 0.8128 thnh s nh phn
Thc hin php nhn lin tip vi 2, phn nguyn ca tch bao gi cng l cc gi
B mn K thut my tnh
tr hoc bng "0" hoc bng "1", thu c kt qu sau:

0.81281 x 2
= 1.6256
= 1 + 0.6256
0.6256
x2
= 1.2512
= 1 + 0.2512
0.25121 x 2
= 0.5024
= 1 + 0.5024
0.50241 x 2
= 1.0048
= 1 + 0.0048
0.0048
Qu nh c th b qua
x2
Lu : Qu trnh bin i ny kt thc khi phn phn s ca tch s bng 0, tuy

nhin, nu qu ko di, tu theo yu cu ca chnh xc d liu khi tnh ton v x
l, c th b qua.
I.2.2. H nh phn v h Hexa
Chuyn i mt d liu nh phn sang h Hexa rt n gin, nu ch rng ta c
2 = 16, c ngha l mt s Hexa tng ng vi mt nhm 4 s ca s nh phn (t 0
n F). V vy, khi chuyn i, ch cn thay nhm 4 ch s ca s nh phn bng mt
ch s tng ng ca h Hexa nh sau.
4
T hp
nh phn
K t
K
K t
K
T hp
T hp nh
T hp nh
s
t s
s
t s
nh phn
phn
phn
Hex
Hex
Hex
Hex
a
0000
0100
1000
11 0 0
0001
0101
1001
11 0 1
0010
0 11 0
1010
11 1 0
0 0 11
0 11 1
1 0 11
11 11
V d:
Lu : Phn nguyn c nhm tnh t v tr ca ch s c trng nh nht, phn

phn s c nhm tnh t v tr ca ch s c trng ln nht.
T cch chuyn i trn, d dng nhn ra php chuyn i ngc t mt s h
Hexa sang s h nh phn bng cch thay mt ch s trong h Hexa bng mt nhm 4
ch s trong h nh phn.
V d: F5E7.8CH = 1111 01011110 0111.1000.1100B
B mn K thut my tnh
I.3. Biu din thng tin trong cc h Vi x l

Cc h Vi x l x l cc thng tin s v ch. Cc thng tin c biu din di
dng m nht nh. Bn cht vt l ca vic biu din thng tin l in p ("0" ng vi
khng c in p, "1" ng vi in p mc quy chun trong mch in t) v vic
m ho cc thng tin s v ch c tun theo chun quc t. Mt bin logic vi ch
hai gi tr duy nht l "0" hoc "1" c gi l mt bit. Hai trng thi ny ca bit c
s dng m ho cho tt c cc k t (gm s, ch v cc k t c bit khc). Cc
bit c ghp li thnh cc n v mang thng tin y cho cc k t biu din cc
s, cc k t ch v cc k t c bit khc.
Bit (BInary digiT) l n v c bn ca thng tin theo h m nh phn. Cc mch
in t trong my tnh pht hin s khc nhau gia hai trng thi (in p mc "1" v
in p mc "0") v biu din hai trng thi di dng mt trong hai s nh phn
"1" hoc "0".
Nhm 8 bit ghp k lin nhau, to thnh n v d liu c s ca h Vi x l c
gi l 1 Byte. Do c lu gi tng ng vi mt k t (s, ch hoc k t c
bit) nn Byte cng l n v c s o cc kh nng lu gi, x l ca h Vi x l.
Cc thut ng nh KiloByte, MegaByte hay GigaByte thng c dng lm bi s
trong vic m Byte, d nhin theo h m nh phn, ngha l:
1 KiloByte
= 1024 Bytes,
1 MegaByte
= 1024 KiloBytes,
1 GigaByte
= 1024 MegaBytes.
Cc n v ny c vit tt tng ng l KB, MB v GB.

1.3.1. M ho cc thng tin khng s
C hai loi m ph cp nht c s dng l m ASCII v EBCDIC.
- M ASCII (American Standard Code for Information lnterchange) dng 7 bits
m ho cc k t.
- M ABCDIC (Extended Binary Coded Decimal Interchange Code) dng c 8 bits
(1 Byte) m ho thng tin.
- Loi m c dng trong ngnh bu in, trong cc my teletype l m
BAUDOT, ch s dng 5 bits m ho thng tin.
I.3.2. M ho cc thng tin s
Cc s c m ho theo cc loi m sau:
B mn K thut my tnh
- M nh phn s dng cc s c biu din theo h m nh phn nh nu

trn.
- M nh thp phn (BCD Code - Binary Coded Decimal Code) s dng cch
nhm 4 bits nh phn biu din mt gi tr thp phn t 0 n 9. Cc gi tr
vt qu gii hn ny (> 9) khng c s dng.
I.3.3. Biu din d liu s trong my tnh
Biu din d liu l s nguyn c du: Gi s dng 2 bytes (16 bits) biu din
mt s nguyn c du, bit cao nht (MSB - Most Significant Bit) c dng nh
du. S dng c bit du S = "0", s m c bit du S = "1".
D15 D14 D13 D12 D11 D10 D9
S
D8
D7
D6
D5
D4
D3
D2
D1
D0
- Biu din d liu l s thc c du: V nguyn tc, du ca s vn l gi tr ca

MSB nh quy c trn. C hai dng s c du phy c s dng trong my tnh:
S du phy tnh (fixed point) v s du phy ng (foatting point).
+ Du phy tnh s phn chia chui ch s thnh phn nguyn v phn phn s. V
d ta c th vit:
0011101.01101101
Nhng ni chung, trong cc my chuyn dng, thng phi tm mt phng php
thch hp c th biu din s c du phy c nh m du phy c t ngay sau
du, ngha l s du phy tnh c dng:
0.knkn-1kn-2k1k0
+ Du phy ng c dng rt ph bin, dng chun tc nh sau:
N = F x 2
trong : F l phn nh tr (Mantissa)

E l phn c tnh (Exponent - s m)
Theo nguyn tc ny, mt s thc c biu din trong cc my 32 bit nh sau:
S c biu din c gi tr thc tnh theo biu thc:

N = (-l)s x 2E-127 x F
Vi cch biu din ny, c th thy ln ca cc s nh sau:
S dng:
+3.4 x 1038 < N < +3.4 x 10-38
s m:
- 3.4 x 1038 < N < - 3.4 x 10-38
B mn K thut my tnh
Lu : Khi kt qu php tnh vt qu cc gii hn trn, nu s m (exponent) l

dng, s c coi l - hoc + . Trong trng hp s m l m v vt qua s m
cc i cho php, kt qu c coi l bng 0.
Dng s chnh xc gp i (Double precision) c biu din nh sau (64 bits):
V gi tr thc c tnh theo biu thc: N = (-l)s x 2E-l023 x F.

Cng cn lu rng, i vi cc d liu s c du thun tin cho x l v tnh
ton, trong my thng c biu din di cc dng m thun, m ngc
(complement) hoc m b 2 (two-complement). Gi s ta c s A=+0.10010, cc m
trn u biu din nh nhau, nhng vi s B = -0.10010 th s c biu din nh sau:
Bnh thng
A = -0.10010
M ngc
A = 1.00110 (b 1, tc l o cc ch s trong s )
M b 2
A = 1.00111 (tng ng vi b 1 cng thm 1)
I.3.4. Bn cht vt l ca thng tin trong cc h Vi x l

Trong cc h Vi x l, thng tin v cc gi tr "0" hay "1" c biu din thng
qua mt mc in p so vi mc chun chung, thng l t (GND - GrDund). ln
ca in p biu din cc gi tr ny ph thuc vo cng ngh c s dng to nn
phn t mang thng tin. i vi cc mch t hp TTL (Transistor-Transistor-Logic),
cc mc in p c m t trong hnh I.1
Hnh 1.1. Phm vi mc cao "1" thp "0" Ca mch TTL

Ta thng dng k hiu VH ch mc cao, VL ch mc thp. Trong mch TTL,
ta dng mc cao mc thp ch in p cao, in p thp so vi in p chun
chung. Cc mc cao, thp khng phi l mt gi tr c nh, m l mt vng gii hn
cho php. Ngoi phm vi nu, vng khng thuc hai mc trn l vng khng chc
chn, khng xc nh.
B mn K thut my tnh
Vt mang thng tin v cc gi tr "0" hoc "1" l mt mch in t c bit, m

u ra ca n s tng ng vi mt trong hai mc trn, c gi chung l Flip-Flop.
Tu theo yu cu s dng, cc Flip-Flop c cc kh nng thu nhn cc tn hiu vo v
a tn hiu ra theo nhng quy lut nht nh (Hnh I.2)
I.4. Vi nt v thc hin cc php tnh trong h m nh phn
Php cng v php tr hai s nh phn 1 bit c thc hin theo quy tc nu trong
bng sau:
A
Carr (Nh)
Hiu
Carrow (Mn)
I.4.1. Php cng v php tr

a) Php cng i s cc s hng du phy c inh
i vi php cng i s: Thc hin bnh thng. Trong trng hp c mt ton
hng l mt s m ta s dng m ngc hoc m b 2 ca n, hiu chnh kt qu theo
cc quy tc thng qua cc v d minh ho sau:
B mn K thut my tnh
10
Thy rng:
S biu th kt qu s l m thun nu l mt s dng.
S biu th kt qu l m ngc nu ta dng m ngc i vi s hng m v
cho kt qu l mt s m
S biu th kt qu l mt s b 2 nu dng m b 2 i vi s hng m v kt
qu l mt s m.
b) php cng i s cc s hng du phy ng:
i vi php cng i s cc s hng du phy ng, cn tin hnh cc bc sau:
Cn bng phn c tnh (s m) bng cch dch chuyn phn nh tr
c tnh ca tng bng c tnh chung
nh tr ca tng bng tng cc nh tr
Chun ho kt qu nu cn.
I.4.2. Php nhn v php chia
a) Php nhn:
i vi php nhn cc ton hng du phy tnh, vic quan trng l phi xc nh
du ca kt qu, theo hu ca kt qu bng tng modulo 2 ca cc bit du. Tr s
ca tch l kt qu ca php tnh tin (dch phi) v php cng.
Vi cc ton hng c du phy ng, du ca tch c xc nh nh php nhn
vi du phy tnh, sau tin hnh tm tch s nh sau:
Cng phn c tnh (s m), kt qu l c tnh ca tch.
Nhn phn nh tr, khng n du ca cc ton hng.
b) Php chia:
i vi php chia cc ton hng du phy tnh, vic quan trng l phi xc nh
du ca kt qu, theo du ca kt qu bng tng modulo 2 ca cc bit du. Tr s
ca thng s l kt qu ca php dch tri v php tr.
Vi cc ton hng c du phy ng, du ca thng s c xc nh nh php
B mn K thut my tnh
11
chia vi du phy tnh, sau tin hnh tm thng s nh sau:

Tr phn c tnh (s m), kt qu l c tnh ca thng s
Chia phn nh tr, khng n du ca cc ton hng
Nhn xt: D dng nhn thy rng cc php tnh s hc nu trn chung quy li vn
ch yu l thc hin php cng v php dch (shift).
I.5. Cu trc ca h Vi x l v my vi tnh
I.5.1. Vi nt v lch s pht trin cc trung tm Vi x l
S xut hin ca my tnh in t (MTT) vo khong nm 1948 m ra mt
trang mi trong nghin cu khoa hc ni chung v khoa hc tnh ton ni ring.
Nhng phi mi n nm 1971 , cc h Vi x l mi bt u xut hin. S ra i ca
Single chip 4-bit Microprocessor Intel 4004 P4004) vo nm thc s l mt cuc
cch mng trong ngnh cng nghip my tnh. C th ni P4004, vi di t x l
4 bits, lm i thay ton b cch nhn nhn v cc thit b u cui ca MTT, hay
cc c cu chp hnh trong iu khin qu trnh. P4004 c th qun l trc tip 4K t
lnh 8bit ca b nh chng trnh v 5120 bits b nh d liu RAM. CPU cn c 16
thanh ghi ch s c s dng lm b nh tm cho d liu. Vi tp lnh gm 46 lnh,
P4004 chim c nhiu u th trong cc ng dng thc t lc by gi. Tip tc
ca dng P 4bit ny l P4004, c nhiu ci tin mnh m so vi P4004 v mt lot
cc chip chc nng, chip nh ra i. Trong giai on tip theo t nm 1974 n 1 977,
Intel i u trong vic ch to cc CPU 8bit, P8008, P8080 v c bit l
P8085, nhng CPU c BUS d liu 8 bits v BUS a ch 16 bits. Cc loi CPU ny
c kh nng qun l dc 64K t nh ca b nh v 256 thit b ngoi vi. iu
ng ch P8085 l cng ngh dn knh v chia s thi gian hp l trn
BUS cho php a ra thm nhng tn hiu iu khin rt mnh, cho php xy
dng nhng my vi tnh u tin.
Khong thi gian nm 1978 n nm 1982 l giai on ra i v pht trin mnh
m ca cc trung tm Vi x l 16 bits. c bit cui giai on ny l s xut hin
cc trung tm Vi x l P8088, P8086, vi kh nng x l d liu 16 bits v BUS a
ch 20 bits, c s dng to ra cc my vi tnh XT, c a mm lu gi
chng trnh ng dng v d liu.
Tip theo ca giai on ny l s pht trin v bo ca cc loi P80186,
P80286, 80386SX, 80486-SX v 80486-DX, vi nhp ng h ln n IOOMHZ.
My vi tnh AT v cc my tnh PC ra i trong giai on ny gi thnh cn rt
cao, nhng tr thnh rt thng dng trong i sng con ngi.
T khong gia nhng nm 1993 tr li y, cc trung tm vi x l Pentium ra
B mn K thut my tnh
12
i, tc ngy cng cao, vi nhp ng h ln n hng GHZ, v s xut hin ca

cc trung tm x l a phn lung nh cc chip Pentium IV hin nay.
I.5.2. Cu trc c bn ca h Vi x l
Cc khi chc nng c bn ca mt h Vi x l (hnh I.3) gm:
- n v x l trung tm (CPU)
- B nh ROM, RAM
- Thit b vo (nhp d liu - Input device)
- Thit b ra (a d liu ra - Output device)
Ngoi ra cn phi k n khi to xung nhp (Clock Generator) v khi ngun
(Power Supply).
Hnh I.3. S khi cu trc c bn h Vi x l

Cc khi chc nng c bn c ni vi nhau qua mt tp ng dy truyn dn
tn hiu in gi l BUS h thng. BUS h thng bao gm 3 BUS thnh phn: BUS a
ch, BUS d liu v BUS iu khin. Thit b vo/ra thng c ghp ni vi BUS h
thng thng qua giao din ghp ni (I/O lnterface).
n v x l trung tm (Central Processing Unit - CPU) l khi chc nng c bn
nht to nn mt h Vi x l hay my tnh c nhn (Personal Computer - PC). My
vi tnh l mt trong nhng ng dng c th ca mt h thng gi l H Vi x l.
a) CPU thc hin chc nng x l d liu thng qua cc hot ng chnh sau:
c m lnh - c tp cc bit thng tin "0" hoc "1" t b nh chnh
Gii m lnh - to cc xung iu khin tng ng vi m lnh iu khin

hot ng ca cc khi chc nng khc
Thc hin tng bc cc thao tc x l d liu theo yu cu ca lnh.
Bn trong CPU c cc thanh ghi (Registers):
B mn K thut my tnh
13
Thanh ghi con tr lnh IP (Instruction Pointer), trong cc trung tm vi x l

trc y cn gi l thanh m chng trnh PC (Program Counter) cha a
ch ca lnh k tip cn c thc hin trong tun t thc hin chng trnh
Cc thanh ghi a dng khc GPRS (General Purpose Registers) lu tr tm
thi d liu, kt qu trung gian hay trng thi ca h thng cng vi n v s
hc v logic ALU (Arithmetic and Logic Unit) thc hin cc thao tc x l d
liu
n v iu khin CU (Conlrol Unit) l thnh phn phc tp nht, c chc
nng gii m lnh v to cc tn hiu iu khin hot ng ca ton h thng.
b) B nh chnh c t chc t cc t nh, trong IBM/PC t nh c di 1 byte
(8 bits). B nh ny gm cc chip nh ch c ROM (Read Only Memory) v cc chip
nh truy xut ngu nhin RAM (Random Access Memory) c tc truy cp nhanh.
B nh c s dng cha cc chng trnh v cc d liu iu khin hot ng
ca h thng. CPU nhn cc lnh t y khi ng h thng. Cc chng trnh ng
dng v d liu c th c cha ROM hoc RAM, cc kt qu trung gian hay kt
qu cui cng ca c c t hao tc x l c th dc cha trong c c thanh ghi a dng
hoc trong khi nh RAM
c) Cc mch ghp ni vo/ra l cc mch in t cho php CPU trao i d liu
vi cc thit b ngoi vi nh bn phm, mn hnh, my in... lm giao din vi ngi
dng hoc cc b chuyn i s-tng t DAC (Digital/Analog Converter), chuyn
i tng t-s ADC (Analog/Digital Converter), cc mch vo/ra s Do (Digiral
Outputs), DI (Digital Inputs)...
d) H Vi x l cn c mt mch to xung nhp gi l ng h h thng (Clock
Generator) iu khin v duy tr hot ng ng b ca tt c cc khi chc nng. B
to xung ny c iu khin bng mt mch thch anh c tn s thch hp v m
bo tn s lm vic n nh cho ton b h thng.
e) Mt khi ngun nui (Power Supply) cung cp nng lng cho h thng t
mng in li.
B ngun ca cc h Vi x l thng thng l b ngun xung vi k thut ngngt dng bn dn cng sut (Switching Power Supply), va gn nh cng sut ln li
va m bo gn sng nh nht v kh nng chng nhiu cao. Hnh I.4 l s
khi ca b ngun ng-ngt. in p li (220VAC) c chnh lu trc tip, lc
bng t ho cung cp cho mt b dao ng tn s cao (t 20KHZ n 40KHZ). Cc
xung in p tn s cao c chuyn sang bin p xung cng sut h p. in p li
ra ca bin p xung c chnh lu v lc thnh in p ngun mt chiu cung cp
cho h thng. Nguyn l n p y l thay i rng ca cc xung c tn s n
nh do vy s dao ng ca in p u ra khi c ti c chuyn qua b cm bin
iu chnh rng ny, m bo s n nh ca in p ra.
B mn K thut my tnh
14
Hnh I.4. S khi b ngun nui my tnh

I.5.3. T h Vi x l n my vi tnh PC
Trong thc t, cc h Vi x l hin i c trang b thm nhiu thit b ngoi vi
tin dng tu theo yu cu, mc ch s dng v c giao din thn thin vi con ngi.
l cc my vi tnh PC. Cng c th l nhng h Vi x l chuyn dng cho nhng
mc ch tnh ton hay iu khin.
a) My tnh x l d liu: L cc my tnh c dng tnh ton x l cc d
liu nh qun l nhn vin trong c quan, tnh ton tin lng, tnh ton kt cu cng
trnh, phn tch d liu trong kinh doanh, v.v... Quan im ng cho rng my tnh ch
gm CPU v b nh chnh, cn cc thit b ph tr khc nh bn phm, my in, cc
a cng, a mm, CD, chut, mn hnh, my in..., l nhng thit b ngoi vi. Cc
chng trnh x l d liu c lu gi trong b nh chnh hoc trong cc a, c
nhim v x l nhng d liu c ngi dng nhp vo v a kt qu x l ra mn
hnh, in ra giy hoc lu gi trong cc a. nh gi tnh nng v cht lng ca
cc my ny, ta thng cn c vo tc x l d liu, dung lng b nh, a, cht
lng mn hnh, my in v.v...
Hnh I.4. My Vi tnh PC

b) My tnh l b x l s: i vi cc my tnh ny, thi gian dnh cho x l d
liu rt nh, cn thi gian tnh ton, x l cc s liu li v cng ln. Cc my tnh
loi ny c s dng ch yu trong cc c quan d bo, nh d bo kh tng, thu
B mn K thut my tnh
15
vn, trong tnh ton qu o bay ca tn la, my bay, tu thu, v.v... hay trong cc
phng nghin cu khoa hc. Nhng my tnh loi ny thng thng thc hin nhng
chng trnh tnh ton khng l, nn chng c trang b cc CPU rt mnh v cc
thit b ngoi vi, b nh ngoi rt ln. l nhng siu my tnh (Supercomputer).
c) My tnh o lng v iu khin: S pht trin nhanh chng ca cc h thng
my tnh to ra nhng ng dng ln lao trong cc h thng o lng v iu khin
t ng. i vi cc ng dng thng thng nh trong cc dng c gia dng, t Ti vi,
iu ho nhit , my git v.v... l nhng my tnh nh c ch to di dng
mt vi mch (Single-chip Microcomputer). Tuy nhin, cng cn phi tnh n nhng
my tnh ny trong cc thit b hin i v phc tp nh trong cc h thng t ng li
my bay (Autopilot), tu thu, tn la...
d) Cn c vo tnh nng k thut v cc ch tiu v kch thc: Cc my tnh
cn c cha ra thnh my tnh ln gii cc bi ton cc ln vi tc rt nhanh,
my tnh nh s dng trong gia nh, trong trng hc hay cc tnh ton thng dng,
iu khin cc qu trnh cng ngh va v nh.
Cng cn nhc n y mt s khc bit gia hai khi nim h Vi x l v my
vi tnh: Cc my vi tnh lun lun c trang b mt phn mm c bn l H iu
hnh, v d: MS-DOS hay cc phin bn iu hnh a nhim (MS WINDOWS ca
hng phn mm Microsoft, hoc cc h iu hnh ca cc hng khc...) v cc
chng trnh hay phn mm ng dng, trong khi cc h Vi x l ch cn trang b mt
chng trnh Monitor (chng trnh gim st) n gin c ghi trong b nh ROM.
B mn K thut my tnh
16
CHNG II. CC N V VI X L TRUNG TM

(CPU - Central Processing Unit)
V hu ht cc my vi tnh ang c s dng Vit nam u c xy dng trn
c s ca cc chip x l ca hng lntelR nn ti liu ny cng gii hn s trnh by
trong khun kh cc trung tm vi x l ca hng ny. Cc c gi c th tm hiu
thm v cc trung tm vi x l ca cc hng khc nh Motorola, AMD,... mt
s ti liu tham kho lit k phn cui gio trnh.
Khi CPU c ch to t mt mch vi in t c tch hp rt cao th n c

gi l b Vi x l (P - Microprocessor). Trong qu trnh pht trin, hng lntel cho
ra i nhiu th h P t n gin n phc tp, t thng dng n chuyn dng. Tnh
pht huy v k tha lun c coi trng trong qu trnh ny, v vy, cc chng trnh
ng dng chun phn ln c th thc hin c trn bt k my vi tnh c xy dng
t th h P no.
II.1. Trung tm Vi x l, P8085
Hnh II.1a) l s khi cu trc ca P8085
B mn K thut my tnh
17
Hnh II.1a) l s ni chn ca P8085. Khc vi cc loi P xut hin trc

nh P8008 hay P8080, P8085 c nhng bc pht trin c tnh t ph nh sau:
Hnh II.1b) S ni chn ca P8085

1. C cu ngt theo nhiu mc khc nhau c hnh thnh qua mt khi iu khin
ngt, to ra mt vector ngt trnh c s chn nhau do lnh RET N trn BUS d liu.
Tn hiu nhn bit yu cu ngt INTA c to bi khi iu khin ngt, ch khng
phi t mch ph 8228 nh P8080.
2. Cc tn hiu iu khin ghi/c WR v RD c to ra t i nh thi v iu
khin chc nng. Cc tn hiu INTA , WR v RD c to ngay trong CPU, ch
khng do mch ph tr bn ngoi.
3. P8085 c mch to xung ng h c tch hp ngay trong CPU.
4. Khi chc nng iu khin vo/ra ni tip c tch hp cng cho php P8085
thc hin cc lnh vo/ra d liu ni tip m nhiu khi khng cn n s h tr ca vi
mch chuyn dng.
5. c bit hn, P8085 c hai thanh ghi m a ch, l thanh ghi m Ai5 A8 V thanh ghi m AD7-AD0 cho c d liu v a ch. Vic dn knh nh trn to
iu kin cho nhng chn chc nng khc c to thm, lm tng thm sc mnh cho
CPU.
II.1.1. Cc nhm tn hiu trong P8085
A8 A15. Nhm tn hiu ra: 8 bit cao ca a ch, cc chn ny l cc chn c
ni vi bn ngoi qua mch 3 trng thi. Cc phn t 3 trng thi s c t trng
thi high-z trong cc trng hp mt trong cc tn hiu HOLD hay HALT l tch cc.
B mn K thut my tnh
18
AD0 AD7. Nhm tn hiu dn knh 3 trng thi. giai on u ca chu k my,
T1 ca M1, s l byte thp ca 16 b a ch.
ALE (Address mch Enable). Tn hiu ra qua mch 3 trng thi. c s dng
cht byte thp ca tn hiu a ch (A7 - A7) Tn hiu ny c to ra trong giai on
u tin ca chu k my, T1 ca M1, v cng c dng cht cc tn hiu trng thi
S0 v S1 khi cn thit.
S0 v S1 (Data BUS Status). L cc tn hiu ch trng thi ca cc chn thuc BUS
d liu trong mi chu k my. T hp ca hai tn hiu ny cng cho bit trng thi ca
CPU
S0
S1
Hot ng ca BUS d liu
Trng thi HALT
CPU ang thc hin thao tc WRITE
CPU ang thc hin thao tc READ
CPU ang thc hin thao tc nhn lnh Instruction fetch
RD (Read). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu
tch cc khi CPU tin hnh c d liu t b nh hoc t thit b ngoi vi. Trong ch
HALT hoc DMA, chn ra ny trng thi high-z.
WR (Write). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu
tch cc khi CPU tin hnh ghi d liu vo b nh hoc a d liu ra thit b ngoi vi.
Trong cc ch HALT hoc DMA, chn ra ny trng thi high-z.
IO/ M . Trng thi logic ca u ra ny cho bit CPU ang lm vic vi thit b
ngoi vi hay vi b nh. Nu l logic "l", CPU ang truy cp thit b vo/ra, cn nu l
"0", CPU ang truy cp b nh. Kt h vi hai u ra RD v WR to ra cc tn
hiu I/OR , I/OW , RD , MEMR v MEMW trong trng hp s dng a ch tch bit
i vi thit b vo/ra. Nm trong nhm tn hiu iu khin, nn IO/ M cng l u ra
3 trng thi.
Interrupts. P8085 c ngt a mc. C 5 chn ngt tt c: (INTR, RST5.5.
RST6.5, RST7.5 v TRAP). Ngoi chn ngt khng che c l TRAP, cc chn khc
u c th che hoc khng che nh lp trnh phn mm.
- INTR: Chn nhn yu cu ngt t bn ngoi, c p ng theo nguyn tc
polling hoc vectoring thng qua lnh RST
- Cc yu cu ngt RST. C 3 u vo yu cu ngt vi cc mc u tin khc
nhau l RST7.5, RST6.5 v RST5.5. Khi yu cu ngt xut hin ti cc chn
ny, CPU t ng chuyn n cc vector ngt tng ng. C th nh sau:
RST5.5 l mc u tin thp nht, phn ng theo mc in p trn chn
B mn K thut my tnh
19
yu cu ngt, a ch vector ngt ny nm nh c a ch 2CH.
RST6.5 Ngt u tin thp th 2, phn ng theo mc in p trn chn

yu cu ngt, a ch vector ngt ny nm nh 34H.
RST7.5 Mc u tin cao nht. Phn ng theo sn ln ca xung yu cu

ngt. Sn ln ca xung ny tc ng ln mt flip-flop, mch ny gi li
yu cu ngt cho n khi c xo nh tn hiu nhn bit yu cu ngt
Acknowledge. a ch ca vector ngt ny nm nh 3CH.
- TRAP: L chn nhn yu cu ngt khng che c (d nhin l n c mc

u tin cao nht). a ch ca vector ngt ny nh 24H.
INTA . Tn hiu ra nhn bit yu cu ngt ti chn INTR. Cc yu cu ngt
RST5.5, RST6.5, RST7.5 v TRAP khng tc ng n INTA .

HOLD. trng thi logic "1" chn ny l yu cu ca thao tc DMA.
Cc u ra RD, WR, IO/M v ALE s c a v trng thi high-z.
HLDA. Tn hiu nhn bit yu cu HOLD.
RESET IN . Logic thp "0" u vo ca chn ny yu cu ti khi ng h Vi x
l. Do tc ng ca tn hiu RESET IN tch cc, gi tr ca thanh m chng trnh

PC s c np li l 0000H cc mt n ngt v tn hiu HLDA cng c ti thit lp
v gi tr mc nh.
RESET OUT. u ra nhn bit h Vi x l c ti khi ng. Dng tn hiu ny
ti khi ng ton b h thng.
READY. Logic "1" u vo ny thng bo trng thi sn sng cung cp d liu
cho CPU hoc nhn d liu t CPU ca cc thit b ngoi vi. SID (Serial Input Data).
L cng vo ca d liu ni tip ca h Vi x l Bit hin din ti cng ny c c
vo CPU nh lnh RIM, bit s c a vo bit cao ca Acc (MSB).
SOD (Serial Output Data). Bit cao (MSB) ca Acc c truyn ra ngoi chn
ny khi s dng lnh SIM.
X1, X2. Li ni thch anh hoc mt mch dao ng to xung nhp cho CPU. C
th s dng thch anh c tn s dao ng trong khong t 0.5 n 3MHz.
CLK. u ra ca xung nhp, c th lm xung nhp cho cc thnh phn chc nng
khc trong h Vi x l.
Vcc, Vss. Li ni ngun +5V v GND cho P8085. Cng cn nhc li rng,
P8085. ch cn mt ngun nui duy nht l +5V, kh nng cung cp dng ca ngun
cn c thit k tu theo nhu cu ca ton h Vi x l.
II.1.2. Khi nim v bn cht vt l ca cc BUS trong h Vi x l
Hot ng ca mt h Vi x l thc cht l vic trao i v x l cc gi tr nh
B mn K thut my tnh
20
phn gia cc thnh phn, cc khi v cc mch vi in t trong ton b h thng. Nh

bit, cc gi tr nh phn (hoc "0" hoc "1") c th hin qua mc in p so vi
mt chun nht nh. Gi tr "0" tng ng vi mc in p thp (t 0V n +0,8V) v
gi tr "1" tng ng vi mc in p t khong +3V n +5V. biu din mt s
liu nh phn, cc phn t mang thng tin c lin kt k nhau theo nhm (v d
1byte l 8 bits). m nhn cng vic di chuyn cc d liu ny trong ton b h
thng, c cc ng dy truyn dn in chuyn dng c ghp song song thnh h
thng, mi dy truyn dn dnh ring cho 1 bit. Tp cc ng truyn dn dnh ring
cho cc tn hiu c cng chc danh (d liu, a ch, iu khin) c gi l BUS. Nh
vy, trong mt h Vi x l, c ba loi BUS: BUS d liu, BUS a ch v BUS iu
khin. Cc BUS ny hp li thnh BUS h thng.
T khi nim trn, d dng suy ra bn cht vt l ca cc BUS trong mt h Vi x
l: l cc dng truyn dn in, c th di cc dng cp nhiu si, ng dn
trong cc bng mch in v. v... Kh nng v cht lng dn in ca cc ng truyn
dn ny ng vai tr quan trng v quyt nh i vi hot ng ca mt h Vi x l.
ng truyn dn km, tr khng cao c th gy ra s suy gim ca tn hiu in dn
n cc hin tng mt mt hoc sai d liu, rt nguy him.
BUS l ng dn in ni b m theo cc tn hiu c truyn t b
phn ny n cc b phn khc trong h Vi x l. C 3 loi BUS trong mt
h Vi x l cng nhu trong my tnh.
BUS d liu truyn d liu theo hai chiu gia b nh v trung
tm Vi x l, gia cc thit b ngoi vi v Trung tm Vi x l
BUS a ch xc nh cc v tr nh trong b nh, cc thit b
ngoi vi
BUS diu khin truyn cc tn hiu iu khin n cc b phn
cn c iu khin
Cc BUS c xy dng bng cch s dng cc khe cng theo mt quy c
cht ch i vi tng tip im. i vi cc khe cm, cc tip im tng
ng s c ni vi nhau bng cc dy dn hoc ng dn song song trn
mch in. Nh vy khi d liu c truyn i, tt c cc bit (8,16, 32, hay 64)
u c truyn i ng thi, cng mt hng (truyn dn song song).
Cng cn ni thm rng, trong my PC, c 3 loi cu trc BUS thng gp l
ISA (lndustrial Standard Architecture) EISA (Enhanced ISA) v PCI
(Peripheral Component lnterconnect).
II.1.3. Cc mch 3 trng thi, mch cht v mch khuych i BUS 2 chiu
Trc tin, cng cn nhc li mt s linh kin in t s c bn s dng trong my
vi tnh. Nh cng ngh cao, cc linh kin c tch hp ln v rt ln ra i, nhng
B mn K thut my tnh
21
khng th khng nhn li mt s mch t hp thc hin nhng hm logic c bn nht.

a) Cc cng logic
K hiu cc mch c ch ra trn Hnh II.2, cng biu thc hm logic gm: mch
m (bufer), mch o (NOT), mch v (AND), mch NAND, mch hoc (OR), mch
NOR v mch XO
Hnh II. 2 ct s cng Logic thng dng

Cc loi mch ny thng c s dng to nn cc mch t hp logic thc
hin cc chc nng lp m, gii m, dn knh v phn knh. Cng cn lu rng mt
s mch chc nng nh gii m dn knh v phn knh c cc hng tch hp
di dng cc mch MSI. Mt s mch c th k ra nh mch gii m 3/8 SN74138,
mch dn knh 74151, mch cng, v mch nhn v.v...
b)Mch 3 trng thi (Tristate Component)
Trong h Vi x l, c nhiu khi chc nng cn thng tin, nhng ti mt thi
im, bao gi cng ch c mt khi a tn hiu ra (d liu) v mt s hn ch cc khi
thu nhn tn hiu. Thay v ni dy dn lin kt cc khi qua tng i phn t mt, cc
tn hiu ny c a ln BUS. Vi cc cng logic thng thng, khng th ni trc
tip chng ln cng mt ng dy v s xy ra tranh chp BUS v on mch. V d
u ra ca phn t A l "1" trong lc u ra ca phn t B l "0". (Hnh II.3). Cc u
ra ca loi mch ny u theo cu trc pull-up, ngha l c hai transistor c ni ni
tip vi nhau (xem hnh v), emitter ca transistor ny qua mt diode ri n u ra,
n collector ca transistor kia. Vi hai trng thi logic "1" v "0", tng ng s l T1
m, T2 ng v ngc li, T2 m v T1 ng. Trn hnh v II.2 hin tng nguy him
xy ra khi li ra ca phn t logic A l "1", cc kho m hay ng tng ng vic
transistor thng bo ho hay ngt, li ra chua phn t logic B l "0" v hin tng
on mch xy ra.
trnh hin tng ny, mt loi cng logic gi l cng 3 trng thi (tri-state gate)
c s dng cho li ra ca cc khi ni chung vo BUS. Hnh II.3a l mt phn t
B mn K thut my tnh
22
o u ra 3 trng thi. Hnh II.3b l s tng ng ca trng thi high-z, tng

ng vi trng hp u ra b tch khi BUS.
u ra Pull-up
phn t logic
Hnh II. 3a Hin tng on mch xy ra khi ni hai u

ra ca hai phn t trn cng mt ng dy ca BUS
Nh vy, trnh xung t trn BUS, cc phn t c u ra ni vi BUS cn phi

a qua cng 3 trng thi.
Hnh II. 3b phn t o 3 trng thi v s

tng ng u ra ca phn t trng thi high-z
c) Mch cht, thanh ghi:
Mch cht l mt mch gm cc phn t c kh nng lu gi cc gi tr "0" hoc
"1" li ra. C th dng D flip-flop lm mt mch cht vi tn hiu cht d liu ti
u ra Q theo bng gi tr chn l sau:
Hnh II.4. Mch cht (hay phn t nh) D lip-Flop

Bit rng Qn+l = D vi tn hiu iu khin l s xut hin sn dng ca xung
nhp CK. Nh vy, gi tr logic (0 hoc 1) ti D c chuyn sang u ra Q (cht).
Nu CK gi nguyn trng thi bng "1", th trng thi u ra Q c gi nguyn. Nh
vy, gi tr logic ca D c lu gi Q (nh).
B mn K thut my tnh
23
Hnh II.5. Thanh ghi 4bits

Thanh ghi (Register) flip-flop c ni song song vi nhau, c th lu gi c cc s
liu nh phn. Hnh II.5 l s mt thanh ghi lu gi s liu nh phn 4 bits c to
t 4 phn t D flip-flop.
Mt s liu nh phn bt k t D3 n D0 s c cht sang cc li ra t Q3 n Q0
mi khi c mt sn ln ca Xung nhp CK c a ti li vo xung nhp. T nh
phn ny c lu gi li ra cho n khi c d liu mi c a vo li D v c
xut hin sn ln ca xung nhp CK.
d) Mch khuych i BUS 2 chiu
Trn c s ca cc mch 3 trng thi, cc mch khuych i BUS hai chiu c
xy dng theo nguyn l sau:
Hai phn t 3 trng thi s c ghp ngc vi nhau (Hnh II.6) chn iu khin
s dng tn hiu o ca tn hiu c RD. Khi xut hin tn hiu RD, d liu c
php i t QD sang D0 ngc li, tn hiu ch c php i t D0 sang Q0 v cho php
CPU a tn hiu ghi d liu ra ngoi.
Ghp ni s phn t cho tt c cc dy d liu, ta c mch khuych i BUS hai
chiu. Trong thc t, mch c chc nng trn c tch hp theo chun ca TTL,
c k hiu l 8228 hoc 8288 (Octal BUS Transceiver).
Hnh II.6 Phn t khuych i BUS hai chiu

II.1.4 Biu Timing thc hin lnh ca CPU P8085
Vic thc hin mt lnh trong P8085 thc t l mt chui cc thao tc READ v
WRITE. Mi thao tc READ hay WRITE tng ng vi mt chu k my M). Mi
lnh c thc hin qua 1 n 5 chu k my. Mi chu k my cn t 3 n 5 nhp
ng h (hay cn gi l trng thi T)
B mn K thut my tnh
24
chu k my th nht, CPU thc hin vic nhn m lnh (Instruction Code
Fetch), Cn gi l chu k Opcode Fetch. Theo biu thi gian trn hnh II.8, thy
rng vic thc hin chu k my M (chu k nhn lnh Opcode Fetch), CPU gi ra cc
tn hiu IO/M, S1 v S0 (tng ng 0, 1, 1 trn biu thi gian) xc nh thao tc ca
chu k.
Hnh II. 7 nh thi c s ca P8085 (Theo ti liu ca hng intel)

CPU cng ng thi gi 16 bit a ch ra chu k my u tin, ngay t nhp u
tin (T1) xc nh nh hay thit b I/O. Ni dung PCL ch tn ti trong thi gian 1
nhp nn cn phi c cht li nh tn hiu ALE mc cao.
Khi D7 D0 - nh trn cc dy d liu, CPU gi tn hiu RD . Khi nhn
c d liu, RD chuyn ln mc cao cm v tr nh hay thit b o
S lng chu k my v trng thi cn cho thc hin mt lnh l c nh, song s
lng ny khc nhau i vi cc lnh khc nhau, tu theo di ca t lnh (l byte, 2
bytes, 3 bytes). S lng chu k my ph thuc vo s ln CPU phi lin lc vi cc
phn t khc trong h thng, ch yu l vi cc chip khc.
B mn K thut my tnh
25
Hnh II. 8 Biu thi gian ca cc tn hiu trong chu k

my nhn lnh (Opcode Fetch)
II.1.5. Khi nim chu k BUS
Khong thi gian (tnh theo s lng chu k xung nhp) CPU (hoc n v lm
ch BUS) thc hin hon thin mt thao tc di chuyn d liu t CPU n b nh, n
thit b ngoi vi hoc theo chiu ngc li c gi l chu k BUS.
Mt chu k BUS c CPU hoc n v lm ch BUS thc hin trong hai giai
on:
Giai on mt: CPU gi a ch v tr cn truy xut ( nh hoc thit b ngoi vi)
ln BUS a ch, khong thi gian ny c gi l thi gian a ch (address time). a
ch ch (destination - a ch ca mt nh hay a ch thanh ghi d liu ca thit b
ngoi vi cn truy xut) c CPU (hoc n v lm ch BUS) gi ln BUS a ch
cng cc tn hiu xc nh loi chu k BUS
- Giai on hai: CPU kim tra tn hiu sn sng (READY) ca n v cn truy xut
(b nh hoc thit b ngoi vi) thc hin vic di chuyn v cht d liu. Khong
thi gian ny c gi l thi gian d liu.
Tn ti 4 loi chu k BUS c bn:
a. Chu k BUS c d liu t b nh (Memory Read)
b. Chu k BUS ghi d liu vo b nh (Memory Write)
c. Chu k BUS c d liu t thit b ngoi vi (I/O Read)
d. Chu k BUS ghi liu vo thit b ngoi vi (I/O Write)
B mn K thut my tnh
26
Hnh II.9 Biu thi gian ca cc tn hiu trong chu k

BUS c d liu t nh (Memory Read)
Ngoi ra, do s khc nhau v vn tc, kh nng x l v chun b, hon thin d
liu, tn hiu READY cha mc tch cc, cc thao tc di chuyn d liu ca CPU
phi to thm cc trng thi i (Wait State), do vy cc loi chu k BUS c di
khc nhau.
II.1.6 Ngt (lnterrupt)
Trong thc t, tc x l d liu ca CPU cao hn rt nhiu so vi s ch bin
d liu ca cc thit b I/O. V vy cn to ra mt c ch vo/ra hp l tng hiu
sut lm vic ca CPU. Ngt trong h thng Vi x l nhm mc ch gii quyt s bt
hp l do CPU phi ch i thit b ngoi vi. Thit b ngoi vi ch yu cu CPU phc
v vic nhn hay chuyn giao d liu khi bn thn n sn sng. thc hin tt
yu cu ny, c ch phc v ngt l hp l nht.
Ngt ngha l yu cu CPU tm thi dng cng vic hin ti trao i hay x l
d liu khng thuc tun t ca chng trnh ang c thc hin. Ngt l mt hin
tng xut hin ngu nhin v phng din thi im nhng c d on trc.
Ngt l hin tng mt tn hiu xut hin bo vi CPU rng c mt s
kin xy ra yu cu CPU phi x l. Qu trnh x l ca CPU s b
tm thi dng li thc hin mt thao tc khc phc v s kin c yu
cu. Khi thao tc ny kt thc, qu trnh x l va b tm dng s c
tip tc. Bn thn s kin thng thng l yu cu phc v ca thit b
ngoi vi i vi CPU.
Trong thc t, ngt c s dng ch yu khi cc thit b ngoi vi (thng rt
chm so vi tc x l ca CPU) cn trao i thng tin vi CPU.
Khi cn trao i thng tin, thit b ngoi vi gi tn hiu yu cu ngt (Interrupt
Request) ti CPU. CPU s thc hin nt lnh hin ti v tr li bng tn hiu nhn bit
B mn K thut my tnh
27
yu cu ngt ( INTA ). Chng trnh

chnh lc ny b tm dng (ngt) v
CPU chuyn sang thc hin chng
trnh con phc v ngt, tc l chng
trnh con trao i thng tin vi thit b
ngoi vi yu cu ngt. Sau khi xong
cng vic phc v ngt, CPU quay v
thc hin tip chng trnh chnh k
t lnh tip theo sau khi b ngt cc
tn hiu yu cu phc v ngt t mt
thit b ngoi vi bt k c gi ti
chp nhn yu cu ngt ca CPU c
th thng qua mt khi iu khin
ngt, tu theo ngi lp trnh m yu
cu ngt c c chuyn ti CPU hay khng. Trong trng hp yu cu ngt c
gi ti CPU, x l ca CPU gm cc bc sau:
1. Thc hin nt lnh ang c x l
2. Pht tn hiu nhn bit yu cu ngt gi cho thit b yu cu phc v ngt qua
chn INTA
3. Ct cc c trng thi hin ti vo ngn xp
4. Xo cc c IF (Interrupt Flag) v c TF (Trap Flag)
5. Ct a ch lnh tip theo trong tun t chng trnh ang thc hin vo ngn
xp
6. Ly a ch ca chng trnh con phc v ngt trong bng vector ngt
7. Thc hin chng trnh con phc v ngt.
II.1.7. Truy nhp trc tip b nh (Direct Memory Access - DMA)
Trong nhiu trng hp, xy ra hin tng phi chuyn mt khi d liu t thit b
ngoi vi vo mt vng nh hoc ngc li. Vi phng php vo/ra bng chng
trnh, d liu no cng phi i qua CPU, do vy lm chm tc trao i d liu.
khc phc tnh trng ny ta dng phng php trao i d liu gia mt vng nh vi
thit b ngoi vi mt cch trc tip khng thng qua CPU, l phng php truy
nhp trc tip b nh (DMA). Trong phng php ny, CPU giao quyn iu khin
BUS d liu cho mt chip in t chuyn dng gi l chip DMAC (DMA Controller).
Chip DMAC t to ra a ch, to cc tn hiu iu khin vic ghi c b nh, m s
t d liu c ghi vo hoc c t b nh v s thng bo cho CPU khi thc
hin xong vic trao i d liu vi b nh. Qu trnh c thc hin hon ton bng
phn cng, trc tip gia thit b vo/ra v b nh nn tc trao i thng tin tng
B mn K thut my tnh
28
i nhanh. CPU khng cn nhn lnh, gii m lnh v thc hin cc lnh di chuyn d
liu.
Hnh II. 10 M t cc tn hiu iu khin trong qu trnh DMA

Khi c yu cu trao i d liu theo DMA, thit b ngoi vi gi tn hiu yu cu
DRQ ti chip DMAC, chip ny gi tn hiu yu cu treo HRQ ti chn HOLD ca
CPU. Nu yu cu c chp nhn, CPU s gi xung ghi nhn HLDA ti chn HACK
ca chip DMAC v t treo cc BUS, cho php DMAC s dng BUS. DMAC gi tn
hiu DACK ti thit b ngoi vi cho php thit b ny thc hin vic trao i d liu.
Kt thc qu trnh trao i d liu chip DMAC chuyn trng thi ca tn hiu HRQ v
mc thp thng bo cho CPU.
II.1.8 Vi chng trnh (Microprogram) v tp lnh ca P8085
a) n v iu khin CU - Conlrol Unit
CU - Control Unit l n v iu khin, iu phi mi hot ng ca cc b phn
chc nng trong CPU thng qua Control BUS. C th coi CU l khi dch lnh ca
CPU, n to ra cc tn hiu tng ng lm u vo cho Controller Unit iu khin
hot ng ca cc khi chc nng. Cc tn hiu do CU to ra c th phn thnh 2 loi:
Tn hiu nh thi v tn hiu iu hnh hot ng ca CPU. Cc tn hiu nh thi do
CU to ra xc nh trng thi ca CPU lm vic:
- ang ch c d liu vo (Input mode)
- ang a d liu ra (Output mode)
- ang bt u mt hot tc khc (Beginning another operation).
Cc tn hiu trng thi ca CPU xc nh CPU ang:
- c d liu t b nh (Memory Read)
- Ghi d liu vo b nh (Memory Write)
- Nhn lnh (Instruction Fetch)
B mn K thut my tnh
29
- c d liu t thit b ngoi vi (I/O Read)

- a d liu ra thit b ngoi vi (I/O Write)
Cng c th c nhng thao tc khng c nu y, nhng ch cc thao tc trn
l quan trng nht.
Cn hiu rng mch Controller Logic to cc tn hiu iu khin da vo cc tn

hiu trng thi ca CPU v tn hiu nh thi, c ngha l to tn hiu g v vo thi
im no.
hiu c kin trc khi CU, hy tm li gii p cho cu hi: Sau khi nhn
lnh, CPU lm sao bit" phi thc hin nhng thao tc no thc hin lnh?
Tt c cc lnh u c biu din di dng m nh phn. Gi s lnh c biu
din bng mt m 8 bits 01000111B (chuyn ni dung thanh ghi B sang thanh ghi A,
k hiu l [A] <= [B]).
Trc ht, lnh phi c gii m. Mt mch AND c th s dng to ra tn
hiu nhn bit lnh (Hnh II.11). u vo ca mch AND ny c ni vi u ra ca
thanh ghi lnh. u ra ca cc phn t trong thanh ghi lnh xc nhn s hin din ca
lnh MOVE B To A heo cng thc
(MOVE B TO A) = IR 7.IR6. IR 5. IR 4. IR 3.IR2.IR1.IR0.
Trong IRn l u ra ca cc flip-flop tng ng vi cc gi tr nh phn ca m
lnh MOVE B To A. Mch AND nhn bit m lnh c gi l mch gii m lnh.
Nh vy, nu CPU s dng 8 bit m ho cc lnh, c th c 256 lnh, v mch gii
m lnh cng s, cn n 256 mch AND tng t, tuy nhin u vo ca mi mch l
mt t hp duy nht trong 256 t hp c th.
B mn K thut my tnh
30
Hnh II.12 Nhn bit cc lnh t t hp m nh phn

D thc hin lnh, khi iu khin CU xc tin mi thao tc ngay bn trong CPU
bng cch to ra cc tn hiu iu khin v cc xung nhp nh thi cho cc khi
chc nng thc hin cc thao tc.
Sau khi nhn tn hiu t khi gii m lnh (Instruction Decoder), CU s to ra cc
tn hiu iu khin v cc xung nhp. Tn hiu iu khin s cho php (Enable) khi
chn thanh ghi (Reg Select) chn thanh ghi B v thit lp h thng ng truyn thng
sut gia hai thanh ghi B v A. tip theo CU s to cc tn hiu tng ng vic
truyn d liu gia hai thanh ghi c thc hin.
Tip theo, CU iu khin thanh m chng trnh PC tng ln 1 nhn tip lnh
t b nh. V CU c nhim v gim st v iu khin mi thao tc ca cc thnh phn
chc nng trong CPU, nn cc dy iu khin phi c ni trc tip t CU ti mi
khi chc nng trong CPU nh trn hnh.
II.l3a. Cng cn nhn thc rng, lnh c CPU ly t b nh. Trong thc t, d
liu x l cng c th xut pht t b nh, v cc thanh ghi cng c th c chn
bt k ngoi tr thanh ghi lnh IR v thanh m chng trnh PC.
Nh vy, li cn thm mt thanh ghi lin lc vi BUS d liu c nhim v truy

nhp c vo b nh. Thanh ghi ny lm trung gian gia BUS d liu bn ngoi v
B mn K thut my tnh
31
cc thanh ghi a nng khc, v n c lin lc vi nhau thng qua BUS d liu ni
b (Internal Data BUS) - mt BUS m cc thanh ghi c truy xut trc tip. CU phi
lm nhim v xc nh thanh ghi no c truy xut qua BUS d liu ni b ti thi
im . Cng v BUS d liu ni b ca CPU truy xut n BUS d liu.h thng,
nn cn phi c mt cch thc hoc cch ly chng khi cn thit, hoc cho php
ghp ni, nn cn thit phi c thm thanh ghi m d liu hai chiu. V nh vy, CU
phi lm nhim v iu khin hng di chuyn ca d liu khi i qua thanh ghi m
(xem hnh II.13b).
b) Vi chng trnh
Gi thit rng li ra ca khi gii m lnh v to cc tn hiu iu khin phi to ra
12 tn hiu ti cc ca G1 G12, 2 tn hiu iu khin b nh v 5 tn hiu xung nhp
kch hot cc thanh ghi PC (thanh m chng trnh), MAR (thanh ghi m a ch,
MSR (thanh ghi m b nh), Do (thanh ghi d liu) v IR (thanh ghi lnh) iu
khin qu trnh nhn v thc hin lnh ADD. Cc tn hiu ny c gi ti iu
khin hot ng ca cc thnh phn khc nhau trong CPU. Mt chu trnh thc hin
lnh trn s c thi hnh.
Thc t trong CPU ca my tnh c t 64 n hn 200 cc tn hiu iu khin nh
th. S khc nhau quan trng gia cc lnh v vi lnh l ch vi lnh c nhiu trng
hn. Tm bc trong bng trn l mt vi chng trnh dch mt giai on nhn lnh
(OPCODE FETCH) c thc thi sau lnh cng ADD. Nh vy mt lnh c dch
thnh mt chui cc vi lnh, hay ni cch khc, mi m lnh c mt vi chng trnh.
B mn K thut my tnh
32
C th thy rng, khi gii m lnh v to cc tn hiu iu khin:

+ "Bit" phi thc hin lnh "nh th no", mt khi lnh t IR (Instruction
Register) c chuyn ti.
+ Gii quyt vic thc hin mt lnh bng cch iu khin cc khi chc nng lin
quan thc hin cc phn vic.
T cch nhn nhn trn, d dng nhn ra rng khi gii m lnh v to cc tn hiu
iu khin l b no thc th ca CPU. C th coi khi ny l mt my tnh c dng
(Special-purpose Computer)(*) bn trong CPU. N l ht nhn c bn nht dnh ring
cho vic thc hin mt lnh. thit k v xy dng c khi ny, cn phi c mt
"chng trnh" (program)(*) tht chi tit Chng trnh dng xy dng nn khi ny
cn phi c nhng th tc tuyt i chnh xc nhm mc ch thc hin cc lnh.
Chng trnh c gi l Vi chng trnh (Microprogram) v c ch to nh
l mt phn tch hp cng bn trong CPU, ngi lp trnh khng th thay th cng nh
khng th truy nhp vo c.
B mn K thut my tnh
33
i vi cc loi p dng bit-slice microprocessor, Vi chng trnh hon ton

do ngi s dng xy dng.
b) Tp lnh ca P8085
Tp lnh ca P8085 c th chia thnh nhiu nhm lnh nh tu theo tng cch
tip cn. Theo phng thc x l v kt qu ca vic x l d liu, cc lnh trong tp
lnh c chia thnh 4 nhm chnh:
1. Nhm lnh chuyn d liu: cc lnh trong nhm ny thc hin vic di chuyn
d liu gia cc thanh ghi vi nhau, gia thanh ghi vi b nh v ngc li, cc
lnh vo/ra d liu v.v...
2. Nhm lnh s hc v logic: cc lnh trong nhm ny thc hin cc php tnh s
hc c bn l cng v tr 2 ton hng, cc lnh tng gim, hay so snh ni dung
thanh ghi, cc php tnh logic trong s sc nh phn, cc php dch tri, phi d
liu trong thanh ghi, lnh quay vng tri phi v.v...
3. Nhm lnh iu khin: Bao gm cc nhm lnh r nhnh c iu kin v khng
iu kin, cc lnh gi chng trnh con
4. Nhm lnh c bit: Nhm lnh c bit bao gm cc lnh ly b 1 ca s liu
trong ni dung thanh ghi, lnh thit lp v xo cc c, lnh hiu chnh thp phn
mt s liu Hexa v lnh vo/ra d liu ni tip.
II.1.9. Vi nt v lp trnh cho 8085
Pht trin phn mm (lp trnh) v cc k thut lin quan ng vai tr quan trng
bc nht trong cc ng dng t n gin n phc tp ca cc h Vi x l v my vi
tnh. i vi cc h Vi x l, mi ng dng u c pht trin nh vo mt "cng c'
pht trin phn mm hon chnh: Lp trnh hp ng.
Qu trnh pht trin mt chng trnh (phn mm ng dng) cho mt h Vi x l,
k t khi xc nh nhim v cn thc hin cho n khi chng trnh c ci t hon
chnh vo h thng c th chia ra nm bc c bn sau y:
a) t vn (xc nhn vn ): Trc khi gii quyt vn , ngi lp trnh cn
xc nh xem, liu vn c th c gii quyt nh mt chng trnh trong mt h
Vi x l hay khng. Phi thy rng khng phi h Vi x l vn nng" n mc c (h
gii quyt tt c mi vn ny sinh trong thc tin, thm ch i khi cn lm cho s
vic cng thm phc tp.
b) Xc nh phng php gii quyt vn : y chnh l bc tm thut gii
(Algorithm) ti u cho vn c t ra. Ngi lp trnh phi tm v la chn c
t nhiu gii php mt gii php tt nht, nhng kinh t nht thc hin. Khng ch
tm gii thut tt nht m cn phi tm ngn ng lp trnh ph hp nht gii quyt
vn .
B mn K thut my tnh
34
c) Thc hin gii php: Phng php gii quyt vn thng c xc nhn qua
tng bc theo mt lu . Lu l cch th hin tng minh cc bc thc hin
chng trnh trong h thng, ng thi n gip ngi lp trnh nh hng tt khi vit
chng trnh.
d) Vit chng trnh: Bn thn lu cho thy r gii php gii quyt vn
theo quan im lp trnh. Vic chuyn t lu sang ngn ng chng trnh l bc
d dng hn rt nhiu so vi cch vit chng trnh khng c lu . y ch l bc
c th ha lu nh tun t thc hin cc lnh, v l bc thc t ha gii php thc
hin vn .
e) Kim tra v g ri: Sau khi ci t vic kim tra tnh chnh xc l v cng quan
trng. Nhng sai st phi c pht hin v hiu chnh, i khi l t chnh thut gii.
Vic g ri chng trnh tc l thc hin tng bc chng trnh, pht hin cc sai st
n, hiu chnh cc sai st ny.
thc hin c tt cc cc bc trn ngi lp trnh phi c k thut lp trnh
hon thin thit k chng trnh, phi c cc cng c lp trnh tt.
II.1.10. H hiu hnh ca P8085
Cc lnh ca P8085 c thng k trong bng II.1
Mnemonic
Instruction Code
D7 D6 D5 D4 D3 D2 D1 D0
MOVE, LOAD, AND STORE

MOV r1, r2
0 1 D D
MOV M, r
0 1 1 1
MOV r, M
0 1 D D
MVI r
0 0 D D
MVI M
0 0 1 1
LXI B
0 0 0 0
LXI D
0 0 0 1
LXI H
0 0 1 0
STAX B
0 0 0 1
STAX B
0 0 0 0
LDAX B
0 0 0 1
LDAX D
0 0 0 1
STA
0 0 1 1
LDA
0 0 1 1
SHLD
0 0 1 0
LHLD
0 0 1 0
XCHG
1 1 1 0
B mn K thut my tnh
D
0
D
D
0
0
0
0
0
1
0
1
0
1
0
1
1
S
S
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
S
S
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
S
S
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
M t nhim v
Move Register To Register

Move Register To Memory
Move Register To Register
Move Immediate Register
Move Immediate Memory
Load Immediate Register Pair B
Load Immediate Register Pair D
Load Immediate Register Pair H
Store A indirect
Store A indirect
Load A indirect
Load A indirect
Store A direct
Load A direct
Store H & L direct
Load H & L direct
Exchange D & E. H & L Register
35
STACK OPS
PUSH B
PUSH D
PUSH H
PUSH PSW
POP B
POP D
POP H
POP PSW
XTHL
SPHL
LXI SP
INX SP
DCX SP
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
CALL
CALL
CC
CNC
CZ
CNZ
CP
Cm
CPE
CPO
RETURN
RET
RC
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Push Register Pair B & C on

Push Register Pair D & E on
Push Register Pair H & L on
Push A ang Flags on stack
Pop Register Pair B & C off stack
Pop Register Pair D & E off stack
Pop Register Pair H & L off stack
Pop A ang Flags off stack
Exchange Register pair H & L, too
H & L to stack pointer
Load immediate stack pointer
increment stack pointer
Decrement stack pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
Jump uncoditional
Jump on carrv
Jump on no carrv
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
H & L to program counter
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Call uncoditional
Call on carry
Call on no carry
Call on zero
Call on no zero
Call on positive
Call on minus
Call on parity even
Call on parity odd
1 1 0
1 1 0
0
1
1
1
0 0 1 Return
0 0 0 Return on carry
B mn K thut my tnh
36
RNC
1 1 0 1 0 0
RZ
1 1 0 0 1 0
RNZ
1 1 0 0 0 0
RP
1 1 1 1 0 0
RM
1 1 1 1 1 0
RPE
1 1 1 0 1 0
RPO
1 1 1 0 0 0
RESTART
RST
1 1 A A A 1
INPUT/UOTPUT
IN
1 1 0 1 1 0
OUT
1 1 0 1 0 0
RIM
0 0 1 0 0 0
SIM
0 0 1 1 0 0
INCREMENT AND DECREMENT
INR r
0 0 D D D 1
DCR R
0 0 D D D 1
INR M
0 0 1 1 0 1
DCR M
0 0 1 1 0 1
INX B
0 0 0 0 0 0
INX D
0 0 0 1 0 0
INX H
0 0 1 0 0 0
DCX B
0 0 0 0 1 0
DCX D
0 0 0 1 1 0
DCX H
0 0 1 0 1 0
ADD
ADD r
1 0 0 0 0 S
ADC r
1 0 0 0 1 S
ADD M
1 0 0 0 0 1
ADC M
1 0 0 0 1 1
ADI
1 1 0 0 1 1
ACI
1 1 0 0 1 1
DAD B
0 0 0 0 1 0
DAD D
0 0 0 1 1 0
DAD H
0 0 1 0 1 0
DAD SP
0 0 1 1 1 0
SUBTRACT
SUB r
1 0 0 1 0 S
B mn K thut my tnh
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Return on no carry
Return on zero
Return on no zero
Return on positive
Return on minus
Return on parity even
Return on parity odd
1 1 Restart
1
1
0
0
1
1
0
0
Input
Output
Read interrupt mask
Set interrupt mask
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Increment register
Decrement register
Increment Memory
Decrement Memory
Increment B&C register
Increment D&E register
Increment H&L register
Decrement B&C register
Decrement D&E register
Decrement H&L register
S
S
1
1
1
1
0
0
0
0
S
S
0
0
0
0
1
1
1
1
Add register to A
Add register to A with carry
Add memory to A
Add memory to A with carry
Add immediate to A
Add immediate to A with carry
Add B&C to H&L
Add D&E to H&L
Add H&L to H&L
Add SP to H&L
S S Subtract register from A

37
SBB r
SUB M
SBB M
SUI
SBI
LOGICAL
ANA r
XRA r
ORA r
CMP r
ANA M
XRA M
ORA M
CMP M
ANI
XRI
ORI
CPI
ROTATE
RLC
RRC
RAL
RAR
SPECIALS
CMA
STC
CMC
DAA
CONTROL
EI
DI
NOP
HLT
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1 S S S Subtract register from A with

0 1 1 0 Subtract memory from A
1 1 1 0 Subtract memory from A with
0 1 1 0 Subtract immediate from A
1 1 1 0 Subtract immediate from A with
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
S
S
S
S
1
1
1
1
1
1
1
1
S
S
S
S
1
1
1
1
1
1
1
1
S
S
S
S
0
0
0
0
0
0
0
0
And register with A

Exclusive OR register with A
OR register with A
Compare register with A
And memory with A
Exclusive memory with A
OR memory with A
Compare memory with A
And immediate with A
Exclusive immediate with A
OR immediate with A
Compare immediate with A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Rotate A left
Rotate A right
Rotate A left through carry
Rotate A right through carry
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Complement A
Set carry
Complement carry
Decimal adjust A
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
1
1
0
0
Enable interrupt
Disable interrupt
No-operation
Halt
B mn K thut my tnh
38
II.1.1. M t chn ca P8086 v cc tn hiu
P8086 c ch to
theo cng ngh HMOS,
ng v CerDIP 40 chn. L
loi Vi x l c kh nng x
l trc tip d liu 8 hoc 16
bit. V tp 1nh, P8086
hon ton tng thch vi
tp lnh ca IAPX 86/10 v
v phn cng, hon ton
tng thch vi cc mch
ngoi vi ca cc trung tm
8080/8085 ca Intel.
Hnh II.14 S ni chn trung tm Vi x l 8086
P8086 c th hot ng mt trong hai ch :

- Ch MIN: CPU t to ra cc tn hiu iu khin hot ng ca BUS (cc chn
t 24 n 34).
- Ch MAX: CPU ch a ra cc tn hiu trng thi, cn thm mt chip iu
khin BUS (BUS controller 8288) v chip ny s thng dch cc tn hiu trng thi
thnh cc tn hiu iu khin BUS tng thch vi cu trc MULTIBUSTM, cch ny
m bo hot ng c s liu n nh hn.
Hnh II. 11 l s ni chn ca P8086
+ AD15 AD0: BUS dn knh d liu v a ch 16 bits
+ A19 - A16/S6 - S3: 4 bits a ch cao hoc 4 tn hiu trng thi hot ng hin
ti ca CPU
S4
S3
Thanh ghi c truy xut..
ES
SS
CS
DS
S5 ch trng thi c ngt

S6 lun lun bng 0
+ BHE /S7: Tn hiu ny kt hp vi chn a ch A0 cho ch th cc trng thi sau:
B mn K thut my tnh
39
BHE A0
0
Mt t c truyn qua Di5 - Do
Mt Byte trn D15 - D8 c truy xut ti mt a ch Byte l
Mt Byte trn D7 D0 c truy xut ti mt a ch Byte chn
cha xc nh
+ RD : Nu bng "l" ang c b nh (hoc thit b vo/ra)

Nu bng "0" ang ghi ra b nh (hoc thit b vo/ra)
+ READY: nu b nh (hoc thit b vo/ra) cn truy nhp hon tt vic chuyn
d liu n (hoc i) chng cn pht ra tn hiu READY mc "1" ti chn CPU, ch
khi y CPU mi c s liu vo hoc a d liu ra.
+ INTR: CPU kim tra trng thi chn ny sau khi thc hin xong mi lnh xt
xem c yu cu ngt t phn cng n hay khng, nu mc "1", CPU s chuyn
sang phc v ngt. Thao tc kim tra ny c th "chr" c nh dng mt n che ngt.
+ TEST : Li vo ny ca CPU lun lun c kim tra trong lnh WAIT. Nu
bng "0" CPU tip tc thc hin chng trnh, nu bng "1", CPU chy cc chu trnh
gi cho ti khi TEST = "0".
+ NMI: Chn ngt theo sn ln ca xung, khng che c.
+ RESET: Chn nhn tn hiu ti khi ng h thng. Nu c s thy i t "0"
ln "1" v tn ti ti thiu trong 4 nhp ng h th h thng s t khi ng li.
+ CLK: Li vo ca xung nhp ng h
+ Vcc: Ngun nui +5V
+ GND: Chn ni t (0V)
+ MN/ MX : Khi c ni vi Vcc, P8086 hot ng ch MIN, nu ni vi
GND, hot ng ch MAX
+ S2 , S1 , S0 : ch MAX, chip iu khin BUS s dng 3 tn hiu trng.thi
ny pht ra cc tn hiu iu khin truy xut b nh v thit b vo ra. T hp c
ngha nh sau:
S2
S1 S0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
yu cu ngt cng qua chn 1NTR c chp nhn

c thit b vo/ra
Ghi thit b vo/ra
CPU b treo
np m chng trnh vo hng nhn lnh
c b nh
B mn K thut my tnh
40
1
1
1
1
0
1
ghi vo b nh
trng thi th ng
+ RQ / GT 0, RQ / GT 1: Tn hiu phc v vic chuyn mch BUS cc b (Local

BUS) gia cc n v lm ch BUS (BUS master). BUS cc b l BUS gia cc n
v x l (khng phi l BUS ni vi cc thit b ngoi vi). n v lm ch BUS l
P8086 hoc mt chip iu khin no (v d DMAC) hin ang nm quyn iu
khin BUS cc b.
+ LOCK : nu bng "0" n v lm ch BUS khng nhng quyn lm ch BUS
cc b
+ QS1, QS0 ch th trng thi ca hng nhn lnh trc PQ
0
khng hot ng
byte 1 ca m ton trong PQ c x l
hng i lnh c xo
byte 2 ca m ton trong PQ c x l
II.1.2 Cu trc Trung tm Vi x l h 80x86

Cc P h 80x86 c pht trin trn c s cng ngh VLSI vi cc phn t c
bn l cc transistor trng MOS c tiu hao cng sut rt nh. S khi chc
nng ca P8086 c th hin trn hnh II. 15, gm hai thnh phn ch yu l n v
ghp ni BUS (BIU), n v thc hin lnh (EU). Tt c cc thanh ghi v ng truyn
d liu trong EU u c di 16 bits. BIU thc hin tt cc cc nhim v v BUS
cho EU: thit lp khu lin kt vi BUS d liu, BUS a ch v BUS iu khin. D
liu c trao i gia CPU vi b nh khi EU c yu cu, song khng c truyn
trc tip ti EU m thng qua mt vng nh RAM dung lng nh (6 bytes) c gi
l hng nhn lnh trc (lnstruction Stream Byte Quere PQ - Prefetch Quere) ri mi
c truyn cho h thng iu khin EU (Execution Ung Control System).
Khi EU ang thc hin mt lnh th BIU tm v ly lnh sau t sn vo PQ.
y l c ch ng ng (pipeline), mt k thut tng tc cho CPU
K thut ng ng s dng mt vng nh RAM cc
nhanh, lm tng ng k tc ca b Vi x l thng qua
vic truy tm lnh t b nh chng trnh thay cho s lin
h gia CPU vi b nh chng trnh. Ring vi b x l
Pentium, c hai ng ng, mt cho cc lnh v mt cho
cc d liu.
Bng sau cho ta vi thng s k thut c bn ca cc trung tm Vi x l h 80x86

B mn K thut my tnh
41
Loi p
8088
8086
80188
80186
80286
80386SX
80386DX
i486
i486SX
Pentium (Phin bn u)
di rng rng
thanh BUS a BUS d
ghi
ch
liu
16 bits
16 bits
16 bits
16 bits
16 bits
32 bits
32 bits
32 bits
32 bits
32 bits
20 bits
20 bits
20 bits
20 bits
24 bits
24 bits
32 bits
32 bits
32 bits
32 bits
8 bits
16 bits
8 bits
16 bits
1 e bits
16 bits
32 bits
32 bits
32 bits
64 bits
Khng
gian a
ch
Tn s
cc i
1 MByte
1 Mbyte
1 Mbyte
1 Mbyte
16Mbytes
16Mbytes
4Gbytes
4Gbytes
4Gbytes
4Gbytes
10 MHZ
10 MHZ
10 MHZ
10 MHZ
16 MHZ
20MHZ
40 MHZ
66 MHZ
25 MHZ
66 MHZ
Hnh II.15 Cu trc cc khi chc nng P8086

II.1.3 H thng thanh ghi trong cc P80x86
C th coi cc thanh ghi ca cc trung tm Vi x l nh mt b nh c t ngay
bn trong CPU, c tc truy cp cc k nhanh, c dng lu gi cc d liu v
cc kt qu tm thi ca cc qu trnh tnh ton, x l. Cc thanh ghi trong h
P80x86 c di khc nhau, 16 bits vi cc trung tm 8088/86, 80188/86 v 80286,
B mn K thut my tnh
42
32 bits vi cc trung tm 80386/486 tr i v c m t trn Hnh II. 13.

EU ca P8086 c 8 thanh ghi a nng vi tn gi l AH, AL, BH, BL, CH, CL,
DH, DL. Nhng thanh ghi ny c th s dng ring r cho vic lu gi cc d liu nh
phn 8 bits. Cng c th s dng chng thnh tng cp thanh ghi c tn gi l AX
(AH-AL), BX (BH-BL), CX (CH-CL), v DX (DH-DL) lu gi cc d liu nh
phn 16 bits.
Hnh II.16 Cc thanh ghi trong cc trung tm Vi x l h 80x86

1. Cc thanh ghi a nng:
u im ca vic s dng cc thanh ghi ny lu gi tm thi cc d liu l tc
truy cp ca CPU vi chng nhanh hn rt nhiu so vi vic s dng cc nh.
2. Cc thanh ghi on:
CPU a ra BUS a ch 20 bts qun l mt khng gian nh 1Mbyte (l.048.576
Bytes) b nh vt l Tuy nhin, cc thanh ghi trong CPU li ch c di 16 bits, do
vy, khng gian nh c chia thnh tng on (segment), mi on di 64kbytes, a
ch ca Byte u tin c ly lm a ch on. Hai on nh k cn cch nhau ti
thiu l 16 Bytes. Mi Byte nh trong on s c xc nh bi lch (offset), tc
l khong cch tnh t Byte nh n u on.
B mn K thut my tnh
43
Hnh II.17 V khi nim a ch on v a ch offsel

Nh vy, mi mt cp thng s bao gm a ch on v lch (segment offset)
s xc nh a ch logic ca mt Byte nh vt l trong b nh. Thanh ghi on
(Segment Register) cha 16 bits cao, thanh ghi lch (dng thanh ghi a nng hoc
cc thanh ghi ch s, con tr) cha 16 bit thp ca 20 bits a ch. a ch vt l ca
mt v tr nh do vy s c BIU tnh theo cng thc:
a ch vt l = (Segment) x 10H + (offset)
P8086 s dng 4 thanh ghi on ring bit l: Thanh ghi on m lnh CS (Code
Segment), thanh ghi on ngn xp SS (Stack Segment), thanh ghi on m rng ES
(Extra Segment) v thanh ghi on d liu DS (Data Segment).
- Thanh ghi on m lnh CS l thanh ghi cha a ch bt u ca on chng
trnh hin hnh trong b nh
- Thanh ghi on d liu DS l thanh ghi a cha ch bt u ca on cha s
liu hin hnh trong b nh, hay cn gi l ni cha cc bin ca chng trnh
- Thanh ghi on ngn xp SS l thanh ghi a cha ch bt u ca on ngn xp
(Stack) trong b nh ( nh do thanh ghi ny ch n cn c gi l y ngn
xp), ni lu gi a ch v d liu khi thc hin cc chng trnh con, lnh gi
chng trnh con hoc th tc
- Thanh ghi on m rng ES l thanh ghi a cha ch bt u ca on cha cc
d liu Chui, xu k t
- Ngoi ra, trong cc trung tm i386/1486 cn c hai thanh ghi on FS v GS.
Cc on trong b nh c th tch bit nhau, nhng cng c th gi chng ln
nhau, nhng bao gi cng cch nhau ti thiu 16 Bytes. lch 16Bytes ny thc cht
do 4 bit thp nht ca a ch t A3 trn A0 cha c xc nh. Khi b cng trong
n v a ch tnh a ch vt l a ra BUS a ch, n ly ni dung thanh ghi on
chn thm 4 s 0000B cho 4 bits thp nht ca 20 bits a ch ri mi cng vi 16 bits
ca phn a ch offset. iu ny l gii cng thc tng trng nu trn. Phn a
ch bt u ca on c lu gi trong thanh ghi on cng thng c gi l a
ch c s hay a ch nn.
Hnh II. 18 M t cch tnh a ch vt l ca mt v tr nh

3. Thanh ghi c FLAG:
B mn K thut my tnh
44
Ch c 9 trong s 16 bits ca thanh ghi c (trong cc b vi x l P8086 P80286) v 11 trong s 32 bits. ca thanh ghi c (trong cc b x l i386/1486) c
s dng. Mi c c th c lp (= "1") hay xo (="0) biu th trng thi kt qu
ca mt php x l,trc hoc trng thi hin ti ca CPU. Cc c IOP, N, R v V
lin quan n ch bo v trong cc b x l 80286 v i386/1486. Chn c cn li
gm 6 c ch trng thi v 3 c iu khin.
Hnh II. 19 Vi tr cc c trong thanh ghi c ca h Vi x / 80x86

Cc c trng thi gm:
- C nh CF (cany flag) c lp nu mt thao tc xy, ra hin tng carry hoc
borrow i vi ton hng ch. CF c th lp bi lnh STC v xo bi lnh CLC.
- C chn l PF (parity flag) c lp nu kt qu ca mt php x l c s bit
bng "1" l s chn.
- C mang ph AF (auxiliary flag) c dng cho x l cc m BCD v c lp
nu thao tc x l gy hin tng carry hoc borrow cho 4 bits thp ca ton
hng
- C zero ZF (zero flag) c lp nu kt qu x l s liu c kt qu bng 0
- C du SF (Sign flag) du tng ng vi MSB ca kt qu php ton, c lp
vi kt qu dng v xo vi kt qu m
- C trn OF (Overflow flag) nu kt qu php ton l qu ln cho ton hng ch.
Cc c iu khin gm:
- C hng DF (direction flag) xc nh hng ca php ton x l xu, chui l
t, nu c lp, xu, chui s c x l t a ch cao ti a ch thp v
ngc li. C c lp bi lnh STD v xo bng lnh CLD
- C ngt IF (Interupt enable flag) nu c lp, CPU s chp nhn yu cu ngt
cng v phc v ngt. Dc lp bi lnh STI v xo bng lnh CLI
- C by TF (Trao flag) Dng trong g ri chng trnh (Debuger) Khng th lp
hay xo trc tip bi lnh ca my.
4. Thanh ghi con tr lnh IP
Thanh ghi con tr lnh IP (Instruction Pointer) - thanh ghi 16 bts dng lu gi
B mn K thut my tnh
45
phn offset ca a ch lnh k tip s c thc hin trong tun t thc hin chng
trnh. Kt hp vi CS, IP ging nh thanh m chng trnh PC trong P8085, mi
ln t lnh c c ra t b nh, BIU s thay i gi tr IP tu theo di ca t lnh
(s bytes ca t lnh) sao cho n ch n t lnh k tip trong b nh chng trnh.
Cng cn ni thm rng khi gp cc lnh r nhnh hoc lnh gi chng trnh con, gi
th tc..., cc gi tr ca CS:IP s thay i t ngt khng theo quy lut trn. Cc gi
tr mi ca CS:IP do ngi lp trnh cung cp thng qua a ch ca cc nhn (Label)
trong chng trnh hoc gi tr c th.
5. Cc thanh ghi d 1iu
C 4 thanh ghi d liu:
- Thanh ghi tch lu AX (Accummulator register) thng dng lu gi cc kt
qu x l
- Thanh ghi c s BX (Base register) thng dng ch a ch c s (y) ca mt
vng nh trong b nh
- Thanh ghi m CX (Counter register) thng dng khai bo s ln mt thao
tc no phi c thc hin trong cc vng lp, php dch, php quay..., Gi
tr ca ni dung thanh ghi CX s gim i mt sau mi thao tc
- Thanh ghi s liu DX. (Data register) thng dng lu gi s liu dng lm
thng s chuyn giao cho mt chng trnh. DX l thanh ghi duy nht c dng
cha a ch ca cc thit b vo/ra
6) Cc thanh ghi con tr v ch s
C 2 thanh ghi con tr v 2 thanh ghi ch s:
- Thanh ghi con tr ngn xp SP (Stack Pointer) cha a ch nh ngn xp (vng
nh c bit, hot ng theo nguyn tc LIFO - Last In First Out - vo sau ra
trc) s dng cho vic lu gi tm thi cc d liu hay a ch khi gi chng
trnh con, khi phc v ngt v.v...gi tr ni dung ca SP lun lun l phn offset
ca a ch ngn xp k tip.
- Thanh ghi con tr c s BP (Base Pointer) c chc nng cha gi tr offset tnh
t a ch SS nhng cn c s dng truy cp d liu bn trong ngn xp
- Cc thanh ghi ch s ngun DI v thanh ghi ch s ch SI (Destination Index v
Source Index) c dng lu gi cc thnh phn offset i vi nhng vng
d liu c ct trong on d liu. Hai ni dung ca hai thanh ghi ny lin kt
vi ni dung thanh ghi on DS to ra a ch ngun v a ch ch ca vng
nh.
II.1.4 Cc ch lm vic MIN/MAX
P8086 c hai ch lm vic. ch MIN v ch MAX. Chn s 33 ca
B mn K thut my tnh
46
P8086 c coi nh l chn by (trap pin) cho P8086 trong vic nh ngha ch
lm vic. Nhng mch ph tr cn thit cho hai ch lm vic khng th tho mn
vi h thng 40 chn ca CPU loi ny, v vy mt s chn s m nhim nhng chc
nng khc khi c xc nh cho mt ch ph thuc vo cch ni chn MN/ MX .
Khi, c ni vi GND (mc in p OV), P8086 chuyn i cc chn t 24 n 3 1
sang ch MAX. Mt mch ph iu khin BUS 8288 s gii m cc tn hiu trng
thi S0 , S1 , S2 to ra cc tn hiu nh thi v cc tn hiu iu khin tng thch
vi cu trc MULTIBUSTM trong cc h thng my tnh. Khi c ni ln mc in
p ngun nui (mc Vcc +5V) t P8086 to cc tn hiu iu khin BUS trn cc
chn t 24 n 31 nh c ghi trong ngoc Hnh II. 14.
II.1.5 Phng thc qun l b nh, cc mode a ch
a. Phng thc qun l b nh.
BUS a ch ca P8086 c di 20 bits, do vy c th qun l c 220 = 1M
nh (Mi t hp "0" hoc "1" ca cc bit trong 20 bits a ch xc nh v tr ca mt
nh). V mt nh trong h Vi x l l 1 Byte, nn ni cch khc, khng gian nh m
P8086 qun l c l 1Mbyte..
Cc thanh ghi ca P8086 ch c di 16 bits, nn nu dng mt thanh ghi
nh a ch th ch qun l c 216 nh, tc l 64KB. gii quyt vn qun l
1MByte, tc l 1.048.576 Bytes, P8086 s dng BUS a ch c rng 20 bits
thng qua ni dung ca hai thanh ghi 16 bits nh a ch ca b nh theo phng
thc sau:
Hnh II.20 Cch chia on nh trong P8086

Bng cch lp chng trnh, khng gian a ch c chia thnh cc on
(segment) nh vi kch thc c nh l 64kbytes gi l mt n v logic ca b nh.
Mi on gm cc nh lin tip, c lp v c nh v tch ri nhau. Mi on
c ngi lp trnh gn cho mt a ch on, l a ch nh u tin ca on ,
cn c gi l a ch nn. Gi tr ca cc a ch on lin k cch nhau ti thiu l
16 Bytes. Cc on c th k cn, tch ri ph lp nhau. Bn trong on s s, dng
cc gi tr lch (offset), tc l khong cch t a ch on n nh nm trong on.
B mn K thut my tnh
47
Mt cp gi tr a ch on v gi tr lch, [segment]:[offset], c gi l a ch
logic. a ch logic cho php nh v chnh xc mt Byte nh trong khng gian a ch.
a ch on c cha trong cc thanh ghi on, gi tr dch chuyn c cha trong
cc thanh ghi a nng, con tr hoc ch s.
V bn cht, thanh ghi on cha 16 bits cao ca 20 bits a ch, gi tr dch chuyn l
16 bit thp, v s lch nhau 4 bits c n v a ch ca BIU gii quyt nh trnh by
trong hnh II. 18: Dch tri thanh ghi on 4 bits (tng ng php nhn vi 16, cng vi
gi tr dch chuyn offset trong thanh ghi a nng tnh a ch vt l ca nh. Cng
thc tng ng php "dch tri v cng" c th trnh by nh sau:
a ch vt l = 10H x (segment) + (offset)
Thanh ghi on l mt thanh ghi 16 bits c nhim v xc

nh on ca nh, cn thanh ghi a nng cng l mt thanh
ghi 16 bits. Vy thanh ghi on c th nh c 216 = 65.536
n v (64K) on nh v mi on c 64kbytes. vy Vi x l
P8086 c th nh a ch ti 64K x 64kbytes - 4Gbytes nh.
Thanh ghi on m CS xc nh on nh chng trnh m lnh k tip s c

ly thc hin, thanh ghi con tr IP cha a ch offset ca lnh k tip Cp CS:IP
to nn a ch logic ca lnh.k tip trong tun t thc hin chng trnh. Cc t lnh
ca h 80x86 c th c di t 1 byte n ti a l 15 bytes. Khi lnh c thc
hin, gi tr ca con tr IP do vy s tng ln ng bng s Bytes ca t lnh. Cn nh
rng ni dung ca thanh ghi con tr lnh IP cng vi ni dung thanh ghi on CS xc
nh a ch ca nh lnh tip theo trong tun t thc hin chng trnh.
b. Cc mode nh a ch
1. nh v thanh ghi (register addressing): Ton hng c truy xut nm ngay
trong thanh ghi ca CPU.
Th d MOV AX,BX
;chuyn ni dung ca ton hng ngun (ni dung

ca thanh ghi) BX vo ton hng ch AX. Ni
dung thanh ghi BX vn c gi nguyn.
2. nh v tc thi (immedate addressing): Ton hng tc thi l d liu 8 hay 16

bits nm ngay trong lnh, c th dng lm ton hng ngun hay hng s. Ton hng
tc thi c lu gi ngay trong on m ca b nh, ngay sau m lnh, n c ly
B mn K thut my tnh
48
ra cng vi lnh v ghi vo hng i lnh PQ, do vy c truy xut nhanh hn so vi

truy xut ton hng t b nh. Th d MOV AL, 12H; np s 12H vo thanh ghi AL
3. Cc kiu nh v b nh
Khc vi hai kiu nh v trn, ton hng trong on nh d liu c CPU truy
xut qua BUS d liu. Bit rng, a ch vt l ca nh c tnh t ni dung thanh
ghi on v offset theo cch trnh by trong Hnh II. 18. Gi tr offset m n v thc
hin lnh EU tnh cho mt ton hng trong on nh c gi l a ch hiu dng EA
(effective address) ca ton hng. n v thc hin lnh c th tnh EA da vo cch
m t a ch trong phn ton hng ngun ca lnh. Ngoi gi tr trc tip, hoc ni
dung thanh ghi c s hay thanh ghi ch s, khi cn cn c th c mt gi tr s c
di 8 bits hay 16 bits c cng thm vo gi l gi tr dch chuyn d (displacement).
Xem Hnh II.21
Hnh II.2 1 M t cch xc nh a ch vt l ca nh cn truy xut

C th nh sau:
- nh v trc tip (direct addressing): Ton hng cha a ch l mt s nm ngay
trong lnh. a ch on hin ti nm trong thanh ghi on DS.
Th d MOV CX,[1435H] ;chuyn ni dung nh c a ch offset bng
1435H trong on s liu hin ti vo thanh ghi CX
- nh v gin tip thanh ghi (register indirect): a ch hiu dng EA l ni dung
ca mt trong cc thanh ghi BX, BP, SI hoc DI
Th d MOV AX, [SI]
B mn K thut my tnh
; chuyn ni dung ca nh trong on s liu

hin ti c a ch offset l ni dung thanh ghi SI
49
- nh v c s (based addressing): EA l tng ca ni dung thanh ghi BX hoc BP

v gi tr dch chuyn dp nu c
Th d MOV [BXI + dp, AL; chuyn ni dung thanh ghi AL v nh c a
ch offset bng tng ca ni dung thanh ghi BX v
gi tr dch chuyn dp
- nh v ch s (indexed addressing): EA l tng ca ni dung thanh ghi SI hoc
DI v gi tr dch chuyn dp nu c
Th d MOV AL,[SI] + dp ;Chuyn ni dung nh c a ch offset bng tng
ca ni dung thanh ghi SI v gi tr dch chuyn dp
vo thanh ghi AL
- nh v ch s v c s (indexed addressing): EA l tng ca ni dung cc thanh
ghi c s, thanh ghi ch s v gi tr dch chuyn dp nu c
Th d MOV AH,[BX][SI] + dp, chuyn ni dung nh c a ch offset bng
tng ca ni dung thanh ghi BX, thanh ghi SI v
gi tr dch chuyn d vo thanh ghi AH
- nh v chui (string addressing): dng ring cho x l chui. CPU s t ng s
dng cc thanh ghi ch s ngun SI v thanh ghi ch s ch DI ch n cc byte k
tip
Th d MOVS
;di chuyn chui, ngun ti vng nh c a ch u

l DS: SI, ch l vng nh c a ch u DS: DI.
II.1.6. Phng thc nh a ch thit b ngoi vi

C hai phng thc c bn nh a ch thit b ngoi vi:
nh a ch tch bit (isolated I/O address): Cc tn hiu iu khin phi c
phn bit i vi cc thao tc ghi/c b nh v ghi/c thit b ngoi vi. Trong h Vi
x l P8085, t hp cc tn hiu RD , RW v IO/ M s c gii m to ra cc tn
hiu c ghi ring cho b nh ( MEMR v MEMW ) v ring cho thit b ngoi vi
( I/OR v I /OW ). i vi h 80x86, l vic s dng cho iu khin BUS (BUS
B mn K thut my tnh
50
Controllel 82.88) gii m t hp cc tn hiu nhp ng h CLK, cc tn hiu trm

S2, S1 v S0 trong ch MAX thnh cc tn hiu MRDC , MWTC , IORC v IOWC .
Cc mch logic ph tr iu khin truy nhp thit b ngoi vi trong h Vi x l c
nhim v pht hin cc tn hiu IORC v IOWC thc hin cc thao tc vo/ra d
liu. Mch logic ny c nhim v gii m a ch thit b ngoi vi to ra cc tn hiu
cho php truy nhp ti thit b c th (thng c gi l mch gii m a ch thit b
ngoi vi). Cng cn ni thm rng a ch thit b ngoi vi thc t l a ch ca mt
thanh ghi trong thit b ngoi vi. Nh vy, vic trao i d liu gia CPU v thit b
ngoi vi thc cht l trao i d liu gia CPU v thanh ghi trong khng gian thit b
ngoi vi. Cc P80x86 dnh 16 dy a ch thp (A15 A0) qun l mt khng
gian 64K thit b ngoi vi.
nh a ch tuyn tnh (Linear Addresing I/O), cng cn gi l nh a ch thit
b ngoi vi theo bn nh (Memory-Mapped I/O): Thanh ghi trong thit b ngoi vi
c coi nh mt v tr nh trong khng gian nh, do vy khng s dng n cc tn
hiu iu khin ring cho vic trao i d liu gia CPU vi thit b ngoi vi, m s
dng hon ton chung cho b nh cng nh cho thit b ngoi vi. i vi P8085, tn
hiu phn bt O/M khng cn thit na, cng nh khng cn gi m cc t hp tn
hiu S2 , S1 v S0 i vi cc trung tm 80x86. Mi thao tc trao i d liu gia CPU
v cc thanh ghi thit b ngoi vi u c tin hnh nh vi mt nh trong b nh.
II.1.7 Cc mch Multiplexer, mch Decoder, mch PLA
Cc mch Multiplexer, mch Decoder hay mch PLA l nhng mch ph tr
khng th thiu ca mt h Vi x l. Thng thng, cc mch Decoder v mch PLA
(Programmable Logic Array) c thit k sn trn mt chip, c s dng nhiu
trong cc mch gii m cc tn hiu iu khin, gii m a ch ca vng nh hay a
ch thit b ngoi vi.
- Cc mch Multiplexer (hoc Coder)
Mch Multiplexer (cn gi l mch Coder)thng c xy dng theo mc ch
s dng, c khi rt phc tp. Mt trong nhng v d l mch thu nhn v m ho bn
phm (keyboard), c xy dng trn c s mt chip Vi x l chuyn dng, bao gm
c phn cng ln chng trnh. S khi chc nng ca mt mch Multiplexer c
th hin trn Hnh II.17. Cc tn hiu vo ring r x1, x2, x3 xn, qua x l s to ra
mt t hp nh phn u ra {ymym-1y0}. Phn chuyn i t mt tn hiu vo xi thnh
t hp ra {ymym-1 y0} c thc hin nh mch t hp logic hoc kt hp vi phn
mm chuyn dng.
B mn K thut my tnh
51
Hnh II. 23 S khi mt mch Multiplexer (coder)

- Mch gii m (Decoder)
Cc mch gii m thng thng 1/4, 1/8 c xy dng nh mt chip ph tr
trong cc h Vi x l. C th k n nh mch gii m 1/16 SN74154, mch gii m
1/8 74138 v.v... Bng chn l ca mch gii m 1/8 nh sau:
E3
E2
E1
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Hnh II.25 S ni chn mch gii m nh phn 1/8 v bng chn l

Vi mch gii m nh phn 1/8 c s ni chn nh
Hnh II. 18. Khi vi mch gii m c "Enable", ng vi
t hp cc gi tr E3E2E1 = 100, v vi bt k t hp no
ca cc gi tr A2A1A0 u c mt li ra c gi tr LOW.
ng vi li ra ny s l mt v tr hoc mt vng nh
c chn, hoc mt thit b ngoi vi. i vi cc vi
mch c chn CS (chip select), y l tn hiu chn v
thch hp.
- Mch PLA (Programmable Logic Array)
Mch PLA thc cht l mt chip nh ROM c ghi sn theo mt quy lut no
B mn K thut my tnh
52
theo phng thc gii m mt t hp nh phn u vo. C ngha l ng vi mt

nh l mt t hp gi tr theo mt quy lut gii m u vo, m u vo y chnh l
a ch ca nh . Cc mch PLA thch hp vi nhng ni cn s dng b gii m
vi s lng u vo ln hn 3.
II.1.8 Vi nt v lp trnh hp ng
Hp ng (Assembler) l mt cng c rt mnh c s dng trong vic pht trin
m lnh ca cc h Vi x l v my vi tnh. Hp ng l chng trnh dch cc lnh gi
nh (Mnemonics) v cc k hiu (symbols) thnh m my cho cc h vi x l v my
vi tnh thc hin. Cn phn bit rng hp ng l mt chng trnh, ch khng phi l
mt phn ca phn cng.
D liu vo ca hp ng l tp cc lnh gi nh, v d liu ra ca hp ng chnh
l cc tp cc byte m my nh phn, m thc thi c nh a ch chnh xc trong
khng gian nh chng trnh.
D liu vo c gi l m ngun (source code), d liu ra c gi l m thc thi
hoc m i tng (object code). Qu trnh m ngun c dch thnh m i tng
c gi l assembly. Cng c phn mm thc hin qu trnh ny gi l hp ng
(assembler). C th thy rt d dng rng: vit mt lnh MOV A,M d nh hn rt
nhiu so vi m hexa ca lnh ny: 7EH hoc m nh phn 01111110B
Hin c hai loi chng trnh hp ng ang c s dng rng ri: Hp ng
thng tr (Resident Assemblers) - c ci t ngay trong h thng, v hp ng
chuyn i (Cross Assemblers) khng c ci t ngay trong h thng, m l trong
mt my ch khc. M chng trnh do my ch to ra t hp ng khng th chy
c trn my ch.
Ngoi ra cn tn ti hai loi hp ng khc l hp ng tuyt i (Abssolute
Assembler), v hp ng ti nh v (Relocatable Assemblers), s c gii thiu trong
cc trnh hc hp ng sau ny.
II.3 Cu trc v tnh nng ca mt s chip V x l hin i.
Tri qua my thp k pht trin, cng ngh ch to cc chip Vi x l c nhng
bc tin v bo. xut hin nhiu kiu cu trc chip Vi x l nh CISC (Complete
Instruction-set Computer), RISC (Reduced Instruction- Set Computer), b x l scalar
hay superscalar, Vi x l VLIW (Very Long Instruction Word), Vi x l
Superpipelined, Vi x l Vector, v Vi x l biu tng (Symbolic P), nhm p ng
nhu cu to nn nhng my tnh cc mnh, nhng siu my tnh, mainfram phc v
nhng cng vic tnh ton ln hay to ra cc my tnh x l song song.
i vi h x86, c cc trung tm i486 vi cu trc RISC, tp lnh rt gn vi
tc x l tng nhanh ng k. l nhng trung tm x l 32 bits thc s. Khng
gian a ch vt l v khng gian b nh o c qun l bi 32 bits a ch, ln n
B mn K thut my tnh
53
4Gbytes. Ngoi ra, cc b ng x l ton cng c tch hp to nn sc mnh ng

k. Cc trung tm ny c s dng to nn nhng my tnh x l song song.vi
cu trc hin i v kh nng tnh ton ln cho php gii nhng bi ton rt phc tp.
Nm 1992, chip x l Pentium MMX ra i, trong cu trc c ti hai ng ng
song song (superscalar), hai khi s hc v logic (ALU) cho php thi hnh hai lnh
my trong mt chu k. BUS ni b ca Pentium MMX l BUS 64 bits v 128 bits, tc
trao i d liu vi b nh do vy c nng cao ng k. c bit, chip Pentium
c mt vng nh gi l vng m ch r nhnh BTB (Branch Target Buffer) i vi
256 lnh r nhnh mi. Pentium cng c tch hp mt b ng x ton hc
(Mathematical Coprocessor) vi hiu sut rt cao nh gii thut nhnh hn. D l loi
Vi x l CISC, nhng Pentium ng dng ging nh cc loi Vi x l RISC tc
cao: x l ng ng, cu trc superscalar v d on r nhnh.
Nm 1999, chip Pentium PIII ra i vi cu trc c thm 70 lnh cho truyn thng
a phng tin, tc xung nhp vt qua ngng 1 GHZ. Tip theo l cc chip
Pentium PIV vi tc cao hn hn v cu trc a phn lung.
IBM cho bit h ang p dng nhng phng php sn xut mi nhm cho php
thit b x l dnh cho my ch Power6 c th chy nhanh gp hai ln so vi hin nay
nhng vn m bo yu cu v nhit .
Theo thng tin t Gim c k thut ca IBM, h khng ch thu nh kch c cc
bng bn dn (transistor) m cn thay i phng thc hot ng ca silicon khi t
lp cch in pha di mt lp silicon gm khong 500 nguyn t.
Nhng ci tin khin Power6, sn xut theo

ng ngh 65 tm v d nh ra mt gia nm 2007,
t xung nhp ti 4 - 5 GHZ. IBM khng nh
Power6 s cnh tranh trc tip vi sn phm ca
cc i th th lntel, AMD v Sun Microsystems.
Ngay khi lntel gii thiu cng ngh 90 nm nm
2003, ngi ta nhn thy n gy ra tnh trng tht
thot nng lng nghim trng hn nhng phng
php sn xut trc , khin chip ta nhit ngay
c khi chng khng chy ht cng sut. Mt trong nhng bin php khc phc l tch
hp 2 li x l trn mt chip n v gim xung nhp hot ng tng kh nng vn
hnh cng nh trnh rc ri do nhit cao. Ngc li, Power6 c xy dng
hot ng xung nhp cao cha tng thy nhng vn tiu th in nng hiu qu.
Hin nay, lntel cng ang nghin cu hai k thut sn xut v thit k mi nhm
gim lng in tiu th trn bng mch h thng. Phng php th nht cung cp
ngun in p cho c CPU v b nh m (ca che) cn cch th hai s tch hp b
B mn K thut my tnh
54
iu ha in p trn cc transistor.
Th t, 21/6/2006, 10:04 GMT+7 C~JC~ IBM Pht trin chia 500 GHZ
"Big Blue" v Cng ty Georgia Tech cng ch to
mt chip c xung nhp cao hn 100 ln so vi k lc ca
thit b x l my tnh hin nay, vi iu kin n phi
hot ng nhit nghe c v phi thc t - 268,50C.
nhit trong phng, chip ny vn t tc 350
GHZ, tng ng 350 t vng/giy, nhanh hn nhiu so
vi thit b x l my tnh ti thi im ny (dao ng t
1,8 GHZ n 3,8 GHZ).
y l mt phn d n khm ph tc ti a ca cc chip silicon-germani
(SiGe). SiGe cng ging nh cng ngh chip silicon khc nhng c tng cng
nguyn t germani nng hiu sut v gim lng in tiu th. Trn l thuyt,
SiGe c th m rng tc ln 1 terahertz (THZ), tc mt nghn t vng mi giy.
Tuy nhin thm thnh phn germani ng ngha vi chi ph sn xut tm wafer
tng cao, do SiGe rt kn chn th trng. IBM bn ra hng trm triu chip ny
t nm 1998, nhng cha th ch ni khi so vi con s hng t chip silicon mi nm
nh sn lng in thoi di ng.
Chip SiGe hiu sut ln s c ng dng trong cc h thng phng th, phng
tin khm ph v tr v thit b cm ng t xa.
II.3.1 Cu trc chip Vi x l Pentium
Pentium l loi n v x l trung tm 32 bit v l loi n v x l trung tm u
tin s dng k thut ILP (lnstruction Level Pararellism), k thut x l lnh song
song.
K thut ng ng v k thut x l lnh song song ILP
Mt lnh thng c x l qua nm giai on:
1. Nhp lnh (FI Fetch the Instruction)
2. Gii m lnh (DI Decode the Instruction)
3. To a ch ton hng (GOA Generate Operand Address)
4. Nhp ton hng (FO Fetch Operands)
5. Thc hin lnh (EI Execute Instruction)
Vi k thut x l lnh thng thng, n v x l trung tm phi tun t thc
hin xong tt c cc giai on thc hin mt lnh, thng l sau 5 chu k my, ri mi
chuyn sang nhp v thc hin lnh tip theo. D tng tc x l lnh m khng nht
thit phi tng tn s nhp ca my, ngi ta s dng cc k thut khc nh k thut
B mn K thut my tnh
55
x l lnh kiu ng ng (Pipeline) v k thut x l lnh song song (ILP).

K thut x l lnh kiu ng ng (Pipeline)
K thut x l lnh kiu ng ng c s dng trong cc n v x l trung tm
t i n v x l trung tm Intel 8086.
Chu k my
ng ng tng t nh dy chuyn sn xut nhiu cng on. dy chuyn sn

xut, mi cng on thc hin mt thao tc sn xut. Sn phm c c chuyn v
hnh thnh dn sau mi cng on sn xut, cho n khi c hon thnh cng on
cui cng. Trong k thut x l lnh theo kiu ng ng, vic thc hin lnh cng
c thc hin qua 5 thao tc, mi thao tc c thc hin trong mt giai on, giai
on n tip sau giai on kia, cho n khi thc hin song lnh. Vi mt ng ng 5giai on, ti mi chu k my c 5 b d liu thuc 5 giai on x l c gi vo
ng ng v 5 thao tc c thc hin ng thi, nh vy m sau mi chu k my li
c mt lnh c hon thnh v mt lnh mi c nhp. K thut ng ng vi
ng ng 5-giai on cho php tng tc thc hin lnh ln gp 5 ln. K thut ILP
(x l lnh song song)
K thut ILP l k thut thit k n v x l trung tm v chng trnh dch nhm
lm tng tc cc thao tc my (nh ghi-c b nh) v thc hin cc php tnh.
Trong cc k thut ILP c k thut superscalar, trong ti mt chu k my nhiu
lnh c nhp v c thc hin ng thi trn nhiu ng ng khc nhau.
Pentium l loi n v x l trung tm c thit k theo k thut superscalar,
trong hai lnh c nhp v gii m ng thi. Pentium c hai ng ng thc hin
lnh song song U v V. Qu trnh thc hin lnh c m t nh sau:
B mn K thut my tnh
56
Hnh II. 26 Cu trc trung tm Vi x l Pentium

Pentium l n v x l trung tm loi 32bit v l n v x l trung tm loi CISC
(Complex Instruction St Computer) vi c im: h lnh phc tp, nhiu kiu xc
nh a ch, nhiu khun dng lnh v nhiu kch thc lnh khc nhau.
Pentium c BUS a ch trong v ngoi 32 bit, BUS d liu trong v ngoi 64 bit.
Pentium c hai cache 8 Kbyte c lp: mt cache 8 Kbyte 2 cng dnh cho d liu v
mt cache 8 Kbyte cha lnh. Pentium c hai ng ng thc hin lnh song song U
v V, v 2 n v s hc-logic ALU. Pentium c mt ng ng ring thc hin cc
lnh du phy ng v mt b ng x l du phy ng FPU c tch hp trong
chip.
Pentium c cc thanh ghi sau:
Cc thanh ghi h thng:
-
Cc thanh ghi iu khin 32 bit: CR0, CR1, CR2, CR3
Cc thanh ghi h thng qun l b nh:
GDTR: Thanh ghi bng m t ton cc (Global Descriptor Table Register)

LDTR: Thanh ghi bng m t cc b (Local Descriptor Table Register)
IDTR: Thanh ghi bng m t ngt (Interrupt Descriptor Table Register)
TR: Thanh ghi nhim v (Task Register)
B mn K thut my tnh
57
- Cc thanh ghi on 16 bit:
B mn K thut my tnh
58
II.3.2 Cu trc RISC, CISC

RISC: (Reduced Instruction-set Computer)
CISC: (Complete Instruction-set Computer)
B mn K thut my tnh
59
Cch n gin nht c th kho st nhng u nhc im ca kin trc IUSC l

so snh vic thc hin mt php ton i vi loi kin trc CISC trc y. Gi s ta
phi thc hin mt lnh nhn hai ton hng c lu gi trong b nh.
Hnh II.... m t t chc ca mt my tnh. B nh c to t cc nh t 1: 1
(hng 1: ct 1) n 6:4 (hng 6: ct 4). Khi thc hin lnh c nhim v thc hin cc
lnh tnh ton x (nhn),: (chia), + (cng) v - (tr). Tt nhin, khi thc hin tnh ton
ch c th lm vic vi cc d liu (ton hng) c cha sn mt trong cc thanh
ghi A, B, C, D, E hoc F. Gi s ta phi tm tch 2 s, s th nht c cha 2:3 v
s th hai 5:2, kt qu s c lu li vo 2:3. By gi ta s tip cn cch gii
quyt vn trn hai loi CPU, CISC v RISC.
Trn CPU CISC: u tin hng u ca loi CPU ny l hon thin mt cng vic
vi t lnh nht c th. iu ny c th thc hin nh vo vic xy dng mt phn
cng CPU c kh nng hiu c v thc hin c mt chui cc tc nghip. Trong
trng hp c th ny, CISC s c mt lnh xc nh duy nht, tm gi l MULT, m
khi thc hin, lnh s np hai gi tr ton hng vo 2 thanh ghi sau thc hin php
nhn ri ghi kt qu vo mt thanh ghi tng ng. Nh vy cng vic s c th hin
bng mt lnh nh sau:
MULT 2:3,5:2
Lnh MULT l mt lnh hon thin (complex). Lnh lm vic trc tip trn bng
nh ca my tnh, ch khng cn ngi lp trnh phi dng lnh gi hay np ni dung,
ghi ni dung vo nh. Lnh rt gn vi ngn ng bc cao. Gi s ta gi "a" l gi tr
ca ton hng trong nh 2:3 v "b" l gi tr ton hng trong nh 5:2, th lnh
tng ng trong ngn ng C l "a = a * b u im ln nht ca h thng CISC l
chng trnh dch phi lm rt t vic khi dch mt chng trnh, hay mt lnh ca
ngn ng bc cao sang ngn ng my. V di ca m lnh rt nh, nn h thng
cng cn t RAM hn ghi nh lnh. D nhin, vic thit k cu trc loi CISC c
bit s phi tch hp cc lnh hon thin bng phn cng.
Trn CPU RISC: Cc CPU loi RISC ch s dng cc lnh (lnstruction) c th
thc hin c trong mt chu k xung nhp. Nh vy lnh MULT c m t phn
trn phi c chia thnh 3 lnh nh hn. LOAD chuyn d liu (ton hng) t
nh vo thanh ghi; PROD" thc hin php nhn hai ton hng c lu gi trong cc
thanh ghi, v lnh "STORE" s thc hin vic chuyn kt qu tnh ton ghi vo nh.
thc hin c php nhn hai ton hng, ngi lp trnh phi m ho thnh 4 lnh
nh sau: LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
B mn K thut my tnh
60
C th thy rng vi cu trc RISC, khng thun li lm cho hon thnh php ton
nhn hai s v phi vit nhiu dng lnh hn, cn nhiu RAM hn lu gi cc lnh
mc assembly. Chng trnh dch cng phi phc hin nhiu vic hn chuyn i
cc lnh ca ngn ng bc cao sang m my. Th nhng, chin lc RISC mang
n nhiu thun li quan trng. V mi lnh ch cn mt chu k xung nhp thc
hin, ton b chng trnh cng s ch cn s chu k xung nhp nh khi thc hin lnh
MULT h thng CISC. Nhng kin trc RISC vi h lnh rt gn cn t linh kin v
khng gian cho mch tch hp, b qua c cc thanh ghi a nng. Hn na, mi lnh
ch thc thi trong mt chu k xung nhp nn vic t chc ng ng cng n gin
hn nhiu.
Vic tch lnh "LOAD" v lnh "STORE" n gin ho ng k khi lng
cng vic CPU phi thc hin. Sau khi thc hin lnh MULT cu trc CISC CPU t
ng xo ni dung cc thanh ghi. Nu mt ton hng no cn tp tc c s dng
cho lnh tip theo, CPU phi np li. cu trc RISC, ni dung ca ton hng vn
c gi li cho n khi mt gi tr mi c np vo.
Cui cng, so snh mt cch ton din hn, cng thc sau c dng nh
gi kh nng tnh ton, x l ca cc loi CPU:
CISC c gng gim s lnh trong mt chng trnh, hy sinh s chu k thc hin
mt lnh trong khi RISC theo chin lc ngc li.
Mt s thng tin th v cho c gi: Ch cc chip h x86 vn trung thnh vi kin
trc CISC, d nhin khng c thng dng lm v nhng l do khc: Trc ht do s
pht trin v bo ca cng ngh tch hp mch, trong cng ngh sn xut linh kin
in t. S gim gi n mc kh hiu ca b nh RAM cng lm o ln cch nhn
nhn nhng nhc im ca cc CPU theo kin trc RISC. Gi lMbyte RAM nm
1977 l khong 5000USD, nhng n nm 1994 l khong 6USD, cn ti thi im
ny (2005) l khong hn 0,2 USD! Cng ngh chng trnh dch (compiler
technology) cng tr nn hon thin hn nn CPU loi RISC cng vi b nh RAM
dung lng ln v cng ngh phn mm tr thnh l tng hn nhiu i vi cc
hng sn xut my tnh.
II.3.3 Qun l b nh
a ch (address) l phng thc duy nht xc nh v tr (location) ca mt
nh trong "khng gian a ch (address space).
B mn K thut my tnh
61
a ch c th hin bng mt s
nguyn nh phn khng du v c lu
gi trong cc thanh ghi chuyn dng v
thanh ghi a nng vi nhng k thut
hon thin. a ch c gii m. bng
phn cng truy xut n mt v tr
nh trong cc khi nh vt l, v d b
nh RAM hoc ROM hay trong mt
ngun nh c bn ho (memory
mapped resource).
Hnh bn biu din cch nhn tng
qut v a ch, khng gian a ch v v
tr nh trong kin trc my tnh 32 bit.
C th thy a ch nh l mt con tr
(pointer), mt s nguyn nh phn tham
chiu n mt i tng hay mt v tr
nh ( nh). D nhin, to ra c mt con tr, cc k thut nh phn on
(segment), s dng lch (offset) v gi tr dch chuyn (displacement) c s dng
v c to nh n v giao din BUS (BIU) trong cc CPU.
Khng gian a ch l tp tt c cc a ch, cng c th hnh dung nh l mt hm
ring tham chiu n cc nh. Thng thng, a ch bt u t 0 (zero) cho n 2N1, trong N l rng ca BUS a ch (l 6, 20, 24, 32 hoc 64). Khng gian ny c
th khng chnh xc vi kin trc phn on. Trong cc h thng hin i, phn ln
khng gian a ch c th c d tr nh kin trc ca h iu hnh, hoc tm thi
khng c bn ho. Nhng vn lin quan c gi c th tm thy trong cc ti
liu v khng gian b nh o v khng gian b nh vt l.
II.3.4 B nh cache
Cache l c ch nh tc cao c bit. Cache c th s dng nh mt vng nh
d tr trong b nh chnh nhng vi nhng chip nh tc cao. C hai loi b nh
cache c s dng chung trong my PC, memory cachtng v disk caching.
Memory cache cn c gi b nh cache hay RAM cache, s dng RAM anh

(SRAM) tc cao. Rt hiu qu v nhiu chng trnh truy nhp cc d liu hoc
lnh thng qua vng nh ny. Bng cch lu gi d liu v lnh trong cache, tc
B mn K thut my tnh
62
truy nhp b nh c nng cao. Cng c mt loi memory cache c tch hp trc
tip trong CPU nh cc CPU 80486 (8KB), Pentium l 16KB. Chng c gi l
cache ni b (internal cache), hay cache mc 1 (Li). Cc PC cn h tr cache ngoi
(External cache), cn gi l cache L2, l b nh c dng trng gian gia CPU v b
nh chnh DRAM.
Disk cache lm vic ging nh nguyn l ca cache nh, nhng thay v s dng
SRAM, cache a s dng DRAM nh b nh chnh. Phn ln d liu c truy xut
t a c lu gi trong cc vng nh m. Mi khi chng trnh truy xut a, thng
thng n kim tra xem, cc d liu c lu vo vng cache a hay cha.
cache ng vai tr rt quan trng trong vic nng cao tc truy xut, v truy xut
mt byte d liu trong RAM c th ni nhanh hn gp ngn ln truy xut mt byte d
liu t cc a. Khi d liu c tm thy trong b nh cache, tc l cache hit, v
hiu sut ca cache c nh gi bng hit rate. Hu ht cc h thng cache u s
dng k thut smart caching, c ngha l h.thng lun lun ghi nhn mt s loi d
liu thng c s dng nht. Chin lc xc nh cc thng tin no c lu gi
vo trong b nh cache l vn c c bit quan tm trong khoa hc my tnh.
II.4 Single-chip Microcomputer C8051
II.4.1 Tng quan
Ngoi cc trung tm vi x l h x86, Intel cn thit k v sn xut cc trung tm
Vi x l chuyn dng phc v cc mc ch o lng v iu khin t ng, phc v
cc ng dng n gin nhng rt ph bin khc. Cc chip Vi x l loi ny vt ra
ngoi khun kh ca mt trung tm Vi x l n thun, tr thnh mt Vi my tnh
(Microcomputer). Cng c th nhn nhn rng, cc trung tm Vi x l h ny l mt Vi
my tnh thc th, nu nhn nhn chip ny theo quan im kin trc ca ng t my
tnh Von Neumann: Chip c trang b thm b nh chng trnh (ROM hoc
EPROM) v b nh d liu, cng nh cc cng vo/ra ni tip, vo/ra song song.
MCS-51 l h vi iu khin ca IntelR. Cc nh sn xut khc nh Siemens,
Advanced Micro Device, Fujitsu va Philip c cp php lm cc nh cung cp cc
chip ca h MCS -51.
Vi mch ch yu ca h MCS - 51 l chip C8051, linh kin u tin ca h ny
c a ra th trng. Chip C8051 c cc c trng c tm tt nh sau:
o 4 KB ROM v 128 byte RAM
o 4 port 8- bit, 32 li vo/ra
o 2 b nh thi 16 bit
o Mch giao tip ni tip
o Khng gian nh chng trnh (m rng) ngoi 64K
B mn K thut my tnh
63
o Khng gian nh d liu ngoi 64K

o B x l bit (thao tc trn cc bit ring r)
o 210 v tr bit nh c nh a ch
o Nhn chia trong thi gian 4s.
Cc thnh vin khc ca h MCS-51 c cc t hp ROM (EPROM), RAM trn
chip khc nhau hoc c thm b nh thi th ba. Mmi mt chip ca h MCS -51 u
c phin bn CMOS tiu th cng sut thp.
Di y l thng s c bn ca mt s C h MCS-51:
Chip
8051
8031
8751
8052
8032
8752
B mn K thut my tnh
B nh
chng trnh
trn chip
4 K ROM
0K
4 K EPROM
8 K ROM
0K
8 K EPROM
B nh d
liu trn chip
Cc b nh
nh thi
128 byte
128 byte
128 byte
256 byte
256 byte
256 byte
2
2
2
3
3
3
64
Port 0 (cc chn t 32 n 39) c hai

cng dng. Trong cc thit k ti thiu. port
0 c s dng lm nhim v vo/ra. Trong
cc thit k ln hn c b nh ngoi. port 0
tr thnh bus a ch v bus d liu dn
knh.
Port 1 ch c mt cng dng l vo/ra
(cc chn t 1 n 8). v dng giao tip
vi cc thit b ngoi vi h0oc lm cng
vo/ra hoc lm cc li vo cho mch anh
thi th ba.
Port 2 (cc chn t 21 n 28) c hai
cng dng. hoc lm nhim v vo/ra hoc
l byte a ch cao ca bus a ch 16-bit
Hnh II.28. S khi chn chip C8051
cho cc tht k c b nh chng trinh
ngoi hoc cc thit k c nhiu hn 256 byte b nh d liu ngoi Port 3 (cc chn t 10
n 17) c hai cng dng. Khi khng hot ng vo/ra, cc chn ca port 3 c nhau chc
nng ring mi chn c chc nng ring lin quan n cc c trng c th ca 8051)
II.4.2 M t cu trc v chc nng
Hnh II.28 cho ta s chn ca chip 8051. Chc nng tm tt ca tng chn nh
sau. 32 trong s 40 chn ca 8051 c cng dng vo ra, tuy nhin 24 trong 32 ng
ny c hai mc,ch, mi ng c th hot ng vo/ra hoc hot ng nh mt
ng iu khin hoc nh mt ng a chun liu ca bus a chun liu dn knh.
32 chn nu trn hnh thnh 4 port 8-bit. Vi cc thit k yu cu ti thiu b nh
ngoi hoc cc thnh phn bn ngoi khc ta c th s dng port ny lm nhim v
vo/ra. 8 ng cho mi port c th c x l nh mt n v giao tip song song
vi cc thit b ngoi vi.
+ Port 0
Port 0 (cc chn t 32 n 39) c hai cng dng. Trong cc thit k ti thiu, port
0 c s dng lm nhim v vo/ra. Trong cc thit k ln hn c b nh ngoi, port
0 tr thnh bus a ch v bus d liu dn knh.
+ Port 1
Port 1 ch c mt cng dng l vo/ra (cc chn t 1 n 8), v dng giao tip
vi cc thit b ngoi vi hoc lm ng vo/ra hoc lm cc li vo cho mch nh
thi th ba.
+ Port 2
Port 2 (cc chn t 21 n 28) c hai cng dng, hoc lm nhim v vo/ra hoc l
B mn K thut my tnh
65
byte a ch cao ca bus a ch 16-bit cho cc thit k c b nh chng trnh ngoi

hoc cc thit k c nhiu hn 256 byte b nh d liu ngoi.
+ Port 3
port 3 (cc chn t 10 n 17) c hai cng dng. Khi khng hot ng vo/ra, cc
chn ca port 3 c nhiu chc nng ring (mi chn c chc nng ring lin quan n
cc c trng c th ca 8051).
+ Chn cho php truy nhp b nh chng trnh PSEN 8051 cung cp cho ta 4 tn
hiu iu khin bus. Tn hiu PSEN (Program store enable) l tn hiu ra trn chn 29.
y l tn hiu iu khin cho php ta truy xut b nh chng trnh ngoi, chn ny
thng ni vi chn cho php ra OE (output enable) ca EROM (hoc ROM), cho
php c cc byte lnh.
Tn hiu PSEN logic 0 trong sut thi gian tm np lnh (Instruction Fetch). Cc
m nh phn ca chng trnh hay opcode (m thao tc) c c t EPROM, qua bus
d liu v c cht vo thanh ghi lnh IR ca 8051 c gii m.
Khi thc thi mt chng trnh cha ROM ni, PSEN c duy tr logic khng
tch cc (logic 1).
+ Chn cho php cht a ch ALE
8051 s dng chn 30, chn cho php cht a ch ALE (address latch enable)
gii dn knh (demultiplexing) bus d liu v bus a ch. Khi port 0 c s dng
lm bus a chun liu dn knh, chn ALE a ra tn hiu cht a ch (byte thp
ca a ch 16-bit) vo mt thanh ghi ngoi trong sut 1/2 u ca chu k b nh
(memory cycle). Sau khi iu ny c thc hin cc chn ca port 0 s vo/ra d
liu hp l trong sut 1/2 th hai ca chu k b nh.
+ Chn truy xut ngoi EA
Li vo ny (31 chn) c th ni c vi 5V (logic 1) hoc ni vi GND (logic
0). Nu chn ny ni ln 5V, 8051/8052 thc thi chng trnh trong ROM ni
(Chng trnh nh hn 4K/8K). Nu chn ny ni vi GND (chn PSEN logic 0),
chng trnh cn thc thi cha b nh ngoi. i vi 8031/8032 chn EA phi 1
gic 0 v chng khng c b nh c hng trnh trn chip. Nu chn EA logc 0 i
vi 8051/8052, ROM ni bn trong chip c v hiu ho v chng trnh thc thi
cha E PROM bn ngoi.
Cc phin bn EPROM ca 8051 cn s dng chn EA lm chn nhn in p cp
in 2 1 V cho vic lp trnh EPROM ni.
+ Chn RESET (RST)
Li vo RST (chn 9) l li vo ti khi ng (master reset) ca 8051 dng thit
lp trng thi ban u cho.h thng hay gi tt l reset h thng. Khi li ny c treo
B mn K thut my tnh
66
logic 1 ti thiu hai chu k my, cc thanh ghi bn trong ca 8051 c np cc gi

tr thch hp cho vic khi ng li h thng.
+ Cc chn XTALI&XTAL2
Mch dao ng bn trong chip 8051 c ghp vi thch anh bn ngoi hai chn
XTAL 1 v XTAL2 (chn 18 v 19). Tn s danh nh ca thch anh l 12MHZ cho
hu ht cc chip ca h MCS-51 (Ring 80C3 lBH-l s dng thch anh 16MHZ bn
trong, mch dao ng trong chip khng cn thch anh bn ngoi). Mt ngun xung
clock TTL c th c ni vi chn XTALI v XTAL2.
Hnh 2.30 8051 ghp lt mch dao ng TTI bn ngoi

+ Cu trc ca Port vo/ra.
Hnh II. 31 Cu trc ca port vo ra

8051 internal bus: Bus ni ca
8051 Read latch: b cht phc
v c internal pull up: Mch
pull-up
Read pin: chn port

Port latch: B cht ca port
Write to latch: Ghi vo b cht
S mch in bn trong ca port vo/ra c v n gin nh hnh II.23, vic

ghi n 1 chn ca Port s np d liu vo b cht ca port, li ra Q ca b cht iu
khin mt Transistor trng v Transistor ny ni vi chn ca port. Kh nng fanout
ca cc port 1, 2 v 3 l 4. Ti vi mch TTL loi Schottky cng sut thp (LS) cn ca
port 0 l 8 ti loi LS.
B mn K thut my tnh
67
Ta thy c 2 kh nng: c b cht" v "c chn port". Cc lnh yu cu thao

tc c-sa-ghi c b cht trnh nhm ln mc in p do s kin dng ti tng.
Cc lnh nhp 1 bit ca port (nh MOV C,P 1. 5) c chn port. Trong trng hp
ny b cht ca port phi cha 1 nu khng transistor FET s c kch bo ho v
iu ny kch li ra di mc thp.
+ T chc b nh.
Hu ht cc b vi x l (CPU) u c khng gian nh chung cho d liu v
chng trnh, cc chng trnh c lu trn a v np vo RAM thc thi vy th
c hai d liu v chng trnh u lu tr trong RAM.
Cc chip vi iu khin him khi c s dng ging nh cc CPU trong cc h
my tnh, thay vo chng c lm thnh phn trung tm trong cc thit k hng
iu khin, trong c c b nh dung lng gii hn, khng c a v h iu hnh.
Chng trnh iu khin thng tr trong ROM.
8051 c khng gian v b nh ring cho chng trnh v d liu u t bn
trong chip, ta c th m rng b nh chng trnh v b nh d liu bng cch s
dng cc chip nh bn ngoi vi dung lng ti a l 64K cho b nh chng trnh
(hay b nh m) 64K cho b nh d liu
B nh trong chip bao gm ROM (Ch c 8051/8052) v RAM.
RAM trn chip bao gm vng RAM a chc nng v vng RAM vi tng bit c
nh a ch (gi l vng RAM nh a ch bit, cc Banh) v cc thanh ghi chc nng
c bit SFR (specail function register). Hai c tnh ng lu l:
(a) cc thanh ghi v cc port vo/ra c nh a ch theo kiu nh x b nh
(memory mapped) v c truy xut nh mt v tr trong b nh.
(b) Vng stack thng tr trn RAM trong chip (RAM ni) thay v trong RAM
ngoi i vi cc b vi x l.
+ Vng RAM a mc ch.
Vng RAM a mc ch c 80 byte t a ch t 30H n 7FH, bn di vng
ny t a ch 00H n 2FH l vng nh c th c s dng tng t. Bt k v tr
nh no trong Vng RAM a mc ch u c th c truy xut t do bng cch nh
a ch trc tip hoc gin tip.
+ Vng RAM nh a ch bit.
8051 cha 210 bit c nh a ch trong 128 bit cha trong cc byte a ch
20H n 2FH (16 byte x 8 bit = 128 bit) phn cn li cha trong cc thanh ghi c
bit. Truy xut cc bit ring r thng qua phn mm l mt c trng mnh ca hu ht
cc b vi iu khin. Cc bit c th c Set, Reset, AND, OR, v.v... bng mt lnh.
Hu ht cc b vi x l yu c u mt chui lnh c-sa-ghi nhn c cng mt
B mn K thut my tnh
68
kt qu. Ngoi ra 8051 cn c cc port vo/ra c th nh a ch tng bit, iu ny lm

n gin vic giao tip bng phn mm vi cc thit b vo/ra n bit.
+ Cc thanh ghi.
32 v tr thp nht ca b nh ni c s dng nh nhng thanh ghi. Cc lnh ca
8051 h tr 8 thanh ghi t R0 n R7 thuc bng 0 (bank 0) y l bng mc nh sau
khi reset h thng. Cc thanh ghi ny c nh a ch t 00H n 07H.
Cc lnh s dng cc thanh ghi t R0 n R7 l cc lnh ngn v thc hin nhanh
hn so vi cc lnh tng ng s dng kiu nh a ch trc tip. Cc gi tr s
dng nhiu nn cha mt trong cc thanh ghi ny. Bng thanh ghi ang c s
dng c gi l bng thanh ghi tch cc. Bng thanh ghi tch cc c th c thay i
bng cch thay i cc bit chn bng trong t trng thi chng trnh PSW.
+ Cc thanh ghi chc nng c bit (SFR)
Cc thanh ghi ca hu ht cc b vi x l u c truy xut r rng bi mt tp
lnh. Thao tc c xc nh r rng trong opcode ca lnh. Vic truy xut cc thanh
ghi cng c s dng trn 8051.
Cc thanh ghi ca 8051 c cu hnh thnh t mt phn ca RAM trn chip, do
vy mi thanh ghi cng c mt a ch. iu ny hp l vi 8051 v chip ny c rt
nhiu thanh ghi. Cng nh cc thanh ghi t R0 n R7, ta c 21 thanh ghi chc nng
c bit SFR chim phn trn ca RAM ni t a ch 80H n FFH.
+ C nh.
C nh CY (CARRY FLAG) c hai cng dng. Cng dng truyn thng trong cc
php ton s hc l c st bng 1 nu c s nh t php cng bit 7 hoc c s mn
mang n bit 7.
+ C nh ph.
Khi cng cc gi tr BCD, c nh ph AC (auxiliari cany flag) c st bng 1 nu
c mt s nh c to t bit 3 chuyn sang bit 4 hoc nu kt qu trong 4 bit thp
nm trong vng t OAH n OFH. Nu cc gi tr c cng l gi tr BCD, lnh cng
phi c tip theo bi lnh DAA (hiu chnh thp phn thanh cha A) a cc gi
tr kt qu ln hn 9 v gi tr ng.
+ C 0
y l c c nhiu mc ch dnh cho cc ng dng ca ngi lp trnh.
+ Cc bit chn dy thanh ghi
Cc bit chn dy thanh ghi RS0, RS1 dng xc nh dy thanh ghi tch cc. Cc
bit ny c xo sau khi c thao tc reset h thng v i mc logic bi phn mm khi
cn.
B mn K thut my tnh
69
+ C trn
C trn OV (overflow flag) c reset bng 1 sau php ton cng hoc tr nu c
xut hin mt trn s hc. Khi cc s c du c cng hoc c tr, phn mn c
th kim tra bit trn OV xc nh xem kt qu c nm trong tm hay khng.
+ C chn l
Bit chn l P t ng c st bng 1 hay xo bng 0 mi chu k my thit
lp kim tra chn l cho thanh cha A. S cc bit 1 trong thanh cha cng vi bit P
lun l s chn. Nu thanh cha c ni dung 10101101 B, bit P s l 1 c s bit 1l
6. bit chn l c s dng nhiu kt hp vi cc chng trnh vo/ra ni tip trc
khi truyn d liu hoc kim tra chn l sau khi truyn d liu.
+ T trng thi chng trnh PSW.
Bit
K hiu
a ch
M t bit
PSW.7
CY
D7H
C nh
PSW.6
AC
D7H
C nh ph
PSW.5
FO
D6H
C 0
PSW.4
RSI
D5H
Chn dy thanh ghi (bit 1)
PSW.3
RSO
D4H
Chn dy thanh ghi bit 0

00 = Bank 0: a ch t 00H n 07H
01 = Bank 1: a ch t 08 n 0FH
10 = Bank 2: a ch t 10H n 17H
11 = Bank 3: a ch t 18H n 1 FH
PSW2
OV
D3H
C trn
PSWI
D1H
D tr
PSWO
DOH
Kim tra chn l
+ Thanh ghi B
Thanh ghi B a ch FOH c dng chung vi thanh cha A trong cc php
ton nhn, chia. Lnh MUL AB nhn 2 s 8-bit khng du cha trong A v B v cha
kt qu vo cp Thanh ghi B:A (Thanh cha A cha byte thp v thanh cha B cha
byte cao ca tch s).
Lnh chia DIV AB chia A bi B, thng s cha trong thanh cha A v s d
cha trong Thanh ghi B. Thanh ghi B cn c x l nh mt thanh ghi nhp. Cc bit
c nh a ch ca thanh ghi B c a ch t FOH n F7H.
+ Con tr Stack
B mn K thut my tnh
70
Con tr stach SP (stack pointer) l mt thanh ghi 8 -bit a ch 81H. SP cha a

ch ca d liu hin ang nh ca stack. Cc lnh lin quan n stack bao gm d
liu ct vo stack v lnh ly d liu ra khi stack. Vic ct vo stack lm tng SP
trc khi ghi d liu v vic ly d liu ra khi stack s gim SP. Vng stack ca 8051
c gi trong RAM ni v c gii hn n cc a ch truy xut c bi kiu nh
a ch gin tip.
+ Con tr d liu DPTR
Con tr d liu DPTR (data pointer) dng truy xut b nh bn ngoi hoc b
nh d liu ngoi. DPTR l mt thanh ghi c a ch l 16 bit c a ch l 82H (DPL,
byte thp) v 83H (DPL, byte cao).
+ Cc thanh ghi port.
Cc port vo/ra ca 8051 bao gm port 0 ti a ch 80H, port 1 ti a ch 90H,
port 2 ti a ch AOH, v port 3 ti a ch BOH, cc port 0, 2 v 3 khng c dng
vo/ra nu ta s dng thm b nh ngoi hoc nu c mt s c tnh ca 8051
c s dng (nh l ngt, port ni tip,) P 1.2 n P 1.7, ngc li, lun l cc ng
vo/ra a mc ch hp l.
Tt c cc port u c nh a ch tng bit nhm cung cp kh nng giao tip
mnh.
+ Cc thanh ghi nh thi.
8051 c 2 b m nh thi (time/counter) 16-bit nh cc khong thi gian
hoc m cc s kin. B nh thi 0 c a ch l 8AH (TLO, byte thp) v 8CH
(TH0, byte cao); b nh thi 1 c a ch 8BH (TL 1, byte thp) v 8CH (TH 1, byte
cao).
Hot ng ca b nh thi c thit lp bi thanh ghi ch nh thi TMOD
(time mode register) a ch 89H v thanh ghi iu khin nh thi TCON (time
control register) a ch 88H. Ch c TCON c nh a ch tng bit.
+ Cc thanh ghi ca port ni tip.
Bn trong 8051 c mt port ni tip truyn thng vi cc thit b ni tip nh
cc thit b u cui hoc modem, hoc giao tip vi cc IC khc c mch giao tip
ni tip (nh cc thanh gh dch).
Mt thanh ghi c gi l b m d liu ni tip S BUF. (serial data buffer)
a ch 99H lu d liu truyn i v d liu nhn v. Vic ghi ln SBUF s np d liu
truyn v vic c SBUF s ly d liu nhn c.
Cc ch hot ng khc nhau c lp trnh thng qua thanh ghi iu khin
port ni tip SCON (serial port control register) a ch 98H, thanh ghi ny c
nh a ch tng bit.
B mn K thut my tnh
71
+ Cc thanh ghi ngt

8051 c mt cu trc ngt vi 2 mc u tin v 5 nguyn nhn ngt. (5 source, 2
priority level interrupt structure). Cc ngi b v hiu ho sau khi reset h thng v sau
c cho php bng cch ghi vo thanh ghi cho php ngt IE (interrupt enable
register) a ch A8H. Mc u thanh ghi c thit lp qua thanh ghi u tin ngt IP
(intenupt priority register) a ch B8H. C 2 thanh ghi ny u c nh a ch
tng bit.
+ Thanh ghi iu khin ngun
Thanh ghi iu khin ngun PCON (power control register) c a ch 87H cha
cc bit iu khin.
Bit SMOD tng gp i tc bang ca port ni tip. Khi port ny hot ng
cc ch 1, 2 hoc 3, cc bit 4, 5 v 6 ca PCON khng c inh ngha. Cc bit 2
v 3 l cc bit c a mc ch dnh cho cc ng dng ca ngi s dng.
Cc bit iu khin ngun, ngun gim PD v ngh IDL, hp l cho tt c chip
thuc h MCS-51, nhng ch c thc hin trong cc phin bn CMOS ca MCS-51.
TCON khng c nh a ch bit.
Ch ngun gim.
Lnh thit lp bit PD bng 1 s l lnh sau cng c thc hin trc khi i vo
ch ngun gim:
(1) mch giao ng trn chip ngng hot ng
(2) Mi chc nng ngng hot ng
(3) Ni dung ca RAM trn chip c duy tr
(4) Cc phn port duy tr mc logic ca chng
(5) ALE v PSEN gi c mc thp. Ch ra khi ch ny bng cch reset h
thng.
Trong sut thi gian ch ngun gim, Vcc c in p l 2v. Cn phi gi cho
V.cc khng thp hn sau khi t c ch ngun gim v cn phc hi Vcc bng
5V ti thiu 10 chu k dao ng trc khi chn RST t mc thp ln na.
Bit
K hiu
M t
SMOD
bit tng gp i tc bang, bit ny khi st lm cho

tc baud tng 2 cc ch 1,2 v 3 ca port ni tip
Khng nh ngha
Khng nh ngha
Khng nh ngha
B mn K thut my tnh
72
CFI
Bit c a mc ch 1
CFO
Bit c a mc ch 2
FD
Ngun gim; thit lp tch cc ch ngun gim,

ch ra khi ch bng reset
IDL
Ch ngh; thit lp tch cc ch ghi, ch ra

khi ch bng mt ngt hoc reset h thng.
Ch ngh.
Lnh thit lp bit IDL bng 1 s l lnh sau cng c thc thi trc khi i vo ch
ngh. ch ngh, tn hiu clock ni c kho khng cho n CPU nhng
khng kho i vi cc chc nng ngt, nh thi v port ni tip. Trng thi ca CPU
c duy tr v ni dung ca tt c cc thanh ghi cng c gi khng thay i.
Cc chn port cng c duy tr cc mc logic ca chng. ALE v PSEN c gi
mc cao.
Ch ngh kt thc bng cch cho php ngt hoc bng cch reset h thng. C
hai cch va nu u xo bit IDL.
+ B nh ngoi
Cc b vi x l h MCS-51 c kh nng m rng cc ti nguyn trn chip (b nh,
I/O, v.v...) trnh hin tng c chai trong thit k. Cu trc ca MCS-51 cho kh
nng m rng khng gian b nh chng trnh n 64K v khng gian b nh d liu
n 64K ROM v RAM ngoi khi cn thit.
Cc IC giao tip ngoi vi cng c th c thm vo m rng kh nng vo/ra.
Chng tr thnh mt phn ca khng gian b nh d liu ngoi bng cch s dng
cch nh a ch kiu I/O nh x b nh. Khi b nh ngoi c s dng, port 0 lm
nhim v ca port vo/ra. port ny tr thnh bus a ch (A0-A7)v bus d liu (D0D7) dn knh. Li ra ALE cht byte thp ca a ch thi im bt u mi mt chu
k b nh ngoi. Port 2 thng (nhng khng phi lun lun) c dng lm byte cao
ca bus a ch.
B mn K thut my tnh
73
(b) Multiplexed (16 pins)

Hnh II.32 a hp a ch (byte thp) v Bus d liu
(a) khng dn knh (24 chn), (b) dn knh (16 chn)
+ Truy xut b nh chng trnh ngoi
B nh chng trnh ngoi l b nh ch c, c cho php.bi tn hiu PSEN.
Khi c mt EPROM ngoi c s dng, c hai port 0 v port 2 u khng cn l cc
port vo/ra. Kt ni 8051 vi b nh ngoi EPROM c trnh by hnh II.33
Mt chu k my ca 8051 c 12 xung nhp. Nu b giao ng trn chip c tn s
12MHZ, mt chu k my di l sec. Trong mt chu k my in hnh, ALE c 2 xung
v 2 byte ca lnh c c t b nh chng trnh (nu lnh ch c mt byte, byte
th hai c loi b).
B nh d liu ngoi l b nh c/ghi c cho,php bi cc tn hiu RD v WR
cc chn P3.6. Lnh dng truy xut b nh d liu ngoi l: MOVX, s dng
hoc con tr d liu l6-bit DPTR hoc R0, R1 lm thanh ghi cha a ch.
B mn K thut my tnh
74
Hnh II.33 Kt ni 8051 vi b nh chng trnh ngoi

RAM c th giao tip vi 8051 theo cch nh EPRO ngoi tr ng RD ni vi
ng cho php xut (OE) ca RAM v WR ni vi ng ghi (W) ca RAM. Cc kt
ni vi bus d liu v bus a ch ging nh EPROM. Bng cch s dng cc port 0
v port 2, ta c dung lng RAM ngoi ln n 64K c kt ni vi 8051.
II.4.3 Lp trnh cho C8051
lp trnh cho 8051, ngi lp trnh cn nm tht vng cch t chc rt hu hiu
nhng tng i phc tp ca b nh RAM tch hp trong chip. Khng n thun
ng vai tr b nh d liu trong MCS51, n cn s dng mt phn b nh RAM
lm thanh ghi a nng v thanh ghi vi cc chc nng c bit.
Tn ti chng trnh Assembler ring cho h MCS51, lp trnh hp ng tng
ng nh lp trnh hp ng cho h 80x86. im mnh tng ng l tn ti mt phin
bn ngn ng C cho MCS51, to iu kin cho nhng ai quen vi lp trnh C c th
to cc phn mm ng dng ci t vo trong b nh ROM ca MCS51 i vi
nhng ng dng thc t
Bn c c th tham kho ti liu [1] v lp trnh cho C8051 c nu cui
cun gio trnh ny.
II.4.4 Cc kh nng ng dng ca C8051
Thng thng, cc trung tm Vi x l c dng xy dng nn cc my tnh.
Ring cc trung tm ca Single Chip Microcomputer, do nhng cu trc c trng v
tnh nng k thut, c ng dng nhiu trong cc thit k nh, vi s thnh phn ph
tr thm vo ti thiu nht. Nh cu trc v kh nng ci t cc chng trnh ng
dng ngay trong b nh ROM tch hp sn, cc hng v cc ng dng c th ca h
Vi x l ny ch yu tp trung vo cc mc ch gia dng v dn dng. Thng k mt
s lnh vc ng dng ca cc trung tm Vi x l h ny c lit k trong bng sau.
in gia dng
Thit b m thoi
in thoi
Trong gia
H thng an ton
n h
M ng ca
Tr li t ng My
FAX
Thit b vn in thot My tnh
phng
H thng an ton
My tnh gia nh
TV
Truyn hnh cp
VCR
Camera
iu khin t xa
Tr chi in t
My FAX L vi sng
PhotocoDV
T ng
ho
o lng Truyn tin...
My tnh hnh trnh

iu khin ng c
B mn K thut my tnh
Nhc c in t
My khu
iu khin nh sng
My nhn tin v v
My in Laze My in
mu My nhn tin
iu ho khng kh
v.v...
75
CHNG III. B NH TRONG CA H VI X L
III.1 B nh trong h Vi x l
B nh c s dng lu gi m lnh ca chng trnh v d liu cn x l. B
nh c ghp ni trc tip vi CPU qua BUS h thng v l ni u tin CPU truy
xut ti ly thng tin khi khi ng h thng. Yu cu t ra cho b nh l phi cho
php truy xut vi tc cao p ng kp thi cc i hi ca CPU. Ch c b nh
bn dn mi p ng c yu cu cao v tc truy xut cao (hng trm n hng
chc nsec).
B nh bn dn c chia ra hai loi: B nh ch c ROM (Read Only Memory)
v b nh truy xut ngu nhin RAM (Ran dom Access Memory).
III.1.1 Phn t nh, vi mch nh, t nh v dung lng b nh
a) Phn t nh
Phn t nh thng thng l mt mch in c th ghi li v lu gi mt trong hai
gi tr ca mt bin nh phn, hoc "0" hoc "1", tng ng vi khng c in p hoc
c in p, c gi l bit. Trn mch in di y (Hnh III. 1), trn dy D1 s
khng c in p (o cng tc m), trong khi dy D2 c in p (v cng tc ng, hay
thng qua diode mc theo chiu thun), gn bng gi tr ngun nui Vcc, tng ng
vi bit D1 = "0" v bit D2 = "1"
Phng php to phn t nh D1 = 0 v D2 = 1 bng mch in n gin
Hnh III.1 M phng phn t nh

Mch flip-flop RS (cn gi l triger RS) ng b l mt mch c kh nng lu gi
cc gi tr "0" hoc "1" li ra. C th dng RS flip - flop lm mt mch lu gi tn
hiu vo R bng cch cht d liu li ti u ra Q (hnh III.2a). Cc hng ch to
thc hin mch ny bng cng ngh cao, nn kch thc v cng nh, c th c hng
nhiu triu phn t nh trn mt din tch 1mm2. cc Vi mch nh thng thng c
ch to vi di t nh v s lng t nh c nh. S b nh c lin kt ti mt
v tr nh (c cng a ch) trong mt chip nh c gi l t nh ca chip nh,
thng c chn l 1, 4, hoc 8bit. to c mt t nh ca b nh, tc l t nh
c di (s bit trong mt t) chun (theo chun IBM l 8 bits), trong mt s trng
B mn K thut my tnh
76
hp nht nh cn phi tin hnh ghp cc chip nh li vi nhau.

Hnh III.2 a), b) v c) cho ta khi nim v kh nng to mt t nh c bn (byte)
khi t nh ca chip nh l 1bit, 2bits v 4 bits. Trong trng hp di t nh ca
chip nh l 8 bits, vic lin kt l khng cn thit.
Hnh III.2 a) Mch Flip-flop RS nh mt phn t nh gi tr nh phn

b) Chip nh RA v chip nh ROM
c) Chp cc chip nh c di t nh khc nhau to c
t nh c di 8 bit.
III.1.2. vi nt v b nh trong ca h Vi x l v my tnh PC
Do u im tng thch tuyt i v kch thc, tiu th nng lng thp v mc
logic, c bit l tc truy nhp, nn b nh bn dn c s dng lm b nh chnh
(Main Memory) trong cc h Vi x l cng nh trong cc my tnh PC, nhiu khi c
ghp ni ngay trong b mch chnh, hoc c thit k nh nhng v nh cm vo khe
cm ring trn b mch chnh.
Nh nhng tin b vt bc ca cng ngh vi mch, c bit l cng ngh cao
(Hight Technology) cc chip nh c ch to ngy cng nh v c dung lng tng
i ln, tc truy nhp rt cao v gi thnh thp. Hin c cc chip nh c dung
lng hng trm triu t nh, c cu thnh t hng chc t transistor trn mt mt
cu trc c 1mm2. B nh trong ca mt h Vi x l gm hai loi chnh:
B mn K thut my tnh
77
- B nh ROM - l b nh ch c (Read Only Memory), thng thng

cha cc chng trnh gim st (monitoring) cc hot ng chc nng ca
h Vi x l: chng trnh thit lp h thng, chng trnh vo/ra d liu
qun l v phn pht b nh, qun l cc thit b vo/ra v.v...i vi my
tnh PC, l chng trnh h thng vo/ra c s (BIOS - Basic Input
Output System). c im c bn nht ca b nh ny l s bo ton d
liu khi khng c ngun nui.
- B nh RAM - l b nh ghi/c tu tin (Random Access Memory).
V c kh nng ghi/c tu theo ngi dng, nn b nh ny c s dng
cha d liu, cc chng trnh ng dng nht thi ca ngi dng v.v...
Trong my tnh PC, b nh ny l ni chng trnh h iu hnh c np
khi khi ng my, hay ni cha cc chng trnh ng dng lc n c
thc thi. B nh ny b mt d liu khi b mt ngun nui.
Trong cc h Vi x l n gin, hai b nh ny thng c thit k v lp rp t
cc chip nh ring bit thnh mt v nh. a ch c gii m cho tng chip nh nh
khi gii m, thng thng l mt vi mch gii m hay c xy dng t cc mch t
hp logic. Cc tn hiu iu khin vic gh/c b nh do CPU cung cp. Mch triger
RS ng b l mt mch c kh nng lu gi cc gi tr "0" hoc "1" li ra. C th
dng RS flip-flop lm mt mch lu gi tn hiu vo R bng cch cht d liu li
ti u ra Q (hnh III.2)
B nh c xy dng t cc chip nh. Cc chip nh RAM (SRAM hoc DRAM)
thng c cc t nh c di 1 bit, 4 bits hoc 8 bits. T cc chip nh loi ny c th
xy dng c b nh vi mi nh cha c byte d liu (8 bits).
- Xy dng b nh vi cc chip SRAM
Gi s cn xy dng mt b nh kch thc 16kbyte trn c s cc chip SRAM
loi 16Kx1bit.
Bng nh SRAM 16kbyte c xy dng trn c s 8 chip SRAM loi 16Kxbit,
c c nh c di 8 bits (t nh c bn). lm c iu ny ngi ta sp
t 8 chip SRAM loi 16K x bit sao cho mi chip ti mt v tr xc nh s m nhim
lu tr bit d liu c trng s tng ng trong byte d liu.
Cu trc chip SRAM
B mn K thut my tnh
78
Hnh III.3. Chip nh RAM 64K bit (64K x 1)

Cc ng tn hiu:
A 13 A0 BUS a ch
- CS: Tn hiu chn chip. Nu CS = 0 th truy nhp c chip
- W/R: Tn hiu iu khin ghi/c. W-O iu khin ghi
DO - D7: Cc ng dy truyn cc bit d liu t D0 n D7.

Chu k ghi b nh SRAM:
B mn K thut my tnh
79
Hnh III.5 - Biu thi gn ghi c b nh

- T chc b nh vi DRAM
Cu trc ca chip DRAM:
Hnh III.6 Cu trc bn trong chip DRAM
DRAM dng phng php dn knh np ln lt (2 ln) a ch hng v a ch

ct vo m a ch.
Tn hiu iu khin:
+ RAS: khi RAS (Row Access Strobe) tch cc th a ch hng c np (cht
li):
+ CAS: khi CAS (Column Access Strobe) tch cc th a ch ct c np (cht
li).
+ WE: WE - "0" iu khin ghi chp, WE - "l" iu khin c chip.
Vic xy dng b nh t cc chip DRAM c thc hin gn tng t nh vi
SRAM.
III.1.3 Phn loi cc chip nh ROM, RAM
Cc chip nh ROM (Read Only Memory) c phn loi theo kh nng ghi c
nh sau:
B mn K thut my tnh
80
ROM, nh ch c, d liu trong chip nh loi ny c ghi ngay ti hng sn

xut chip nh theo n t hng ca cc nh sn xut thit b cn s dng n.
EPROM, chip nh ROM c kh nng xo ni dung v ghi li ni dung. Ni
dung c xo bng tia cc tm nh mt thit b chuyn dng.
EEPROM, chip nh ROM c kh nng xo, ghi li nh s dng xung in
Cc chip nh RAM ch yu c chia thnh 2 loi ch yu sau:
RAM tnh (SRAM), mi phn t nh l mt mch flip-flop trong qu trnh s
dng khng cn quan tm n vic d liu c lu gi nu khng b mt
ngun nui
RAM ng (DRAM), phn t nh dng cng ngh np in tch ln t in.
Trong qu trnh s dng cn thit mt ch lm ti
B mn K thut my tnh
81
Phn t RAM ng (Dynamic RAM) MOS 4 Transistors

Hnh III.7b S cu trc cc phn t nh
III.3 T chc b nh cho h Vi x l

III.3.1 T chc b nh vt l
T chc b nh cho mt h Vi x l (my vi tnh) ph thuc khng ch vo mt h
Vi x l c th, m cn ph thuc vo cch b tr thun li bn trong h thng. Trc
ht, hy lm quen vi cc khi nim chip nh v t nh phn tch vn t chc
vt l mt b nh, sau m rng khi nim t chc theo quan im ca ngi lp
trnh (t chc logic).
Cc chip nh c sn xut di nhiu kch c khc nhau, ph thuc vo cng
ngh ch to. Chip nh l mt vi mch c th, c b tr cc chn c bn nh Hnh
III.8 Cc chn ca mt chip nh thng thng gm cc li vo ca BUS a ch, li d
liu, cc chn iu khin chn chip, gh/c v cc chn ngun.
0 A9 Cc chn a ch
D1 D4 Cc chn d liu
CS
Chn chn chip
WE
iu khin Ghi/c
Vcc
Chn ngun nui +5V
GND Chn ni t
Hnh III.8 S ni chn mt vi mch nh

RAM 1kx4
B mn K thut my tnh
82
Tu theo tng chip, s lng chn a ch v s lng chn d liu c th khc

nhau ph thuc vo di t nh ca chip v dung lng ca chip nh. di t nh
ca chip nh c th l 1bit, 4 bits hoc 8 bits, trong khi s chn a ch c th t 10 tr
ln tu thuc vo dung lng ca chip nh. Trong trng hp di t nh ca chip
l 1 bit, ta cn phi ghp song song 8 chip to thnh 1 byte, ghp song song 16 chip
to mt t word - 2 bytes).
Hnh III. 8 To t nh 8 bit t cc cc chip nh c di t nh nh hn
III.3.2 Thit k v nh cho h Vi x l

Thit k v nh l mt vic rt quan trng v rt cn thit trong vic xy dng mt
h Vi x l. Cc v nh c thit k thng thng l EPROM, cc loi v nh RAM,
t cc chip nh c sn. Thng thng, cc chip nh c chn l nhng chip thng
dng trn th trng, c cc thng s k thut ch yu sau:
a. Dung lng nh ca chip nh tnh theo n v Kbyte
b. di t nh ca chip nh tnh theo s bits
c. Mt s thng s k thut khc nhu thi gian truy xut, cng sut tiu tn ca
chip v. v... Nhng thng s ny khng c nh hng ln n qu trnh thit k
v xy dng v nh.
Cc thng s c cho trc trong vic thit k mt v nh bao gm:
a. Loi chip nh v d dng EPROM 2764 (8kx8) hay RAM TMS 2064 (8kx8)
v.v...
b. Dung lng ca v nh l dung lng v nh phi c, v d 64KB, 128KB v.v...
c. a ch u ca vng nh v d v nh c a ch u l A0000H chng hn.
B mn K thut my tnh
83
V d minh ha: Dng EPROM 2764 (8kx8bit) xy dng v nh c dung lng

32KB, a ch u l 22000H.
Gii: Da trn yu cu ca ra, phi thc hin cc bc sau:
1. Xc nh s chip nh cn thit to t nh c bn ( di 8 bits), c th tnh
theo cng thc:
n=
8
trong : n l s chip cn to c t nh c bn
k
k l di t nh ca chip nh
Tn hiu chn v CS ca cc chip ny c ni chung vi nhau, cc chip ny c
coi nh mt chip lin thng, cc bit d liu s c nh v theo th t t D7: D0
tng ng vi cc bit t D7: D0 ca BUS d liu.
2. Xc nh s chip nh, hoc s chip lin thng to c dung lng nh theo
yu cu. Trong trng hp c th ca ra, cn 4 chip to c dung lng
nh 32KB. Tnh theo cng thc:
M =
Q
trong : Q l dung lng ca v nh
D
D l dung lng ca chip nh hoc dung lng ca

chip lin thng
M l s chip nh hoc s chip lin thng cn thit
3. Xc nh s dy a ch c s (tc l s dy a ch thp c ni trc tip vo
chip nh hoc chip lin thng): S dy a ch m ph thuc vo dung lng nh
ca chip nh hoc chip lin thng theo biu thc sau:
2m = D trong : D l dung lng ca chip nh
m l s dy a ch c s
4. T s chip hoc s chip lin thng, xc nh s dy a ch cn thit to cc
dy chn chip ring bit. Tnh theo cng thc:
2i = M
trong i l s dy a ch cn gii m xc nh cc tn
hiu chn chip cho cc chip nh hoc chip lin thng. M l
s lng chip hoc s lng chip lin thng. Xy dng
mch t hp to cc tn hiu chn chip CSi.
5. Cc dy a ch cn li c s dng to tn hiu xc nh vng nh ca,v

nh trong khng gian nh (c gn cho v nh theo a ch u ca v nh theo
yu cu).
B mn K thut my tnh
84
Hnh II.9 S ni chn chip nh ROM v chip nh RAM
S khi v nh nh sau, cc mch t hp logic xy dng theo kin thc hc

c mn hc K tht in t s.
Hnh II.10 S khi vi nh 32KB t cc chip ROM 2764
B mn K thut my tnh
85
CHNG IV. CC CHIP KH LP TRNH

(Programmable)
IV.1 Tng quan
Chip kh lp trnh (Programmable) l mt loi mch in t chuyn dng c kh
nng thc hin chc nng thng qua vic cung cp cc t iu khin (Control Word CW) c CPU gi ti (do ngi lp trnh son). Ni dung cc bit nh chc nng
trong t iu khin s iu khin mch lm vic theo nhng ch nh trc. Tn ti
mt s mch chc nng chuyn dng tiu biu cho cc h Vi x l P8085 v h cc
trung tm vi x l 80x86 nh mch phi ghp ngoi vi song song kh lp trnh
PPI8255 iu khin vic phi ghp vo/ra d liu song song gia CPU vi cc thit b
ngoi vi, mch m nh thi v to khong thi gian PIT8253/54, mch phi ghp
vo ra d liu ni tip USART 8251, mch iu khin ngt PIC8259 v.v... Phn tip
theo s tm hiu mt s mch tiu biu.
IV.2 Mt s mch chc nng tiu biu
IV.2.1 Mch vo/ra d liu song song PPI-8255 (Programmable Penpheral
lnterface).
a) Gii thiu chung
PPI8255 l mch giao din thit b ngoi vi kh lp trnh, c thit k lm vic
trong h thng vi tnh ca hng Intel. PPI8255 thc hin chc nng giao din song
song gia cc thit b ngoi vi v my vi tnh.
Cu hnh hot ng ca PPI8255 c th lp trnh c bng phn mm. PPI8255
thng c dng ch to cc mch vo/ra d liu s dng song song.
S khi cc thnh phn chc nng ca mch PPI8255 c th hin trn Hnh
IV.1, gm mt m BUS d liu, khi iu khin ghi/c, hai khi iu khin hai
nhm cng A v B, v cc cng 8bits PA, PB v PC.
m BUS d liu: l b m 8 bits hai chiu 3 trng thi. D liu c pht hoc
nhn qua b m ny. T iu khin v trng thi cng c truyn t CPU n
PPI8255 qua b m ny.
Logic iu khin v ghi/c: logic iu khin v ghi/c qun l ton b cc qu
trnh truyn d liu v iu khin cc cng PA, PB, PC. Cc tn hiu iu khin t
CPU. Tn hiu c RD, tn hiu ghi WR v tn hiu ti thit lp theo mc nh RST.
RST - Reset: tn hiu RST t tt c 3 cng A, B, C ch u vo
Cc tn hiu RD , RW , Al, A0:
a ch A0, Al phi hp vi tn hiu RD. WR iu khin vic ghi/c i vi 3
cng A, B, C:
B mn K thut my tnh
86
Cc cng PA, PB v PC: cc cng PA, PB v PC l cc cng vo/ra d liu loi 8

bit. Chc nng ca tng cng c xc nh bng phn mm (bng t iu khin).
Cng A: l cng ra 8 bit c cht d liu hoc l cng vo 8 bit.

Cng B: l cng ra 8 bit c cht d liu hoc l cng vo 8 bit.
Cng C c chia thnh 2 phn:
4 bit cao (PC7. PC4) cng vi cng A lm thnh nhm A.
4 bit thp (PC3: PCO) cng vi cng B lm thnh nhm B.
Tu theo ch hot ng (c xc lp thng qua t iu khin) m hai phn ny
c th thc hin chc nng vo/ra d liu 4 bit hoc nhn/pht tn hiu bt tay cho
tng nhm tng ng
Mch PPI8255 c 3 ch lm vic
Ch 0: vo/ra c bn
Ch 1: vo/ra c xung cht d liu
B mn K thut my tnh
87
Ch 2: vo ra hai chiu (ch cho nhm A)

b) Ch lm vic v t iu khin
Hnh IV.2 Cu trc t lch ca PPI 8255
C th chn v t li ch lm vic ca PPI8255 qua cc t iu khin.

Khun dng t iu khin ch lm vic c m t trn hnh IV.2.
+ Ch 0: vo/ra c bn, r c cht, vo khng cht d liu.
T iu khin:
1
0
0
Tnh cht c bn ca ch 0:
1/0
- Hai cng 8 bit

- Hai cng 4 bit
- Ra c cht
- Vo khng cht
- Cho php chn v dng 1 trong 16 cu hnh cng vo/ra
Khi t t iu khin #0, l 10000000, cu hnh cc cng ca 8255 c t nh
sau:
Tt c cc cng u ch Output nh hnh v
B mn K thut my tnh
88
Khi t t iu khin #3, l 10000011, cu hnh cc cng ca 8255 nh sau
+ Ch 1: vo/ ra d liu c xung cht d liu.

c tnh ca ch 1: c hai nhm A v B, mi mt nhm c mt cng vo/ra 8
bit v mt cng iu khin 4 bit.
Cu hnh cng vo d liu (ch 1):
T iu khin:
Cc tn hiu iu khin:
STRA / STRB : mc tch cc thp cht d liu vo 8255
IBFA/IBFB (Input Buffer Full): mc tch cc cao bo d liu c cht trong

8255
INTRA/INTRB (Interrupl Request): yu cu ngt
INTEA v INTEB (Interrupt Enable): c t/xo (1/0) bi bit PC4 v PC2
B mn K thut my tnh
89
Cu hnh cng ra d liu (ch 1)

T iu khin:
Cc tn hiu iu khin:
OBFA / OBFB (Output Buffer Full): tn hiu ra, mc tch cc thp khi c d liu ra
cc cng A/B.
ACKA / ACKB (Acknowledge): tn hiu vo, sc tch cc thp, bo 8255 l d liu
ra cng A/B c nhn.

INTRA/INTB: yu cu ngt, yu cu a d liu (tip theo) ra 8255 theo tn hiu
bo ngt ny.
+ Ch 2: Vo/ ra hai chiu c xung cht d liu (ring cho nhm A)

c tnh ch 2; ch c dng cho nhm A. Cng A l cng vo/ra 8bit hai
chiu. Cng C c 5 bit c dng lm cc tn hiu iu khin bt tay. Vo ba d liu
u c cht.
Kh nng ng dng: ch 2 cung cp cng c truyn tin vi thit b ngoi vi theo
cch pht v nhn d liu 8 bit song song trn cng mt ng BUS. Qu trnh truyn
tin thuc kiu khng ng b. Cc tn hiu bt tay STB, IBF, OBF, ACK c dng
B mn K thut my tnh
90
phi hp vic truyn d liu gia my tnh v thit b ngoi vi.

Cc bit ca cng C c th c thit lp ln "1" (st) hay v "0" (reset) bng cch
ghi t iu khin vi D7 = 0, Vic Chn bit cn SET hay RESET qua chn bit D0 =
"1" hoc "0" v v tr ca bit cng C thng qua cc bit D1, D2 v D3 nh sau: 000 = bit
PC0, 001 = bit PC1... v 111 = bit PC7
0
x
x
x B2 Bi
IV.2.2 Mch iu khin ngt PlC-8259
Bo s
CPU c thit k p ng c vi cc qu trnh ngt cng. CPU c mt u

vo nhn tn hiu ngt INT, khi nhn c tn hiu ny CPU s phn ng theo c ch
ngt cng.
Hnh IV.3 - S ghp ni PIC8259 trong h Vi x l

Trong thc t c nhiu thit b ngoi vi yu cu c phc v theo phng php
ngt cng (bn phm, ng h h thng, my in, v.v.) v sinh ra nhiu yu cu ngt, do
vy cn c mt b iu khin gip CPU qun l v phc v cc yu cu ngt, l b
iu khin ngt PIC8259 (Programmable Interrupt Controller).
Cu trc h thng ngt cng:
H thng ngt cng c xy dng trn c s 2 b iu khin ngt PIC 8259, mi
PIC 8259 c th nhn 8 tn hiu yu cu ngt IRQ t thit b vo/ra. Hai PIC ny c
kt ni vi nhau theo kiu ghp tng, kt hp hot ng c th phc v c 16 yu
cu ngt IRQ.
Chc nng c bn ca PIC 8259: PIC 8259 l mt vi mch in t kh trnh c
thit k gip CPU thc hin qu trnh ngt cng. PIC 8259 thc hin cc chc nng
sau:
- Ghi nhn c 8 yu cu ngt IRQI, i=o,l,...,7.
- Cho php chn v phc v cc yu cu ngt theo mc u tin.
B mn K thut my tnh
91
- Cung cp cho CPU s ngt tng ng vi yu cu ngt IRQI. S ngt ny i

din cho a ch ca chng trnh con phc v thit b yu cu ngt IRQI.
- Cho php hoc khng cho php cc yu cu ngt IRQI kch hot h thng ngt.
a) Thit b iu khin ngt PIC 8259 v c ch hot ng ca h thng ngt cng
Cu trc bn ngoi ca PIC 8259:
Cu trc bn trong ca PIC 8259:

Cc khi chc nng:
- IRR (Interrupt Request Register - Thanh ghi yu cu ngt): l thanh ghi 8 bit.
IRR cha (ghi nhn) tt c cc yu cu ngt
- IRQI i phc v. Nu tn hiu IRQi = "1" th bit IRRI tng ng c t bng "1".
- PR (Priority Resolver- B gii quyt u tin): l thanh ghi 8 bit. PR cho php xc
lp mc u tin ca cc yu cu ngt. Ngt c u tin cao nht c chn v t vo
bit tng ng trong ISR trong chu k INTA.
B mn K thut my tnh
92
- ISR (In Service Register - Thanh ghi ngt ang c phc v): l thanh ghi. 8 bit.
ISR ghi nhn cc ngt ang c phc v. Yu cu ngt IRQI no ang c phc v
th bit ISRI tng ng c t bng "l".
- Khi logic iu khin: khi logic iu khin a ra tn hiu INT, c ni thng
vi chn INT ca CPU. Khi INT c mc cao l i CPU phc v ngt. Khi logic
(iu khin nhn tn hiu INTA t CPU. Khi nhn c tn hiu INTA, PIC 8259 s
cung cp s ngt ra BUS d liu cho CPU.
- Khi m BUS: l loi 8 bit, 2 hng, 3 trng thi. Cc t iu khin ICW, OCW
c a vo PIC 8259 qua khi ny xc lp ch hot ng ca 8259. S ngt
v trng thi hot ng ca PIC cng c a ra BUS d liu qua khi ny.
- Khi ghp tng
- PIC 8259 c c cu cho php ni ghp tng cc PIC 8259 vi nhau v phi hp
hot ng ca cc PIC ny. Tng th nht c u ra INT ni trc tip vi CPU, gi l
PIC 8259-ch. u vo IRQI ca PIC ch c ni vi u ra INT ca PIC 8259 th
hai. PIC ny c gi l PAC 8259-th. C ch ghp tng cho php xy dng mt h
thng ngt cng qun l c n 64 yu cu ngt IRQ.
Khi logic ghi/c v gii m: thc hin gii m cc t iu khin ICW
(Initialization Command Wora - T iu khin khi ng) v OCW (Operation
Command Word - T iu khin hot ng). Qua hai loi t iu khin nay ngi s
dng c th lp trnh xc lp ch hot ng cho PIC.
- Thanh ghi IMR: l thanh ghi 8 bit, cha mt n ngt.
Bng cc tn hiu CS, A0, RD, WR, v cch ghi/c PIC 8259.
CS
A0
RD
WR
D4
D3 Hng thng tin
IRR, ISR => BUS
0
0
1
0
0
1
1
D
x
0
x
0
(IMR) = OCWI -> BUS

BUS => OCW2
BUS => OCW3
0
0
0
1
1
1
0
0
1
x
x
x
BUS => ICW1

BUS => ICW2, ICW3, ICW4, OCWI
b) C ch hot ng ca h thng ngt cng:

iu kin ban du: PIC 8259 cn c lp trnh khi ng qua cc t iu khin
ICW. Sau khi cc t iu khin ICW c np th PIC 8259 sn sng hot ng.
- Mt hoc nhiu thit b vo-ra c yu cu c phc v pht tn hiu IRQI = "1"
(mc tch cc) cho PIC. PIC ghi nhn cc yu cu ngt IRQI ny bng cch t cc bit
IRRI tng ng ln - PIC 8259 chn IRQI c mc u tin cao nht phc v. PIC
gi tn hiu INT cho CPU, i CPU phc v.
B mn K thut my tnh
93
- CPU thc hin cc thao tc sau:

Thc hin nt lnh ca qu trnh hin hnh.
Lu a ch tr v (ni dung ca cc thanh ghi CS, IP) v thanh ghi c
FLAGS vo ngn xp.
Gi hai tn hiu tr li ngt INTA cho PIC.
Khi PIC 8259 nhn c tn hiu INTA th 1: bit ISRI ng vi IRQI c mc u
tin cao nht c thit lp (ISRi=1) v bit IRRI tng ng b xa (IRRI=0). Trong
chu k INTA th nht ny PIC 8259 khng gi g cho CPU qua BUS d liu.
- Khi PIC 8259 nhn c tn hiu INTA th 2: PIC 8259 gi s ngt tng ng
vi IRQI ang c phc v qua BUS d liu cho CPU.
- CPU nhn s ngt v trn c s s ngt ny vo v tr tng ng trong Bng vc
t ngt xc nh a ch ca chng trnh phc v ngt. CPU np a ch chng
trnh phc v ngt vo cc thanh ghi CS v IP v bt u thc hin chng trnh phc
v ngt ny.
Khi thc hin xong chng trnh phc v ngt th qu trnh phc v ngt ca CPU
cng kt thc. H thng ngt cng c th kt thc phc v ngt hin thi theo hai ch
:
Kt thc ngt bnh thng EOI (End Of Interrupt): khi PIC c t ch
kt thc ngt bnh thng EOI th CPU phi pht lnh bo kt thc ngt
EOI (qua OCW2) cho PIC trc khi ri khi chng trnh con phc v
ngt. Khi bit ISRI ca ngt ang c phc v s c t xung 0.
Kt thc ngt t ng AEOI (Automatic EOI): khi ' PIC c t ch kt
thc ngt t ng AEOI th ti chu k INTA th 2 bit ISRI ca ngt ang
c phc v s c t xung 0.
Bng cc cch ni trn h thng ngt cng c th tip tc phc v yu cu ngt ny
nhng ln tip theo.
c) Lp trnh khi ng PIC 8259 v cc t iu khin khi ng ICW
B mn K thut my tnh
94
Cn xc lp ch lm vic ca PIC 8259 trc khi s dng. Qu trnh ny c

gi l lp trnh khi ng thit b. Vic lp trnh khi ng PIC 8259 c thc hin
qua cc t iu khin ICW v theo lu sau: Cc bit D5 - D7 khng dng cho CPU
x86.
IC4 (bit D0): Cho bit c cn ICW4 ?
IC4 = 0: khng cn ICW4.
IC4 = 1: c ICW4.
x
LTIM
ADI
SNGL
l041
+ SNGL (Bit D1): cho bit h thng ngt ch c mt PIC hay c nhiu PIC ghp
tng.
SNGL = 0 c ghp tng
SNGL = 1 ch c mt PIC 8259
+ ADI (bit D2): khng dng cho h CPU x86
+ LTIM: xc nh dng tn hiu IRQ
LTIM = 1 IRQ phi l tn hiu mc TTL
LTIM = 0 IRQ phi l tn hiu dng sn xung.
+ D4 = 1
+ D5 = D6 = D7 = 0
a- ICW2:
B mn K thut my tnh
95
ICW2 nh ngha s ngt nn cho 7 s ngt cn li.

1 T7
T6
T5
T4
T3
Cc bit T7 - T3 l 5 bit cao ca s ngt, 3 bit cn li lin quan n cc u vo

IRQi.
Nm bit cao T7 - T3. (do ngi s dng ty chn) cng vi 3 bit thp nht bng 0
xc nh s ngt nn. Da trn s ngt nn ng vi IRQO ny, PIC 8259 t to ra cc
s ngt tip theo tng ng vi cc IRQI n IRQ7
V d: h thng ngt cng ca my vi tnh PC, cc s ngt do PIC 8259-ch cung
cp nh sau:
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
..
0
0
0
0
1
1
1
1
- Icw3: lin quan n ghp tng.
ng vi IRQ0
ng vi IRQ1
ng vi IRQ7
Mch phn cng c chn SPIEN xc nh ch/th ch ghp tng: nu SP = 1

th PIC l ch, nu SP = 0 th PIC l th.
C hai loi ICW3
- ICW3 cho PIC ch: xc nh u vo IRQI nhn tn hiu INT t PIC th th i.
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Nu Si = 1 bo c PIC th ni vo chn IRQI ca ch
- ICW3 cho PIC th: xc nh a ch (ch th nhn dng) ca PIC th.
ID2
ID1
IDO
Cc bit ID2, ID1, ID0 xc nh a ch ring ca cc PIC 8259-th. Khi nhn c

tn hiu INTA2, PIC 8259-th so snh cc tn hiu CASO CAS2 (pht ra t PIC 8259ch) vi ID2 - IDO, nu chng ging nhau th PIC 8259 - th gi s ngt ln BUS d
liu cho CPU, ngc li th khng gi.
ICW4:
D7
D6
D5
D4
D3
D2
D1
SFNM BUFF M/S AEOI
D0
P
+ Bit p: bo cho PIC 8259 bit phi lm vic v h vi x l no.

p = 1: lm vic vi h x86
p = 0: lm vic vi h 8085
+ Bit AEOI: xc lp ch kt thc ngt.
AEOI = 0: kt thc bnh thng EOI
B mn K thut my tnh
96
AEOI = 1: kt thc t ng AEOI

+ Bit BUFF: bo ch c b m BUS
BUFF = 1: PIC lm vic ch m BUS, lc ny tn hiu SP/EN ch ra v
vic nh ngha ch/th c xc nh bng bit M/S.
+ Bt M/S: xc nh ch/th
M/S = 1: PIC l ch
M/S = 0: PIC l th.
Nu BUFF = 0 th M/S khng c ngha.
+ Bit SFNM: bit ny c t bng 0 ngay khi khi ng h thng. Kiu u tin
c nh l mc nh, trong IRQO c mc u tin cao nht, IRQ7 c mc u tin
thp nht. C th thay i kiu u tin bng t iu khin OCW2. Trong kiu u tin
c nh, khi SFNM = 0, khi bit ISRI = 1 th tt c cc IRQI c mc u tin thp hn
u b cm. Ch c cc IRQI c mc u tin cao hn c php gy ngt chng trnh
phc v ngt hin thi.
d) Cc t iu khin hot ng OCW
Cc t iu khin OCW c dng xc lp cc ch lm vic c th trong qu
trnh hot ng ca PIC 8259. C th gi.cc t OCW ny cho PIC8259 vo bt k lc
no sau khi khi ng h thng ngt.
+ OCWI: cho php hoc cm nhn mt yu cu ngt IRQi no bng mt n
ngt.
+ Vi PIC ch: a ch thanh ghi cha OCW 1 l 2 1H Vi PIC th: a ch thanh
ghi cha OCWI l AIH
D7
D6
D5
D4
D3
D2
D1
D0
M7
M6
M5
M4
M3
M2
M1
M0
Mi bit Mi tng ng vi IRQI

Khi Mi = 1 mt n ngt c t, cm PIC nhn IRQi (Cm IRQI gy ngt)
Khi Mi = 0 mt n ngt c xo, cho php PIC nhn IRQI (cho php IRQI gy
ngt)
H iu hnh t mt n che chn cc IRQ m h thng cha dng n.
+ OCW2: dng i kiu u tin v bo kt thc ngt EOI.
PIC cho php chn mt trong ba ch u tin:
u tin c nh: IRQO c mc u tin cao nht, IRQ7 c mc u tin thp nht.
Trong ch ny IRQ mc cao c quyn ngt chng trnh phc v ngt c mc u
tin thp hn.
B mn K thut my tnh
97
u tin quay vng: IRQI no va c phc v th bit ISRI s b xo xung 0 v

t ng c mc u tin thp nht. iu ny thc t to ra cc mc u tin bng
nhau.
u tin c bit: ngi lp trnh c th thay i mc u tin bng chng trnh.
Nu cc bit trong OCW2 R=1, S1=l th cc bit L2-L0 s t IRQn xung mc thp
nht v IRQn+l ln mc cao nht.
Du ch thanh ghi cha OCW2: 20H (PIC ch), A0H (PIC th)
+ OCW3 cho php t/c ISR v cc thanh ghi khc ca PIC 8259.
ESMM =l v SMM cho php t/xo ch mt n c bit. Ch mt n c
bit ny ch cm mt IRQ v cho php tt c cc IRQ cn li c yu cu ngt.
- D4 = 0, D3 = 1
- Bit P: cho php PIC 8259 lm vic vi CPU ch hi p, khng cn qua cc
tn hiu INTR, INTA. Nu P=l th PIC coi tn hiu iu khin c RD nh l tn
hiu INTA.
- Cc bit RR v RIS:
RR 1 & RIS = 0: bo s c IRR lnh c tip sau
RR = 1 & RIS = 1: bo s c ISR lnh c tip sau.
e) Phn b chc nng cc yu cu ngt v s ngt trong my PC.
PIC 8259-ch:
PIC 8259-ch chim hai. a ch cng: 20H, 21H
PIC 8259-th:
PIC 8259-th chim hai a ch cng: A0H, AIH
IRQi
IRQ0
s ngt
08H
B mn K thut my tnh
Thit b yu cu ngt
B to xung nhp ng h h thng
98
IRQ1
09H
Thit b giao din bn phim
IRQ2
0AH
PIC 8259-th
IRQ3
0BH
Thit b giao din vo/ra ni tip 2 (COM 2)
IRQ4
0CH
Thit b giao din vo/ra ni hp 1 (COM 1)
IRQ5
0DH
D phng
IRQ6
0EH
Thit b giao din a mm FDC
IRQ7
0FH
Thit b giao din vo/ra song song (LPTI)
Dy IRQ s ngt
IRQ8
70H
Thit b yu cu ngt
ng h thi gian thc
IRQ9
71H
D phng
IRQ10
72H
Card m thanh
IRQ11
73H
Thit b giao din vo/ra USB
IRQ12
74H
Thit b giao din chut PS/2
IRQ13
75H
B ng x l x87
IRQ14
76H
B iu khin BUS IDE 1 (primary)
IRQ15
77H
B iu khin BUS IDE 2 (secondary)
IV.3.3 Mch m nh thi a nng PlT-8253 (Programmable lnterval Timer)

Vi mch PIT-8253 l mch m nh thi, to xung c rng thay i a nng v
thu thp tn hiu dng xung, c thit k s dng vi h vi x l dng Intel. Mch
8523 thc hin c nhiu chc nng. Cc chc nng c xc nh bng phn mm
thng qua t iu khin.
Cc chc nng chnh ca PIT-8253:
-
To khong thi gian chnh xc
Pht xung vi tn s lp trnh c
m s kin
Chia tn s
ng h thi gian thc
Pht xung n
B mn K thut my tnh
99
Hnh IV.4 - S cu trc bn trong PIT-8255

m d liu: l b m 8 bit, hai chiu, 3 trng thi, c s dng giao din vi
BUS ca my tnh.
Logic c/ghi: logic Ghi/c nhn cc tn hiu t h thng BUS, t iu khin
vic truy nhp cc thanh ghi ca PIT-8253.
Thao tc chn b m v ghi/c b m:
A1
A0
RD
WR
cng vic c thc hin
Np b m C#O
Np b m C#1
Np b m C#2
Ghi t iu khin
c b m C#O
c b m C#1
c b m C#2
Thanh ghi iu khin: thanh ghi iu khin nhn t iu khin xc nh ch

hot ng cho PIT-8253.
B m C#O, C# 1, C#2:..
Mch PIT-8253 c 3 b m, mi mt b m l loi 16bit, m li t khi ng
li. Mi mt b m c th c lp trnh v hot ng c lp. C th c ni dung
ca tng b m ngay trong khi ang hot ng. Bng t iu khin c th chn ch
lm vic cho cc b m (6 ch ).
1. T iu khin.
Tng b m ca PIT-8253 c th c lp trnh hot ng c lp bng cch ghi
t iu khin vo thanh ghi t iu khin (A0=1, A1=1).
B mn K thut my tnh
100
Khun dng t iu khin.

DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
SCSCI SCSC0 RLRL RLRL0 MM2
MM1
MM0 BCDCD
SC (Select Counter): chn b m.

SC1
SC0
0
0
B m 0
0
1
B m 1
1
0
B m 2
1
1
Khng hp l
RL (Read/Load): Xc nh c/np b m.
RLRL0
c hoc np Byte cao
0
Thao tc cht b m. Cho php c ni
dung b m trong qu trnh m
1
0
c hoc np Byte cao
0
1
c hoc np Byte thp
1
1
c hoc np Byte thp trc, Byte cao sau
M (Mode): ch lm vic
RLRL0
0
M
0
0
x
x
1
1
M
0
0
1
1
0
0
M
0
1
0
1
0
1
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
BCD: kiu m m
BCD Kiu m m
0
M nh phn 16 bit
1
M BCD (4 ch s BCD)
Np ni dung b m: thanh ghi m ch c np khi c hai byte gi tr m c
ghi.
2. Th tc xc lp ch lm vic cho b m.
B mn K thut my tnh
101
3. Cc ch lm vic
Ch lm vic xc nh cch p ng ca u ra Output i vi u vo l dy
xung CLK v tn hiu Gate.
B m thc hin m lng chu k xung tnh t na thp ca chu k u tin
C 6 ch lm vic.
a. Ch O:
To khong thi gian tr xc nh v t u ra Output = "1" khi kt thc m.
u Output = "0" ngay sau khi chn ch .
Ngay sau khi s m c np th bt u m. iu kin lm vic l Gate = "1"
Khi kt thc m th Output = "l" v gi nguyn cho n khi c np li.
Vic np li s m gy ra hai s kin:
+ Ghi byte u tin lm dng m.
+ Ghi byte th hai lm khi u ln m mi.
b. ch 1
To xung n c rng xc nh...
u ra Output = "0" khi GATE = "1" v bt u m.
Output = "1" khi kt thc m.
Vic np li s m trong khi Output = "0" khng lm nh hng ti rng xung
u ra.
Vic m c khi u li (xung Output b ko di) nu GATE = "0" v sau
GATE = "l".
c. Ch 2
B chia tn - pht xung.
B m c dng nh mt b chia tn. Ni b m c np xc nh h s chia.
Chu k dy xung u ra, tnh t mt xung u ra Output = "0" n mt xung Output =
"0" tip theo ng bng s lng xung vo CLK.
B mn K thut my tnh
102
iu kin lm vic l GATE - "1".

rng mc "0" ca xung ra ng bng chu k T ca xung CLK.
C th dng tn hiu GATE ng b qu trnh m - pht xung.
d. ch 3
B chia tn - pht xung vung.
Lm vic ging ch 2, ch khc ch l rng mc "0" bng rng mc "1".
iu kin lm vic l GATE = "1".
e. Ch 4
To xung cht bng phn mm.
Sau khi t ch lm vic th Output = "1".
Sau khi s m c np th bt u m. iu kin lm vic l u ra Output =
"0" khi kt thc m, rng xung u ra bng rng chu k xung CLK.
Vic np li s m trong khi m lm khi ng li vic m.
f. Ch 5
To xung cht bng phn cng.
Sau khi t ch th Output ="1".
Bt u m khi GATE = "1". u ra Output = "0" khi kt thc m, rng xung
u ra bng rng chu k xung CLK.
MODE O: Interrupt on Terminal Count with GATE = 1
MODE l: Programmable One-shot.
B mn K thut my tnh
103
MODE 2: Rate Generator. (with GATE=1)
MODE 3: Square Wave Generator (with GATE=1)
MODE 4: Software Triggered Strobe (with GATE=1)
MODE 5: Hardware Triggered Strobe
B mn K thut my tnh
104
4. Kh nng c ni dung b m trong khi m (c trong khi m).

thc hin c thao tc c trong khi m th cn np t iu khin c bit
vo thanh ghi c a ch A1, A0 = 11.
D7
SC1
SC1, SC0:
D6
D5
D4
D3
D2
D1
D0
SC0
0
0
x
x
x
x
B m c chn t ch c trong khi m.
D5, D4:
(00, M xc nh ch c trong khi ghi)
Khng tc ng
IV.4.4 Mch iu khin vo/ra ni tip ng b/d b USART-8251 (Untversal

Synchronous/Asynchronous Receiver Transmitter).
USART-8251 l mt mch giao din vo/ra kh lp trnh ca hng Intel. Cc tnh
nng ch yu ca mch bao gm:
-
Hot ng mt trong hai ch ng b hoc khng ng b
Hot ng ng brvi m 5 - 8 bits, k t ng b ni b hoc t bn ngoi,

c ch ng b t ng.
B mn K thut my tnh
105
Hot ng khng ng b vi m 5 - 8 bits, h s xung nhp 1, 16 hoc 64 ln tc

Baud, to k t tm dng; vi 1,1 - v 2 bits Stop, pht hin li bit Start v k t
Break (tm dng) - Kh nng t pht hin li thu pht.
- Tng thch hon ton vi cc chip h 80x86
Mch USART 8251 c thit k cho mc ch trao i d liu ni tip gia CPU
v cc thit b ngoi vi. Ngi lp trnh c th chn cc phng thc thu/pht d liu
ng b hoc khng ng b, chn tc thu/pht ph hp thng qua cc t iu
khin (Control Wora - Cw). Bn thn USART thc hin cng vic chuyn i d liu
t CPU thnh d liu ni tip gi ra thit b ngoi vi, ng thi, mch cng t
chuyn d liu ni tip thu nhn c thnh d liu song song chuyn cho CPU.
Chc nng ca USART 8251 l lm trung gian cho vic giao tip vi thit b ngoi vi
(interfacing) bng thu/pht d liu ni tip, cn bn thn d liu trao i gia CPU v
USART 8251 vn l giao din song song.
a) M t chc nng.
Cng nh cc mch chc nng khc trong h thng 80x86, cu hnh chc nng ca
mch USART-8251 rt uyn chuyn nh c thit lp bng phn mm. Trong mi
trng trao i d liu, giao din ni tip thc hin vic bin i d liu sng
song ca h thng thnh dng d liu ni tip gi i v bin dng d liu ni
tip thu nhn c thnh d liu sng song CPU c vo. Tt nhin, khi thc
hin cng vic bin i, USART-8251 s t ng b i hoc thm vo cc bit hoc
k t ng nht chc nng trong k thut thu pht thng tin. Chnh nh vy, giao din
B mn K thut my tnh
106
gia CPU v USART-8251 l hon ton minh bch, ch n thun l gi i hay nhn
v mt byte d liu.
+ m BUS d liu:
L b m 3 trng thi hai chiu vi rng 8 bits dng lm giao din gia CPU
v mch 8251. D liu c gi i hay nhn v qua b m khi thc hin lnh INPut
hay lnh OUTput trong CPU. Cc t lnh (Command Word), t iu khin (Control
Word) hay thng tin trng thi cng c chuyn qua thanh m d liu. Thanh ghi
trng thi lnh (Command Status Register), thanh ghi d liu ra (Data Out Register) v
thanh ghi d liu vo (Data In Register) l nhng thanh ghi c lp v cng c kt
ni BUS d liu ca h thng thng qua m d liu.
+ RESET:
Mc "1" logic u vo ny a 8251 v ch ngh. Ch ny tn ti cho n
khi mt chui t iu khin, t lnh mi c gi ti 8251 xc nh ch lm
vic. Mc "1" ny phi tn ti trong khong thi gian ngn nht ca 6 chu k xung
nhp h thng.
+ CLK (Clock):
L u vo xung nhp cho 8251 lm vic. Tn s xung nhp ny phi ln hn ti
thiu 30 ln so vi tc thu/pht ca 8251.
+ WR (ghi):
Mc "0" logic xut hin u vo ny l xung iu khin t CPU trong vic ghi t
iu khin hoc gi d liu cho 8251.
+ RD (c):
Mc "0" logic xut hin u vo ny l xung iu khin t CPU trong vic c
trng thi ca 8251 hoc c d liu t 8251 vo CPU.
+ C/D :
u vo iu khin, kt hp vi cc tn hiu vo gm CS , WR v RD xc nh
cho 8251 d liu tn ti trn BUS l k t d liu, t iu khin hay thng tin trng
thi. "1" ng vi CONTROL/STATUS, "0" ng vi DATA.
C/D
RD
WR
CS
8251 DATA
DATA BUS
DATA BUS
8251 DATA
STATUS
DATA BUS
DATA BUS
CONTROL
DATA BUS
TRI-STATE
DATA BUS
TRI-STATE
B mn K thut my tnh
Lu : Chn C/D thng c

ni vi dy a ch Ao ca BUS a
ch. do vy c th d dng phn bit
hai a ch duy nht ca 8251 l: a
ch nn l a ch c hoc ghi d
liu. a ch nn + 1 l a ch cho
ghi t iu khin v c trng thi.
107
+ CS (Chip Select):
Tn hiu chn v i vi 8251. Mc "0" l tch cc, chip 8251 c chn. Khi CS
= "1", cc tn hiu c ( RD ) v ghi ( WR ) khng c tc ng i vi 8251.
+ Modem Control:
Vi mch 8251 c mt tp tn hiu vo/ra c th s dng n gin ho vic phi
ghp vi cc MODEM. Cc tn hiu do khi chc nng iu khin Modem to ra
nhm mc ch hon ton tng thch vi cc tn hiu iu khin trao thng tin thng
qua thit b Modem khi cn thit. l cc tn hiu DSR (Data Set Ready), DTR Data
Tenninal Ready), RTS (Request To Send), v CTS (Clear To Send).
+ m pht (Transmitter Buffer):
m pht tip nhn d liu song song t m d liu, chuyn i thnh chui bits
ni tip, chn thm cc k t hoc cc bit thch hp cn thit trong k thut truyn tin
v gi chui bits ny.ra u pht TxD theo sn xung ca xung nhp pht TXC. Khi
pht bt u cng vic ngay khi tn hiu CTS = "0" v dng lp tc vi trng thi
c gi nguyn khi TXE l "0" hay CTS = "1".
+ iu khin pht (Transmitter Control):
Khi iu khin pht gim st ton b mi hot ng lin quan n truyn d liu
ni tip. Khi c nhim v chp nhn v to ra tt cc cc tn hiu tng ng thc
hin vic tuyn d liu.
+ TxRDY (Transmitter Ready):
Tn hiu ra ca 8251 thng bo cho CPU bit n sn sng nhn d liu tuyn i.
Tn hiu ny c th s dng lm tn hiu yu cu ngt i vi h thng, v khc vi tn
hiu TXE (Transmitter Empty); Trong ch pht c thm d, CPU c th thng qua
tn hiu TxRDY quyt nh chuyn d liu cho 8251. Tn hiu ny b Reset bi tn
hiu WR khi d liu c gi ti 8251 t CPU.
Lu rng, trong ch pht theo thm d, tn hiu TxRDY khng b rng buc
bi tn hiu TXE, n ch c tc dng thng bo trng thi y hay rng ca thanh ghi
m pht.
+ TXE (Transmitter Empty):
Khi 8251 chuyn xong mt k t. "khng cn g pht i", u ra TXE s
chuyn i ln mc "1" logic. C th thng qua tn hiu ny bit c trng thi kt
thc truyn ca 8251, c bit trong ch half- duplex.
Trong ch thu pht ng b gi tr "1" u ra ny ch ra rng cha c d liu
c truyn i, k t SYNC hoc l k t d liu sp sa c truyn. TXE khng
B mn K thut my tnh
108
thay i mc khi k t SYNC bt u c gi i.

+ TxC (Translmtter Clock):
Xung nhp pht iu khin tc truyn cc k t ch thu pht ng b, tc
Baud Rate (IX) bng chnh tn s TxC . Trong ch thu pht khng ng b tc
ny lun theo mt t l tng ng ca Baud Rate. Cc t l thng s dng l 1x, 16x
hoc 64x tc Baud Rate. Sn xung ca TxC dch chuyn d liu ni tip ra chn
TxD ca 8251.
+ m thu (Receiver Buffer):
m thu thu nhn d liu ni tip v chuyn i thnh d liu song song sau khi
loi b nhng k t hoc bit tng ng s dng trong k thut thu pht thng tin.
Tn hiu thu c a qua cho RxD v c dch chuyn vo thanh ghi m thu theo
sn ln ca xung RxC .
+ Khi iu khin thu (Receiver Control):
Khi ny gim st v iu khin mi hot ng lin quan n vic nhn d liu ni
tip. Cc tnh nng ch yu ca khi ny nh sau:
- Trong iu kin ngh, RxD ngn mi tn hiu "low". Trc khi bt u
nhn d liu ni tip, trn chn ny phi c khng nh gi tr "1" logic,
t , khi bt u d tm gi tr "0" c ngha, tng ng vi Start bit.
- Mch nhn bit bit Start bng cch loi tr mi tn hiu nhiu thng qua
d tm sn xung trn RxD v xc nh bit Start cho vic thu nhn d
liu.
- Pht hin li chn l thng qua bit trng thi chn l - Pht hin li khung
d liu thng qua bit Stop cui byte d liu cui cng trong ch thu
pht khng ng b.
+ RxRDY (Receiver Ready):
Tn hiu ra RxRDY bo rng 8251 nhn xong mt k t v ang sn sng
chuyn cho CPU. RXRDY cng c th ni vo chn yu cu ngt i vi CPU trong
phng php vo/ra theo ngt, hoc lm tn hiu bo trng thi trong phng php
vo/ra thm d (polled operation). Tn hiu RxEnable khi l off, s gi cho RxRDY
iu kin ti khi ng. Thanh ghi m vo phi c php d tm bit Start ca d
liu mi v k t hon chnh c nhn phi c gi vo thanh ghi d liu ra. Khi
xy ra s c c k t nhn c t thanh ghi d liu ra, chip s to li Overun, k
t va nhn s b b qua.
+ RxC (Receiver Clock):
Xung nhp nhn to lp tc thu d liu. D liu c ghi nhn tng bit theo
B mn K thut my tnh
109
sn ln ca xung nhp RxC .Trong ch thu pht ng b, tn s RxC bng ng tn

s ca xung Baud Rate. Cn trong ch thu pht khng ng b, tn s xung ny
c ly theo t l 1x, 16x hoc 64x tn s tc Baud Rate. C th ly v d:
Baud Rate l 2400 Baud, yu cu i vi xung nhp RxC l
RxC =
2400Hz ch 1x
RxC =
38,4KHZ ch 16x v
RxC =
153,6KHX ch 64x.
Lu rng, tc Baud Rate l mt tc phi chn theo quy chun quc t,

thng thng l 300, 600, 1200, 2400, 4800, 9600, 19200 Baud, v.v..., Ch khng phi
l mt s bt k, nn vic to xung tn s cho RxC v TxC thng c s dng
nhng thch anh c tn s l bi 16, bi 64 ca chui s trn vi chnh xc rt cao,
ch khng s dng tu tin. Hn na, trong phn ln cc h thng thu pht thng tin,
tc thu v tc pht l nh nhau, dn n tn s RxC v TxC cng l mt v c
ly chung t b to tc Baud Rate Generator n gin ho phn giao din.
+ SYNDET (SYNC Detect/BRKDET Break Detect): chn ny c s dng
trong ch thu pht ng b nhn bit k t ng b, c th s dng nh u vo
hoc u ra, c nh ngha qua t iu khin. Chn c chuyn u ra sau khi h
thng c Reset. Trong ch ng b ni (Intemal Sync Mode), chn ny ln mc "1"
c s dng nh u ra trng thi bo nh v c k t ng b trong ch
thu. Khi c lp trnh ch xung ng b kp (Double Sync Character), hay cn
gi l bi-sync, SYNDET s ln mc "1" gia bit cui ca k t ng b th hai.
SYNDET c Reset trong khi thc hin c trng thi. ch ng b ngoi
(Extemal Sync Detect Mode), sn xung ln ti chn SYNDET khi ng 8251 bt
u ghp d liu k t t sn tn ca xung nhp RxC . Ch ny b cm khi tp
trnh cho 8251 hot ng ch Intemal Sync Mode.
+ BREAK (ch c trong ch khng ng b (Asynchronnous Mode):
u ra ny s ln "1" khi trn li vo l LOW (="0") xuyn sut hai ln gp bit
Stop trong chui (tt nhin k c bit Start, cc bits d liu v bit chn l). Bit BREAK
cng c th c c nh mt bit trng thi.
a) M t hot ng
Vic xc nh ch lm vic cho USART-8251 c thc hin thng qua
chng trnh mm. Mt chui cc t iu khin cn c CPU gi ti 8251 xc
nh cc nh dng truyn tin. Cc t iu khin s xc lp: Baud Rate, di m k
t, s bit Stop, ng b hay d b, kim tra chn l v.v... Trong ch ng b, cn
cn xc minh Intemal Sync
hay Extemal Sync Mode. Sau khi nhn c cc t iu khin cn thit, 8251
B mn K thut my tnh
110
sn sng lm vic. Tt nhin, sau khi nhn cc t iu khin, 8251 cn phi ch cho
n khi bit TxEnable c thit lp nh t lnh lm vic (Command Instruction Word)
v tn hiu CTS (Clear To Send).
b) Lp trnh cho 8251:
Trc khi pht hay nhn d liu, 8251 phi c nhn mt chui t iu khin. T
iu khin 8251 c hai loi: Lnh ch (Mode Instruction) v Lnh lm lm vic
(Command Instruction).
- Mode Instruction (MI):
T iu khin ch lm vic cho 8251, c np vo sau khi mch c khi
ng hay ti khi ng cng hoc mm (Reset). Khi c CPU ghi vo 8251, cc
k t SYNC. hoc t lnh lm vic (Command Instruction) c th c chuyn tip
cho 8251 kch hot 8251.
- Mode Instruction (CI):
T lnh lm vic cho 8251, c dng iu khin cng vic thc th ca mch.
T iu khin (MI) v t lnh (CI) phi c gi cho 8251 theo mt tun t khe kht
(Xem Hnh IV.6). MI phi c ghi vo 8251 ngay sau khi c tn hiu Reset trc khi
s dng cho vic truyn d liu.
Hnh IV.6 Tun t khi ng v lm vic vi 8251.

K t SYNC th hai c th b qua khi MI xc nh cho 8251
lm vic ch t ng b (Internal SYNC Mode)
8251 c th lm vic trong hai ch : D b (Asynchronous) v ng b
(Synchronous). hiu c cc ch lm vic ny, c th gi thit rng 8251 l hai
vi mch c lp: mt mch thu pht ng b v mt mch thu pht d b cng c
ghp vo trong mt v. Cc ch ch c th t cho 8251 sau tn hiu Reset h thng.
Lu rng khi cho php s dng bit kim tra chn l (parity bit), n s khng c
tnh vo trong di ca k t thu pht. Gi tr thc ca bit chn l trn li vo RxD
khng c c vo 8251. Nu di k t nh hn 8 bits, n s b b i khi c vo
B mn K thut my tnh
111
8251, cn nu di k t b hn, s c coi l mc "0". Cu trc t iu khin ch

khng ng b (Asynchronous Mode) c th hin trn Hnh IV.7. T iu khin
c gi cho 8251 ngay sau khi c tn hiu Reset. Dng t iu khin ca USART8251 c biu din trn Hnh IV. 7
Hnh IV.7 Khun dng t iu khin cho 8251

Ch khng ng b (Asynchronous Mode)
Only affects Tx,

Rx never requires mo re
than one stop bit
+ Pht khng ng b (Asynchronous Transmission): Khi d liu c chuyn

cho 8251 pht i, 8251 t ng ghp thm bit Start (mc "0"), sau l cc bit d liu,
bt u bng LSBit v gn thm bit kim tra chn l, ri n bit Stop theo ng khung
d liu c nh ngha trong t iu khin, khung d liu ny c truyn i nh mt
chui xung trn li ra TxD. Cc bit c dch chuyn ra TxD bng sn xung ca
xung nhp TxC theo tc 1, 16 hay 64 ln xung nhp TxC theo t iu khin xc
nh sn. Khi khng cn d liu truyn i, TxD chuyn ln mc cao l (marking).
B mn K thut my tnh
112
Lu : Nu di k t c gn theo lnh l 5, 6 hoc 7 bits

Cc bits khng dng ti s c gn bng "0".
+ Thu khng ng b (Asynchronous Receive):

Bnh thng, RxD mc cao ("1"), sn xung xut hin c coi l s bt u
ca bit Start. Tnh hp l ca bit Start c xc nhn bng xung mu ti im gia ca
xung ny (i vi trng hp tc 16x hay 64x). Nu vn c gi tr l "0", l bit
Start hp l, v b m bit bt u hot ng. Cc bit ca d liu v bit chn l c
ly mu ti im gia trn li vo RxD bng sn ln ca xung nhp RxC . Nu mc
thp c nhn bit on tn ti ca bit Stop, c li s c thit lp, bit Stop bo
hiu kt thc ca mt k t. Lu rng phn thu ch cn nhn c mt bit Stop, bt
k s lng bit Stop c gn l bao nhiu. K t nhn c s c chuyn vo b
m song song ca 8251. Tn hiu RxRDY s chuyn ln mc cao bo cho CPU
bit c th nhn k t.
Nu k t trc cha c CPU c v, k t mi vn s c chuyn vo thanh
ghi m ny, v c bo l trn s c thit lp (tc l k t trc b b qua). Tt cc
cc c bo li c th Reset nh lnh Enor Reset. Hnh IV.4 cho thy cc dng thc
B mn K thut my tnh
113
khung d liu (Data Fram) c pht i v thu v trong ch lm vic khng ng

b.
+ Pht ng b (Synchronous Transmission):
u ra TxD mc cao cho n khi CPU chuyn t tin n 8251, thng thng
l k t ng b SYNC. Khi u CTS chuyn sang mc thp, k t u tin c
c pht ni tip TxD. Tt cc cc k t c dch chuyn ni tip ra theo sn
xung ca TxC. Tc pht d liu bng ng tc TxC. K hi hot ng pht
c khi ng, chui d liu trn TxD c ng b theo TxC. Nu CPU khng
cung cp d liu cho 8251 trc khi b m pht b rng, th (cc) k t SYNC s
c chn vo.chui k t pht i ng thi tn hiu in p chn TxEMPTY s
chuyn i ln mc "1" thng bo rng b m pht rng v k t SYNC c
pht. in p trn chn TxEMPTY c Reset khi k t mi c CPU chuyn ti
8251.
+ Thu ng b (Synchronous Receive):
Tn hiu ng b c th l t ng do bn thn 8251 to ra hoc thu t bn ngoi.
Khi hot ng ch ng b, lnh "sn tm" (bit EH - ENTER HUNT) c gp
trong t lnh cho 8251. liu trn li vo RxD c "ly mu" qua sn ln ca xung
nhp RxC . Ni dung ca thanh ghi m nhn Rx buffer c so snh vi k t ng b
SYNC cho n khi hon ton ph hp. Nu c chn l ch ng b kp, tp cc
k t cng c so snh tng t. Khi c hai k t ng b c nhn bit,
USART 8251 kt thc ch sn tm v chuyn sang ng b ho k t. Chn
SYNDET chuyn sang trng thi logic "1", v s t ng Reset nh lnh c trng
thi.
Trong ch Extemal Sync, vic ng b t c nh p mc cao ln chn
SYNDET loi tr ch "sn tm" ca 8251. Mc cao ny s c Reset sau mt
nhp RxC . Lnh EH khng c tc ng g trong ch ny. Vic pht hin li chn l
v li trn hon ton tng t nh thu d b.
Hnh IV.8 l gi d liu trong thu pht ng b.
- Command Instruction (CI)
Dng ca t lnh c th hin trn Hnh IV. 11. Sau khi 8251 c thit lp
ch lm vic, v k t ng b c tch (nu l ch ng b) n sn sng
cho mt hot ng thu pht d liu. T lnh c s dng iu khin cc hot ng
thc t ca 8251 trong ch t. Cc hot ng l: Cho php Thu / cho php
Pht, Reset cc li hay iu khin Modem.
B mn K thut my tnh
114
Hnh IV.9 Khun dng t iu khin cho 8251,

Ch ng b (Synchronous Mode)
Cng cn hiu thm v t trng thi ca 8251. Vi lnh c INput vo CPU trong
trng hp C/D = "1", t trng thi c c vo. Ni dung t trng thi c th hin
trn Byte c vo, cc gi tr logic ca cc bit trng thi RXRDY, TxEMPTY,
SYNDET/BRKDET ti cc bit ng ng D1, D2 v D6 l gi tr trn chnh cc chn
ra tng ng ca 8251. Ring bit TxRDY (bit D0) th hin trng thi rng ca thanh
ghi m d liu votr, cn gi tr trn chn ra TxRDY ca 8251 l kt qu ca s phi
hp cng cc gi tr ca CTS v TxEN c .
D7
DSR
D6
D5
D4
D3
D2
D1
D0
SYND
PE
OE
PE
TxEMPTY
RxRDY
TxRDY
B mn K thut my tnh
115
Hnh IV. 10 Byte trng thi ca 8251

Bit D3 (Panty Error) bng "1" ngha l pht hin c li trong khi kim tra tnh chn
l ca byte d liu, bit ny c xo bng t lnh (bit ER). Bit D4 (Overrun Error)
c Set nu CPU khng kp c d liu trc khi c mt byte mi ang c thu v.
cn bit D7 (Data Set Ready) thng bo DSR ang mc "0".
`
Hnh IV. 11 - Khun dng ca t lnh 8251
B mn K thut my tnh
116
CHNG IV. THIT B VO RA CA H VI X L

VI. Bn phm Hex Keyboard
Bn phm c t chc theo kiu ma trn cc

hng v cc ct, ti v tr giao nhau khng tip xc
c ghp mt cng tc thng m ni hng vi
ct, ch tip xc khi c nhn. xc nh c
mt phm b nhn, ta ni t tt c cc hng v c
ni dung cc ct. Nu trn ct no ta c c
gi tr l "0", tng ng vi trng hp c mt
phm trn ct b nhn. D dng thy rng, nu
cc hng i v i + 1 ni t bt c phm no trn ct
j (hay j + 1) b nhn, ta u c c gi tr "0"
trn ct j (hay j + l).
Hnh V.2 l mt bn phm Hexa gm 22 phm
c to t mt ma trn 3 hng v 8 ct. Gi s rng ta dng vi mch vo ra song song
PPI-8255 xy dng nn bn phm nh trn Hnh V.2. Ba li ra ca port B gm R0,
R1, R2 (tng ng vi cc dy PB0, PB 1 v PB2) c dng ch Output, 8 li
vo ca port A dng D0 D7 (tng ng vi cc dy PA PA7) ch Input. Nh
vy chu trnh c phm theo ch d tm (polling) c thc hin nh sau:
1. m bo phm nhn trc c nh ra, cc gi tr "0" cng lc c p
ln tt c cc hng v c cc gi tr trn cc ct. Nu cc ct u mc "l", chng
trnh tip tc c gi tr cc ct
2. Qut cc ct, tc. l c gi tr ti cc ct pht hin c phm b nhn. tng
tin cy khi c phm, trnh tc ng ca nhiu c hc khi phm b nhn v
cc loi nhiu khc, sau khi pht hin c phm b nhn, chng trnh ch
khong 20msec ri c tip gi tr ti cc ct. Gi tr "0" c c ct no s
c ghi nh s dng cho vic xc nh phm v tr no b nhn
3. Qut hng xc nh v tr ca phm b nhn. S vng lp ny l khng c
nh, nhng nhiu nht l bng s hng c trong cu trc ca bn phm
B mn K thut my tnh
117
4. Gn m cho phm. M cho phm l do thit k phn cng quy nh, tu theo
chc nng v yu cu ca ngi dng.
Hnh 1.2 Bn phm 22 phm s dng giao tip qua PPI8255

Trong v d ny gi s rng cc phm c gn m nh sau:
- T phm 00 n phm 0F (ton b cc phm trong Row 1 v Row 2) c gn m
hexa t "0H" trn "FH"
- Cc phm Row 0 c th gn cc chc nng sau
Phm 10 l phm chc nng "GO" - thc hin chng trnh
Phm 11 l phm chc nng "INS" - thc hin chc nng thay i ni dung
cc thanh ghi ca CPU
Phm 12 l phm "REP" - thc hin chc nng sa ni dung thanh ghi ca
CPU
Phm 13 l phm "DISP" - thc hin chc nng hin th ni dung cc thanh
ghi ca CPU
Phm 14 l phm "STEP" - thc hin chc nng chy chng trnh theo tng
lnh
Phm 14 l phm "ENTER" - thc hin chc nng kt thc nhp d liu
hoc lnh t bn phm
B mn K thut my tnh
118
Lu chng trnh c v xc nh phm b nhn c th hin trn Hnh V.3

Chng trnh c th c vit di dng mt chng trnh con.
Do tnh n hi ca l xo trong phm nn s tip xc ca phm sau khi b nhn c
th m t nh hnh sau:
B mn K thut my tnh
119
Hnh V.3 Lu chng trnh c bn phm

V.2 Ghp ni bn phm vi h Vi x l
Bn phm l thit b ngoi vi cho php a thng tin vo my tnh di dng m
k t. Bn phm thc hin chc nng chuyn thng tin dng lc nhn phm v v tr
ca phm c nhn thnh m phm v chuyn cho my tnh. Bn phm gm hai b
phn chnh l ma trn phm v mch in t qut phm. Ma trn phm l t hp cc
phm nhn c sp xp theo cc hng v ct.
Bnh thng phm lun trng thi nh, khi phm nh th hai tip im khng
B mn K thut my tnh
120
c ni vi nhau, u ra c mc in p dng tng ng vi mc logic "l Khi

phm c nhn th hai tip im c ni vi nhau qua cng tc phm v u ra c
mc in p bng 0V tng ng mc logic "0".
mi ln nhn phm c mt m phm tng ng c to ra, cn sp xp h
thng phm di dng ma trn phm.
Ma trn phm gm cc dy hng v cc dy ct giao nhau nhng khng tip xc
vi nhau. Cc cng tc phm c t ch giao ca hng v ct. Hai tip im ca
cng tc nm trn hng v ct ti ch giao nhau . Mi khi phm c nhn th hai
dy hng v ct c ni vi nhau qua hai tip im ca cng tc ti ch giao nhau.
V.2.1 H thng bn phm ca my vi tnh
H thng bn phm ca my vi tnh gm hai phn bn phm v thit b giao din
bn phm, c kt ni v trao i thng tin theo kiu "ch'
Hnh V.4 S ghp ni bn phm (keyboard) vi h thng my tnh

Bn phm l t hp ca ma trn 8x13 phm v mch vi iu khin P8048. Mch
C8048 l mt h vi x l nh c tch hp trn mt n chip. Mch 8048 bao gm
CPU, b nh ROM cha chng trnh iu khin qut v to m phm, RAM cha d
liu ca chng trnh iu khin, hai cng vo/ra P1 v P2, mt cng d liu 8 bit.
Mch 8048 tun t a m nh phn 3 bit ra ti cng P2, qua b gii m 3/8 to ra tn
hiu qut bn phm. Ti thi im m 3 bit c a ra, mch P8048 thc hin c
tn hiu 13 bit t ma trn, phm vo cng P1, t y to ra m phm (m qut) ca
phm c nhn. Khi phm c nh mt m phm (m qut) cng c to ra bng
cch cng m phm nhn vi 80H.
Mch P8048, c nui bng ngun t my tnh, thc hin trao i thng tin vi
thit b giao din bn phm KC 8042 theo kiu ni tip ng b. KC 8042 c cu trc
tng t mch P8048. KC 8042 ng vai tr ch, 8048 ng vai tr "th" trong
B mn K thut my tnh
121
cc qu trnh truyn tin thng qua hai dy tn hiu: dy "DATA" v dy "CLOCK".

Dy " DATA" truyn tn hiu d liu ni tip gia P8048 v KC 8042. Tn hiu
ni tip bao gm: bit START, 8 b d liu, 1 bit PARITY, 1 bit STOP. Qu trnh trao
i thng tin gia P8048 v KC 8042 c ng b bi tn hiu trn dy "CLOCK".
V.2.2 Qu trnh truyn d liu t bn phm cho CPU
Mch P8048 lun phi kim tra trng thi truyn tin qua hai dy DATA v
"CLOCK" trc khi pht i m phm. Khi KC 8042 t "DATA" = 0 v "CLOCK" =l
th 8048 phi nhn cc ch lnh t KC 8042. Khi KC 8042 t "DATA" = 1 v
"CLOCK" = 1 th P8048 c quyn truyn m phm cho my tnh. Qu trnh truyn
d liu c ng b bng dy xung ng b do P8048 pht ra trn dy "CLOCK".
Khi KC 8042 nhn c m phm dng ni tip, n loi b cc bit to khung d
liu truyn, chuyn m phm vo thanh ghi.tm v pht ra yu cu ngt IRQ1 cho h
thng ngt cng. H thng ngt cng s kch hot chng trnh phc v bn phm 09H
(chng trnh phc v ngt 09H) nm BIOS. Chng trnh phc v bn phm 09H
c chc nng dch m phm thnh m hai byte v cha vo vng m bn phm.
Chng trnh phc v bn phm 09H trc ht kim tra (m) cc phm trt (Shift,
Alt, Ctrl) v cc phm c bit (Scrolllock, Numlock, Capslock, Insert) trc khi dch
m phm sang m hai byte.
M hai byte c chng trnh phc v bn phm 09H to ra c cu trc tu thuc
m phm hoc t hp m phm nhn c. Nu nhn c m ca phm k t th byte
thp ca m hai byte cha m ASCII ca k t tng ng, byte cao cha m phm (m
qut phm). Khi chng trnh phc v bn phm 09H nhn c m cc phm khng
phi l k t th byte thp ca m hai byte c gi tr 0, byte cao cha m phm m
rng.
Vng m bn phm c kch thc 32 byte nm trn b nh chnh ti a ch
0000H:041EH. Trng thi ca cc phm trt v cc phm c bit c cha hai
nh 0000H:0417H v 0000H:0418H. C th truy nhp vng m bn phm c
thng tin v bn phm nh chng trnh ngt 16H ca BIOS.
Chng trnh phc v bn phm 09H cng x l cc trng hp c bit nh:
- Khi phm c nhn qu lu (v d qu 0.5 giy) v KC 8042 khng nhn c
m phm nh, n s gi ra cho n v x l trung tm m ca phm c nhn.
- Khi nhn c t hp cc phm Ctrl+Alt+Del n s khi ng li my tnh.
- Khi nhn c m phm Printscreen n s kch hot ngt 05H ca BIOS.
- Khi nhn c m phm Ctrl+Break n s kch hot ngt IBH ca BIOS.
V.3 Mch iu khin v lp trnh ch th 7-segments
Hin th 7 thanh (7-segment Light Emitting Diode - LED Display) l loi n gin
B mn K thut my tnh
122
nht nhn tn hiu ra v hin th di dng pht sng. C th s dng vi mch ny

hin th cc k t s t 0 n 9. Khi c dng in chy qua, diode s pht sng.
a b c d e f q
0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 0 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1
Hnh V.5 l s mch hin th 8 digits s dng cc vi mch hin th 7 segment s
dng 2 cng ca PPI-8255 theo phng php iu khin hin th a cng
(Multiplexing) ng b. Cc thanh sng a, b, c,..., g ca cc mch hin th 7 thanh
c ni song song vi nhau v ni vi u ra ca gii m BCD-7segment SN7447.
Vic cp ngun nui cho mch hin th (1 digit) c ng ngt bi mt transistor
PNP lm vic ch kho ng m nh xung iu khin t mt li ra ca cng A
ca PPI- 8255. Nh vy, ti mt thi im, bng cch lp trnh cho PPI-8255, ta s
iu khin duy nht mt mch hin th pht sng. Nu tn s ca qu trnh pht
sng t n khong 15 n 20 ln/sec, khng xy ra hin tng nhp nhy khi theo
di.
D liu cn hin th dng m BCD (4-bit) c a ra mch gi m hin th 7
thanh SN7447 qua 4 dy.tng ng ca cng.B, ng thi v tr ca digit cn hin th
s c iu khin pht sng bng cch a in p mc "0" ln li ra tng ng trn
cng A lm thng Transistor cp ngun cho mch 7 segment tng ng. Nh vy
bng cch lp trnh qut ln lt vng qua tt c cc digit, c th iu khin hin th
mt d liu gm ti a 8 ch s.
B mn K thut my tnh
123
Hnh V.5 - S nguyn l mch iu khin bng hin th 8 k t s s dng

PPI8255 theo phng php qut ng
V.4 Mn hnh (Monitor)
V.4.1 Mn hnh ng tia m cc CRT (Cathode Ray Tube)
Mn hnh ng tia m cc CRT l thit b hin th thng dng nht hin nay. Mn
hnh CRT c cu to nh sau:
Mn hnh CRT l mt ng thy tinh chn khng vi cc b phn: cathode pht x

in t, ng phng tia in t, cun li tia va mn hin th. Cathode bng kim loi
c ni vi in p m, c t nng v to ra cc in t t do. Mn hin th c
ph mt lp cht liu pht quang v dn in, c ni vi in p dng v ng vai
tr mt anode. Di tc dng ca in trng cng cao trong ng phng, in t
ri khi cathode, c hi t thnh chm tia hng v pha mn hin th. Cun li tia
c tc dng li chm tia in t dch chuyn theo hai chiu dc v ngang mn hnh.
Khi chm tia in t dp vo mn hin th s to nn mt im pht sng. Cng
B mn K thut my tnh
124
im sng ph thuc vo cng chm tia v cht liu pht sng. Khi chm tia mt
i hoc chuyn hng th im vn cn lu sng mt khong thi gian ngn sau ,
thi gian lu sng ph thuc vo cht liu pht sng v cng chm tia.
nh trn mn hnh CRT c to t cc im nh. im nh c to ra khi

cng chm tia in t c tng ln, im nh khng xut hin khi chm tia b tt
i. Cc im nh c to theo tng dng, t trn xung di. Mt nh hon chnh
c to ra trn mn hin th bi cc dng cha cc im nh. Cc im nh ch tn
ti trong mt thi gian rt ngn. c th quan st c nh cn lm ti cc im
nh theo mt chu k xc nh. Cc im nh c lm ti theo tng dng, bt u t
dng th nht. Cc dng c lm ti tun t t trn xung di. Khi dng cui
cng c qut xong, qu trnh lm ti c bt u li t dng u tin (hnh v).
V.4.2 Ghp ni mn hnh vi h Vi x l
Cc thit b hin th c s dng my vi tnh PC u l loi nh x b nh. B
nh ny c c n v x l trung tm v thit b iu khin mn hnh cng truy nhp
v c gi l b nh hin th. Thng tin cn hin th c a ra b nh hin th,
thit b iu khin mn hnh CRTC lin tc c b nh ny a ra mn hnh. Hnh
v sau y minh ha nguyn tc nh x t b nh hin th ra mn hnh trong ch
vn bn:
Hnh V.7 - Hin th k t trn mn hnh CRT theo nguyn tc nh x b nh
Mi mt k t trn mn hnh l mt nh x ca mt nh hai byte trong b nh

hin th. Byte u cha m ASCII ca k t, byte th hai cha thuc tnh (mu nn,
mu ch, c/khng nhp nhy) ca k t. V tr ca m k t trong b nh xc nh v
tr k t trn mn hnh. M k t u tin trong b nh hin th (v d: m 41H) c
B mn K thut my tnh
125
nh x thnh k t (k t A) ln gc tri trn ca mn hin th, m k t tip theo c

nh x thnh k t tip theo v.v.
Phng php nh x b nh cho php chng trnh my tnh c th d dng thay
i ni dung mn hin th bng cch thay i ni dung ca b nh hin th.
Mi k t c hin th trn mn hnh di dng mt ma trn 8x8() im nh
sng/ti nh trn hnh v:
Phng php hin th nh x b nh khng hon ton ph hp vi vic hin th cc

i tng c hnh dng khng bnh thng v chuyn ng nhanh, p ng thi gian
thc b chm v cn phi thao tc nhiu im nh dch chuyn i tng.
V.4.3 B iu khin mn hnh CRTC
Thit b giao din mn hnh (b iu khin mn hnh) CRTC th hin vic chuyn
m k t trong b nh hin th thnh k t hin trn mn hnh. ch vn bn cc
mu k t ch c hin th cc v tr hng v ct c nh (25 hng x 80 ct).
S nguyn l ca thit b giao din mn hnh ch vn bn nh sau:
Mi mt k t trn mn hnh cha nhiu hng im nh. CRTC c nhim v

chuyn mi m ASCII trong b nh hin th thnh chui cc mu im nh, a mi
mu nm ln mt dng mn hnh. iu ny c thc hin nh b ROM to k t.
ROM to k t cha cc hp mu k t, mi hp mu k t c kch thc 8 byte mang
Cng c nhng trng hp s dng ma trn 5x7, 7x9, 7x12 v 9x14 im
B mn K thut my tnh
126
thng tin v ma trn im nh ca mt k t. V d hp mu k t A c dng sau:
00110000
01111000
11001100
11001100
11111100
Nu cn hin th 256 k t ASCII cn mt ROM 2kbyte, cha 256 hp mu k
t, mi hp mu chim 8 nh lin nhau. Cc hp mu k t trong b ROM to k t
c nh v bng a ch 11 bit, trong 8 bit a ch cao xc nh v tr ca hp trong
ROM, 3 b a ch thp xc nh v tr ca tng byte mu im nh trong hp . Cc
mu k t c t trong ROM theo trt t ca bng m ASCII.
Nguyn l hot ng ca thit b giao din mn hnh trong ch vn bn nh sau:
Gi s cn hin th hai k t A v B ti cc v tr hng 0 ct 0 v hng 0 - ct 1 trn
mn hnh.. M ASCII ca hai k t c t. ti hai v tr tng ng trong b nh hin
th (xem hnh v mc 2.2).
CRTC gi a ch hng v ct mn hnh cho b nh hin th (hng=0, ct=0). B
nh hin th gi m ASCII ca k t (k t A) cho ROM, m ASCII ca k t mang
thng tin v a ch ca hp mu k t trong ROM (8 bit a ch cao). Ti cng thi
im ny CRTC gi a ch ca dng mu im nh (dng mu im 0) cho ROM (3
bit a ch thp). Hai a ch ny c kt hp li to thnh a ch (11 bit) cho php
truy nhp vo dng mu im nh u tin ca k t (k t A) trong ROM v xut n
ra thanh ghi dch nh. T thanh ghi dch nh, tng bit mu nh tun t c a ra
mn hnh.
Khi tt c cc bit mu nh t thanh ghi dch c y ra mn hnh, CRTC tip tc
gi a ch hng-ct (hng=0, ct=1) cho b nh hin th v gi a ch dng mu im
nh (dng mu im 0) cho ROM, b nh hin th gi m ASCII ca k t (k t B)
cho ROM. Dng mu im nh u tin ca k t (k t B) c xut ra thanh ghi
dch nh. Tng t nh th cc dng mu im u tin ca tt c cc k t trn cng
mt hng mn hnh c hin th, cho n k t cui cng trn hng.
CRTC tip tc gi a ch hng-ct (hng=0, ct=0) n b nh hin th, nhng a
ch dng mu im nh by gi l 1 (dng mu im 1) cho ROM. B nh hin th
gi m ASCII ca k t A cho ROM, ROM xut ra dng mu im nh 1 ca k t A.
Dng 1 ca k t B c xut ra theo cch tng t. Cc dng im nh tip theo ca
k t ln lt c hin th ln mn hnh cho n khi tt c cc dng im nh ca
hng vn bn u tin (hng 0) c hin th trn mn hnh.
Cc hng vn bn tip theo cng c hin th theo phng php ni trn.
B mn K thut my tnh
127
Trn thc t hot ng ca CRTC phc tp hn. CRTC phi c kh nng hin th
ch ha. CRTC phi theo di thng tin v thuc tnh ca k t hin th, phi to
ra im nhy. CRTC cng phi.to ra hai tn hiu ng b nh ngang - dc v lm ti
mn hnh. Tn s lm ti ti thiu l 50 Hz.
B mn K thut my tnh
128
PH LC
PH L C A
Bng tm tt h lnh ca Trung tm Vi x l h x86
T gi nh
Chc nng
T gi
nh
Chc nng
Cc lnh h 80x86
AAA
chnh sau Php cng 2 s dng CMP

ASCII
so snh ton hng ch v

gc
AAD
chnh hai s m ASCII trc CMPS

php chia
so snh chui Byte hay t
AAM
chnh sau php nhn 2 s m CMPSB

ASCII
so snh xu (byte)
AAS
Chnh sau Php tr 2 s m CMPSW

ASCII
so snh xu (t)
ADC
Cng c c nh
CWD
Bin i t thnh t kp
ADD
Cng 2 ton hng
DAA
Hiu chnh thp phn sau

php cng
AND
V tng bit tng ng ca 2 DAS

ton hng
Hiu chnh thp phn sau

php tr
CALL
Gi chng trnh con
DEC
Gim ton hng ch i 1
CBW
chuyn byte thnh t
DIV
chia khng du
CLC
xo c nh
ESC
Thot
CLD
xo c hng
HLT
Treo
xo c ngt
lDlV
chia s nguyn
CMC
Ly b c nh
IMUL
Nhn s nguyn
IN
c cng vo ra
JS
Nhy nu c c du
INC
Tng ton hng ch ln 1
JZ
Nhy nu bng 0
INT
Gi ngt
LAHF
Np 8 bit thp ca c nh
vo AH
INTO
Ngt nu b trn
LDS
Np nh t kp vo thanh
ghi on d liu
IRET
Tr v ch b ngt
LF-A
Np a ch hiu dng
JA
Nhy nu trn
LES
Np con tr khi dng ES
JAE
Nhy nu hn trn hoc bng
LOCK
Kho bus
B mn K thut my tnh
129
JB
Nhy nu thp hn
LODS
Np xu
JBE
Nhy nu thp hn hoc bng
LODSB
Np xu (bytel)
JC
Nhy nu c c nh
LODSW
Np xu (t)
JCXZ
Nhy nu CX = 0
LOOP
vng lp
JE
Nhy nu bng
LOOPE
Lp li trong khi bng
JG
Nhy nu ln hn
LOOPNE Lp li khi khng bng
JGE
Nhy nu ln hn hoc bng
LOOPNZ Lp khi khng bng 0
JL
Nhy nu nh hn
LOOPZ
Lp khi bng 0
JLE
Nhy nu nh hn hoc bng
MOV
chuyn ngun ti ch
JMP
Nhy khng iu kin
MOVS
chuyn xu
JNA
Nhy nu khng trn
MOVSB
chuyn xu (byte)
JNAE
Nhy nu khng trn hoc MOVSW chuyn xu (t)

bng
JNB
Nhy nu khng di
JNBE
Nhy nu khng di hoc NEG

bng
o du hay ly b 2
JNC
Nhy nu khng c c nh
NOP
Khng hnh ng
JNE
Nhy nu khng bng
NOT
o du (ly b 1)
JNG
Nhy nu khng ln hn
OR
Hoc cc bit tng ng ca

2 ton hng
JNGE
Nhy nu khng ln hn hoc OUT

bng
vit cng vo/ra
JNL
Nhy nu khng nh hn
hi phc ni dung (cc

thanh ghi....)
JNLE
nhy nu khng nh hn hoc POPF

bng
Hi phc ni dung cc c
JNO
Nhy nu khng trn
PUSH
y ni dung (thanh ghi...)

vo ngn xp
JNP
Nhy nu khng c c chn l
PUSHF
y ni dung c vo ngn
xp
JNS
Nhy nu khng c c du
RCL
Quay tri qua c nh
JNZ
Nhy nu khng bng 0
RCR
Quay phi qua c nh
JO
Nhy nu c c trn
REP
Lp li
JP
Nhy nu c c chn l
REPE
Lp li khi bng
B mn K thut my tnh
MUL
POP
Php nhn
130
JPE
Nhy nu c c l chn
REPNE
Lp li khi khng bng
JPO
Nhy nu l l
REPNZ
Lp li khi khng bng 0
REPZ
Lp li trong khi bng 0
STC
t c nh
RET
Tr v
STD
c hng _
ROL
Quay tri
STI
t c ngt
ROI
Quay Phi
STOS
Lu tr xu
SAHF
Lu tr AH vo byte thp ca c STOSB
Lu tr xu (byte)
SAL
Dch tri s hc
STOSW
Lu tr xu (t)
SAR
Dch phi s hc
SUB
Php tr
SBB
Tr c mn
TEST
Kim tra (nhn logic ch

vi gc)
SCAS
Qut xu
WAIT
SCASB
Qut xu (byte)
XCHG
Trao i
SCANW
Qut xu (t)
XLAT
chuyn i bng
SHL
Dch tri
XOR
Hoc tuyt i tng ng 2

s
SHR
Dch phi
Cc lnh ch c trong 80286, 80386 v 80486

ARPL
chnh trng RPL ca b chn
LSL
Np di on nh
BOUND
Kim tra bin ca trng
LTR
Np thanh ghi nhim v
CLTS
xo c chuyn nhim v
OUTS
xut xu ra cng vo/ra
ENTER
To khi cc thng s vo POPA

CTC
Phc hi tt c cc thanh
ghi a nng
INS
Nhp xu t cng vo/ra
PUSHA
y vo ngn xp cc
thanh ghi a nng
LAR
Np quyn thm nhp
SGDT
Lu tr thanh ghi bng b

m t ton cc
LEAVE
Ra khi CTC (chng trnh con) SIDT

m t ngt
LGDT
Np thanh ghi bng b m t SLDT

ton cc

m t cc b
L\D
Np thanh khi bng b m t SMSW

nam
Lu tr t trng thi my
LLDT
Np thanh khi bng b m t STR
Lu tr thanh ghi nhim v
B mn K thut my tnh
131
cc b
LMSW
Np t trng thi my
VERR
Kim tra mt b chn on

c
VERW
Kim tra mt b chn on

vit
Cc lnh ch c trong 80386 v 80486

BSF
Qut bit v pha trc
SETL
t byte nu nh hn
BSR
Qut bit v pha sau
SETLE
t byte nu nh hn hoc
bng
BT
Kim tra bit
SETNA
t byte nu khnq c trn
BTC
Kim tra v o bit
SETNAE t byte nu khng trn

hoc bng
BTR
Kim tra v xo bit
SETNB
t byte nu khng di
BTS
Kim tra v t bit
SETNBE
t byte nu khng di
hoc bng
CDQ
Bin i t kp thnh t kp SETNC

trong EAX
t byte nu khng nh
CMPSD
so snh xu (t kp)
t byte nu khng bng
CWDE
Bin t t thnh t kp trona SETNG

EAX
JECXZ
Nhv nu ECX bng 0
SETNGE t byte nu khng ln hn

hoc bng
LFS
Np con tr khi dng FS
SETNL
t byte nu khnq nh
hn
LGS
Np con tr khi dng GS
SETNLE
t byte nu khnq nh
hn hoc bna
LSS
Np con tr khi dng SS
SETNO
t byte nu khnq trn
LODSD
Np xu (t kp)
SETNP
t byte nu khng c chn

l
MOVSD
chuyn xu (t kp)
SETNS
t byte nu khng du
MOVSX
chuvn vi Siqh-extend
SETNZ
t byte nu khng bng 0
MOVZX
chuyn vi Zero-extend
SETO
t byte nu trn
SCASD
Qut xu (t kp)
SETP
t byte nu c chn l
SETA
t byte nu trn
SETPE
t byte nu chn l chn
SETAE
t byte nu trn hoc bng
SETPO
t byte nu c chn l l
B mn K thut my tnh
SETNE
t byte nu khng ln hn
132
SETB
t byte nu di
SETS
t byte nu c du
SETBE
t byte nu di hoc bng
SETZ
t byte nu bng 0
SETC
t byte nu c c nh
SHLD
Dch tri (t kp)
SETE
t byte nu bng
SHRD
Dch phi (t kp)
SETG
t byte nu ln hn
STOSD
Lu tr xu (t kp)
SETGE
t byte nu ln hn hoc bng

Hon chuyn byte
INVLPG
v hiu ho TLB (cho ch

trang)
CMPXCHG so snh v tro i
WBINV
Ghi tr li b nh chnh
vo nh ngm
INVD
XADD
Hon chuyn v cng
Cc lnh ch c trong 80486

BSWAP
v hiu ha b nh ngm
B mn K thut my tnh
133
PH LC B
Bng lu tha 2n
2n
1
2
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
131,072
262,144
524,288
1,048,576
2,097,152
4,194,304
8,388,608
16,777,216
33,554,432
67,108,864
134,217,728
268,435,456
536,807,912
1,073,741,824
2,147,483,648
4,294,967,296
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2-n
1
0.5
0.25
0.125
0.0625
0.03125
0.015625
0.0078125
0.00390625
0.001953125
0.000976563
0.0004882815
0.00024414125
0.000122070625
0.000061035156
0.000030517578
0.000015258789
0.000007629395
0.000003814697
0.000001907349
0.000000953674
0.000000476837
0.000000238419
0.000000119209
0.000000059605
0.000000029802
0.000000014901
0.000000007451
0.000000003725
0.000000001863
0.000000000931
0.000000000466
0.000000000233
T 2-14 l gi tr lm trn ly 10 s sau du phy
B mn K thut my tnh
134
PH L C C
Bng m ASCII
ROW
Dec
16
32
48
64
80
96
112
Bin
000
001
010
011
100
101
110
111
Hex
10
20
30
40
50
60
70
Dec
Bin
Hex
0000
NUL
DLE
SP
0001
SOH
XON
0010
STX
DC2
0011
ETX XOFF
0100
EOT
DC4
0101
ENQ
NAK
0110
ACK
SYN
&
0111
BEL
ETB
1000
BS
CAN
1001
HT
EM
10
1010
LF
SUB
11
1011
VT
ESC
12
1100
FF
FS
<
13
1101
CR
GS
14
1110
SO
RS
>
15
1111
SI
US
DEL
B mn K thut my tnh
135
PH LC D
CC NHM LNH CA C8051
1. To vng lp v lnh nhy:

a. To vng lp
- Qu trnh lp li chui lnh vi mt s ln nht nh gi l vng lp.
Vng lp trong 8051 c thc hin bng lnh "DJNZ thanh ghi, nhn"
t chc vng lp lng nhau cn s dng 2 thanh ghi lu s m.
b. Lnh nhy
Lnh nhy c iu kin
Lnh
JZ
JNZ
DJNZ
CJNE A,byte
CJNE r,#data
JC
JNC
JB
JNB
JBC
Lnh nhy khng iu kin:
ngha
Nhy nu A=0
Nhy nu A khc 0
Gim v nhy nu A khc 0
Nhy nu A khc byte
Nhy nu byte khc data
Nhy nu CY= 1
Nhy nu CY= 0
Nhy nu bit= 1
nhy nu bit= 0
Nhy nu bit= 1 v xo n
Lnh nhy di:

L lnh 3 byte. Byte u l m lnh, 2 byte cn li l a ch 16 bit ca ch. a
ch ch 2 byte cho php lnh c th nhy n bt k v tr nh no trong khng gian
nh 0000 n FFFF
Lnh nhy ngn ?
Lnh nhy ngn l lnh 2 byte. Byte u tin l m lnh, byte th 2 l a ch
tng i ca a ch ch. a ch ch tng i c ngha l so vi gi tr ca b m
chng trnh.
2. Lnh gi Call
Lnh cao dng gi chng trnh con
Lnh gi di Lnh (longcall):
y l lnh 3 byte. Byte u l m lnh, 2 byte cn li l a ch ca chng trnh
con ch. sau khi thc hin xong 1 chng trnh con, 8051 bit c ch quay tr
v th a ch ca lnh ng ngay sau lnh gi Lcall s c t ng ct vo ngn xp.
B mn K thut my tnh
136
Lnh gi tuyt i A call:

Lnh Acall l lnh 2 byte, a ch ch ca chng trnh con phi nm trong
khong 2 Kbyte a ch v chi c 11 bit ca 2 byte c dng xc nh a ch. Thc
t mt s bin th 8051 ch c 1 Kbyte ROM trn chip. Trong nhng trng hp ,
s dng lnh Acall c th tit kim c mt s byte b nh ca khng gian ROM
chng trnh so vi lnh Lcall.
3. Nhm lnh c bn ca 8051:
Tp lnh ca 8051 c chia thnh 5 nhm:
- S hc.
- Lun l.
- Chuyn d liu.
- Chuyn iu khin.
- R nhnh.
Cc chi tit thit lp lnh:
Rn
Thanh ghi R0 en R7 ca bank thanh ghi c chn.
Data
8 b a ch vng d liu bn trong. N c th l vng

RAM d liu trong (0-127) hoc cc thanh ghi chc nng
c bit.
@Ri
8 bit vng RAM d liu trong (0-125) c nh gi a ch

gin tip qua thanh ghi R0 hoc Ri.
#data
Hng 8 bit chc trong cu lnh.
#data 16
Hng 16 bit cha trong cu lnh.
Addr 16
16 b a ch ch c dng trong lnh LCALL v LJMP.
Addr 11
11 b a ch ch c dng trong lnh LCALL v AJMP.
Rel
Byte offset 8 bit c du c dng trong lnh SJMP v

nhng lnh nhy c iu kin.
Bit
Bit c nh a ch trc tip trong RAM d liu ni hoc

cc thanh ghi chc nng c bit.
a. Nhm lnh x l s hc:
B mn K thut my tnh
137
ADD A, Rn
ADD A,data
ADD A@Ri
(1 byte 1 chu k my): cng ni dung thanh ghi Rn vo

thanh ghi A.
(21): Cng trc tip 1 byte vo thanh ghi A.
(11): Cng gin tip ni dung RAM cha ti a ch c
khai bo trong Ri vo thanh ghi A.
ADD
(21): Cng d liu tc thi vo A.
ADD A,Rn
(11): cng thanh ghi v c nh vo A.
ADD A,data
(21): Cng trc tip byte d liu v c nh vo A.
ADDC A~RI
(l l): cng gin tip ni dung RAM v c nh vo A.
ADDC
A,#data
SUBB A,Rn
(21): Cng d liu tc thi v c nh vo A.

(11): Tr ni dung thanh ghi A cho ni dung thanh ghi
Rn v c nh
SUBB A,data
(2 1): Tr trc tip A cho mt s v c nh.
SUBB A,Ri
(l l): Tr gin tip A cho mt s v c nh.
SUBB
A #d
INCt A
(2 1): Tr ni dung A cho mt s tc thi v c nh.

(11): Tng ni dung thanh ghi A ln 1.
INC Rn
(11): Tng ni dung thanh ghi Rn ln 1.
INC data
(2 1): Tng d liu trc tip ln 1.
INC @Ri
(11): Tng gin tip ni dung vng RAM ln 1.
DEC A
(11): Gim ni dng thanh ghi A xung 1.
DEC Rn
(11): Gim ni dung thanh ghi Rn xung 1.
DEC data
(21): Gim d liu trc tip xung 1
DEC @Ri
(II): Gim gin tip ni dung vng RAM xung 1.
INC DPTR
(12): Tng ni ng con tr d liu ln 1.
MUL AB
(14): Nhn ni dung thanh ghi A vi ni dung thanh ghi
DIV AB
DA A
B (l4): Cha ni dung thanh ghi A cho ni dung thanh ghi

B (ll): hiu chnh thp phn thanh ghi A.
b. Nhm lnh lun l:
B mn K thut my tnh
138
ANL A,Rn
(11): AND ni dung thanh ghi A vi ni dung thanh ghi

Rn.
ANL A,data
(21): AND ni dung thanh ghi A vi d liu trc tip.
ANL A,@RI
(11): AND ni dung thanh ghi A vi d liu gin tip

trong RAM.
ANL A,#data
(21): AND ni dung thanh ghi vi d liu tc thi.
ANL data,A
ANL
data,#data
ANL C,bit
(21): AND mt d liu trc tip vi A.

(32): AND mt d liu trc tip vi A mt d liu tc
thi.
(22): AND c nh vi 1 bit trc tip.
ANL C,/bit
(22): AND c nh vi b 1 bit trc tip.
ORL A,Rn
(11): OR thanh ghi A vi thanh ghi Rn.
ORL A,data
(21): OR thanh ghi A vi mt d liu trc tip.
ORL A,@Ri
(11): OR thanh ghi A vi mt d liu gin tip.
ORL A,#data
(21): OR thanh ghi A vi mt d liu tc thi.
ORL data,A
(21): OR mt d liu trc tip vi thanh ghi A.
ORL
data,#data
ORL C,bit
(31): OR mt d liu trc tip vi mt d liu tc thi.

(22): OR c nh vi mt bit trc tip.
ORL C,bit
(22): OR c nh vi b ca mt bit trc tip.
XRL A,Rn
(11): XOR thanh ghi A vi thanh ghi Rn.
XRL A,data
(21): XOR thanh ghi A vi m d liu trc tip.
XRL A,@Ri
(l l): XOR thanh ghi A vi mt d liu gin tip.
XRL A,#mua
(21): XOR thanh ghi A vi m d liu tc thi.
XRL data,A
(21): XOR mt d liu trc tip vi thanh ghi A.
XRL
data,#data
SETB C
(3 l): XOR mt d liu trc tip vi mt d liu tc thi.

(11): t c nh.
SETB bit
(21): t mt bit trc tip.
CLR A
(11): xa thanh ghi A.
CLR 0
(11): xa c nh.
CPL A
(11): B ni dung thanh ghi A.
B mn K thut my tnh
139
CPL 0
(l l): B c nh.
CPL bit
(21): B mt bit trc tip.
RL A
(11): Quay tri ni dung thanh ghi A.
RLC A
(11): Quay tri ni dung thanh ghi A qua c nh.
RR A
(11): Quay phi ni dung thanh ghi A.
RRC A
(11): Quay phi ni dung thanh ghi A qua c nh.
SWAP
(11): Quay tri ni dung thanh ghi A 1 nibble (1 /2byte).
c. Nhm lnh chuyn d liu:
MOV A,Rn
(l l): Chuyn ni dung thanh ghi Rn vo thanh ghi A.
MOV A,data
(21): Chuyn d liu trc tip vo thanh ghi A.
MOV A,@Ri
(l l): chuyn d liu gin tip vo thanh ghi A.
MOV A,#data
(21): Chuyn d liu tc thi vo thanh ghi A.
MOV Rn,data
(22): Chuyn d liu trc tip vo thanh ghi Rn.
MOV Rn,#data
(21): Chuyn d liu tc thi vo thanh ghi Rn.
MOV mua,A
MOV data,Rn
(21): Chuyn ni dung thanh ghi A vo mt d liu

trc tip
(22): Chuyn ni dung thanh ghi Rn vo mt d liu
trc tip.
MOV data,data
(32): Chuyn mt d liu trc tip vo mt d liu

trc tip
MOV data,@Ri
(22): Chuyn mt d liu gin tip vo mt d liu

gin tip
MOV data,#data
(32): Chuyn mt d liu tc thi vo mt d liu

trc tip
MOV @Ri,A
(11): chuyn ni dung thanh ghi A vo mt d liu

gin tip.
MOV @Ri,data
(22): Chuyn mt d liu trc tip vo mt d liu

gin tip
MOV @Ri,#data
(21): Chuyn d liu tc thi vo d liu gin tip.
MOV
DPTR,#data
B mn K thut my tnh
(32): Chuyn mt hng 16 bit vo thanh ghi con tr

d liu
140
MOV C,bit
(21): Chuyn mt bit trc tip vo c nh.
MOV bit,C
(22): Chuyn c nh vo mt bit trc tip.
MOV
A,@A+DPTR
(12): Chuyn byte b nh chng trnh c a ch

l@a+DPRT vo thanh ghi A.
MOVC
A,@A+PC
(12): Chuyn byte b nh chng trnh c a ch l

@A+PC vo thanh ghi A.
MOVX A,@Ri
MOVX
A,@DPTR
MOVX @Ri,A
MOVX
@DPTR,A
PUSH data
POP data
(12): Chuyn d liu ngoi (8 bit a ch) vo thanh

ghi A.
(12): Chuyn d liu ngoi (16 bit a ch) vo thanh
ghi A.
(12): Chuyn ni dung A ra d liu ngoi (8 bit a
ch).
(12): Chuyn ni dung A ra d liu bn ngoi (16 bit
a ch).
(22): Chuyn d liu trc tip vo ngn xp v tng
SP(22): Chuyn d liu trc tip vo ngn xp v gim
SP.
XCH A,Rn
(II): Trao i d liu gia thanh ghi Rn v2 thanh ghi

A.
XCH A,data
(21): Trao i gia thanh ghi A v mt d liu trc

tip
XCH A,@Ri
(l l): Trao i gia thanh ghi A v mt d liu gin

tip
XCHD A,@R
(l l): Trao i gia nibble thp (LSN) ca thanh ghi A

v LSN ca d liu gin tip.
d. Nhm lnh chuyn iu khin:

ACALL addrl 1
(22): Gi chng trnh con dng a ch tuyt i.
LCALL addr 16
(32): Gi chng trnh con dng a ch di.
RET
(12): Tr v t lnh gi chng trnh con.
B mn K thut my tnh
141
RETI
(12): Tr v t lnh gi ngt.
AJMP addr 11
(22): Nhy tuyt i.
LJMP addr 16
(3 2): Nhy di.
SJMP rel
(22):Nhy ngn.
JMP @A+DPTR
(12): Nhy gin tip t con tr d liu.
JZ rel
(22): Nhy nu A=0.
JNZ rel
(22): Nhy nu A khng bng 0.
JC rel
(22): Nhy nu c nh c t.
JNC rel
(22): Nhy nu c nh khng c t.
JB bit,rel
(32): Nhy tng i nu bit trc tip c t.
JNB bit,rel
(32):Nhy tng i nu bit trc tip khng c t.
JBC bit,rel
(32): Nhy tng i nu bit trc tip c t, ri xa bit.
CJNE A,data,rel
(32): So snh d liu trc tip vi A v nhy nu khng bng.
CJNE A,#data,rel
(32): So snh d liu tc thi vi A v nhy nu khng bng.
CJNE Rn,#data,rel (32): So snh d liu tc thi vi ni dung thanh ghi Rn v

nhy nu khng bng.
CJNE
(32): So snh d liu tc thi vi d liu gin tip v nhy nu
@Ri,#data,rel
khng bng.
DJNZ Rn,rel
(22): Gim thanh ghi Rn v nhy nu khng bng.
DJNZ data
B mn K thut my tnh
(32): Gim d liu trc tip v nhy nu khng bng.
142
TI LIU THAM KHO

[1] Nguyn Tng Cng, Phan Quc Khnh: Cu trc v lp trnh h Vi iu
khin 8051. NXB KH&KT H Ni-2004
[2] V Chn Hng: Gio trnh Kin trc my tnh NXB Giao thng vn ti - H
Ni 2002
[3] Vn Th Minh: K thut Vi x l - NXB Thng k - H Ni 1983 [4] Phng K
thut s - Vin Khoa hc Tnh ton v iu khin: K thut Vi x l - Nh Xut bn
Thng k - H Ni 1983
[5] Alan Clements: Principles ofcomputer Hardware - PWS-KENT Publishing
Company - Boston 1992
[6] Intel Corporation: Component Data Catalog 1982
[7] David Hergert, Nancy Thibeault: PC Architecturefrom Assembly Language To
C. Prentice-Hall, Inc. 1997
[8] Christopher L. Morgan and Mitchell Waite: 8086/8088 16-bit Micno-processor
Primer - McGraw-Hill, Inc. 1982
[9] V.M. Rooney: Microprocessors andMicrocomputers - McMilan Publishing
Company - New York 1983
[10] James L., Turley: Advanced 80386programming techniques - Osbome Me
Graw-Hill 1988
B mn K thut my tnh
143

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I HC THI NGUYN

KHOA CNG NGH THNG TIN

THI NGUYN, THNG 11 NM 2006

Gio trnh K thut Vi x l

Gio trnh K thut Vi x l

CHNG 1. TNG QUAN V CC H VI X L

123,45D = 1 x 102 + 2 x 101 + 3 x 100 + 4 x 10-1 + 5 x 10-2

11011.01B = 1 x 24 + 1 x 23 + 0 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2 =

Gio trnh K thut Vi x l

trong h m nh phn theo bng sau:

3A7,C H = 3 x 162 + 10 x 161 + 7 x 160 + 12 x 16-1=

Gio trnh K thut Vi x l

= 2(kn2n-l + kn-l2n-2 + kn-22n-3 +... + k1) + k0

=kn2n-1 + kn-12n-2 + kn-22n-3 + + k1 = 2(kn2n-2 + kn-12n-3 + + k2) + k1

Thy rng: K t u tin ca s nh phn l k0, ng vi s d khi chia SD cho 2,

= k-12-1 + k-22-2 + k-32-3 + k-m+12-m+1 + k-m2-m

= k-1 + (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)

Thy rng k-1 tr thnh phn nguyn ca v phi, vy:

= (k-22-1 + k-32-2 + k-m+12-m+2 + k-m2-m+1)

= k-2 + (k-32-1 + k-m+12-m+3 + k-m2-m+2)

Gio trnh K thut Vi x l

tr hoc bng "0" hoc bng "1", thu c kt qu sau:

Lu : Qu trnh bin i ny kt thc khi phn phn s ca tch s bng 0, tuy

Lu : Phn nguyn c nhm tnh t v tr ca ch s c trng nh nht, phn

Gio trnh K thut Vi x l

I.3. Biu din thng tin trong cc h Vi x l

Cc n v ny c vit tt tng ng l KB, MB v GB.

Gio trnh K thut Vi x l

- M nh phn s dng cc s c biu din theo h m nh phn nh nu

- Biu din d liu l s thc c du: V nguyn tc, du ca s vn l gi tr ca

trong : F l phn nh tr (Mantissa)

Theo nguyn tc ny, mt s thc c biu din trong cc my 32 bit nh sau:

S c biu din c gi tr thc tnh theo biu thc:

+3.4 x 1038 < N < +3.4 x 10-38

- 3.4 x 1038 < N < - 3.4 x 10-38

Gio trnh K thut Vi x l

Lu : Khi kt qu php tnh vt qu cc gii hn trn, nu s m (exponent) l

V gi tr thc c tnh theo biu thc: N = (-l)s x 2E-l023 x F.

A = 1.00111 (tng ng vi b 1 cng thm 1)

I.3.4. Bn cht vt l ca thng tin trong cc h Vi x l

Hnh 1.1. Phm vi mc cao "1" thp "0" Ca mch TTL

Gio trnh K thut Vi x l

Vt mang thng tin v cc gi tr "0" hoc "1" l mt mch in t c bit, m

I.4.1. Php cng v php tr

Gio trnh K thut Vi x l

Gio trnh K thut Vi x l

chia vi du phy tnh, sau tin hnh tm thng s nh sau:

Gio trnh K thut Vi x l

i, tc ngy cng cao, vi nhp ng h ln n hng GHZ, v s xut hin ca

Hnh I.3. S khi cu trc c bn h Vi x l

c m lnh - c tp cc bit thng tin "0" hoc "1" t b nh chnh

Gii m lnh - to cc xung iu khin tng ng vi m lnh iu khin

Gio trnh K thut Vi x l

Thanh ghi con tr lnh IP (Instruction Pointer), trong cc trung tm vi x l

Gio trnh K thut Vi x l

Hnh I.4. S khi b ngun nui my tnh

Hnh I.4. My Vi tnh PC

Gio trnh K thut Vi x l

Gio trnh K thut Vi x l

CHNG II. CC N V VI X L TRUNG TM

Khi CPU c ch to t mt mch vi in t c tch hp rt cao th n c

Hnh II.1a) l s khi cu trc ca P8085

Gio trnh K thut Vi x l