SUBJECT:FUNDAMENTAL OF CMOS VLSI

Sub
Units Dates
Topic (as per syllbus)
topic

No of
hrs.

Req.
hrs.

PART A
1

BASIC MOS TECHNOLOGY:

6/8/2012

Integrated circuits era. Enhancement and

7/8/2012
9/8/12,
10/8/12
11/8/201

depletion mode MOS transistors.

nMOS fabrication. CMOS fabrication.

13/8/12
14/8/12
16/8/12
18/8/12

1
2
3
4

Thermal aspects of processing.

CIRCUIT DESIGN PROCESSES
MOS layers. Stick diagrams. Design
rules and layout lambda-based design and other
Examples. Layout
diagrams. Symbolic diagrams. Tutorial exercises.
CMOS LOGIC STRUCTURES

20/8/12,
21/8/12
23/8/12
25/8/12,
27/8/12
29/8/12

2
2
2

2
2
2

CMOS Complementary Logic, Bi CMOS

31/8/12
3/9/2012
4,7/9/12
8/9/2012
8/9/2012

1
2
3
4
5

10,11/9/
14,15/9/
17,18,
19/9/12

1
2

Logic, Pseudo-nMOS Logic, Dynamic CMOS

6
Pass Transistor Logic, CMOS Domino Logic
Cascaded Voltage Switch
Logic (CVSL).
BASIC CIRCUIT CONCEPTS
Sheet resistance. Area capacitances.
Capacitance calculations. The delay unit
6
Inverter delays. Driving capacitive
loads. Propagation delays. Wiring capacitances.
Scaling models and factors.
PART B
CMOS SUBSYSTEM DESIGN:
Architectural issues. Switch logic. Gate
logic.

Clocked circuits. Other system

24/9/12
25,28/9/
29/9/12
1/10/201
5/10/201

1
2
3
4
5

6/10/201
8/10/201
9,16/10/
19/10/12
29/10/12

1
2
3
4
5

2,3/11/1
5,9/11/1
10,12/11

1
2
3

3
4

CMOS SUBSYSTEM DESIGN PROCESSES:

General considerations.
Process illustration. ALU subsystem. Adders.
Clocking Strategies
Clocking Strategies
Clocked circuits. Other system
MEMORY, REGISTERS AND CLOCK
Timing considerations. Memory
elements. Memory cell arrays.
Examples. Layout
examples.
exercise
TESTABILITY
Performance parameters. Layout issues. I/O pads.
estate. System delays. Ground rules for design. Test
examples

2
1

1
1
2
1
1

2
2

1
2

1
1
1

1
1

2
1
1

2
2
2

FACULTY
Act.
Dates

16/11/12

Verification for stability and linearity during