Acorn Archimedes 500 series Acorn R200 series Technical Reference ManualCopyright © Acorn Computers Limited 1990 Neither the whole nor any part of the information contained in, nor the product described inthis manual may be adapted Or reproduced in any material form except withthe prior written approval of Acorn Computers Limited. The products described in this manual, and products for use with it are subject to continuous development and improvement, Allinformation ofa technical nature and particulars of the products and their use including the information and particulars in this manual) are given by Acorn Computers Limited in good faith. However, Acorn Computers Limited ‘cannot accept any lability for any loss or damage arising from the use of any information or particulars in this manual, ‘or any incorrect use of the products, All maintenance and service on the products must be carried out by Acorn ‘Computers’ authorised dealers or Approved Service Centr-. Acorn Computers Limited can accept no liability whatsoever for any loss or damage caused by service, maintenance or repair by unauthorised personnel. All correspondence should be addressed to: ‘The Customer Service department ‘Acorn Computers Limited Fulbourn Road Cherry Hinton Cambridge CBI 4JN United Kingdom ‘Support and information can also be obtained from the Acorn Support Information Database (SID), This is a Viewdata system available to registered SID users, Initially, access SID by dialing directly into the Guest User access (party 7E1, speed V21/22/29/22bis,UK telephone number (0223) 243642): this will allow you to inspect the system and use a response frame for ragistration. Alternatively, access SID via Prestal (type "SIDA): this will automatically register you on your first call. ACORN, ARCHIMEDES and ECONET are trademarks of Acorn Computers Limited. IBM is a trademark of International Business Machines Corporation. Published by Aco Computers Limited ISBN 1 85250 0867 Part number 046,052 Issue 1, November 1980(Asoo 1 R209 Contents About this manual Part 1 - System description Part 2 Introduction General ‘The VO system ‘The sound system ‘The keyboard and mouse Floppy disc drive Power supply Hard disc drive Case colour specification Interface cards Ethernet interface Ethernet | expansion card Ethernet Il expansion card SCSI interface card Part 3 - Links, plugs and sockets Links. Plugs Sockets Internal expansion Part 4 - Parts lists Main PCB. 4MB RAM upgrade Backplane adaptor ‘ARMS (PGA) daughter card Keyboard Ethernet | Ethernet Il SCSI interface card (issue 2) Drawings Contents + SCSI interface card circuit diagram * Ethernet | expansion card circuit diagram + Ethernet Il expansion card circuit diagram * Main PCB circuit diagram * Main PCB assembly drawing Technical Reference Manual oe 11 12 19 4-10 1.14 1-15 115 115 24 24 243 218 34 32 32 33 44 46 46 47 47 48 49 410 + 4MB RAM upgrade circuit diagram * Backplane circuit diagram + ARMS (PGA) daughter card circuit diagram * Keyboard adaptor PCB circuit diagram Issue 1, November 1990 ui[Asoo / 200 About this manual This manual is intended as a hardware reference for the following models: + Archimedes 540 + Acorn R260 + Acorn R225 ‘Throughout the remainder of this manual, the generic term workstation willbe used to refer to the above, unless a reference to a specific model is required. ‘This manual supplements the basic information given on system hardware in the /nstallation Guide, supplied with ‘certain models (also available for separate purchase). ‘This manual will be of interest to system integrators, software developers and those developing expansion cards for the workstation, The operating systems, RISC OS and RISC IX, are covered at the user levelin the RISC OS User Guide and the RISC ix User Guide, supplied with certain models, (also available for separate purchase), Programmers and Users requiring a greater depth of information about RISC (08 and RISC iX will also need the following manuals: + RISC OS Programmer's Reference Manual (4 volume set) + RISC IX Programmer's Reference Manual (2 volume sel). They are available from Acorn authorised dealers. Full details on the Acorn ARM chip set used in the workstation are given in the Acorn RISC Machine (AFM) Famiy Data Manual, ISBN 0-13-781618-9, available trom: VLSI Technology, inc. ‘Agplication Spectic Logic Products Division 18375 South River Parkway Tempe, AZ 85284 USA 602-752-8674 or from the VLSI national distributor. Note: This manual describes various PCB assemblies. ‘The issue of each PCB is as defined by the relevant schematic. Technical Reference Manual wv Issue 1, November 1990 Contents[Asoo / 200 Part 1 - System description Introduction ‘The workstation is built around the ARM chip set, ‘comprising the Acorn RISC Machine (ARI) itself, the ‘Memory Controller (MEMO), Video Controller (VIDC) and Input Output Controller (10C). The ARM CPU is fitted on a daughter card. Additionally, memory expansion cards are available, each with 4MB of RAM and a MEMC controller. ‘A black diagram of the workstation is shown below: Techi al Reference Manual General The ARMS CPUs a pipelined, 32-bit reduced instruction ‘set microprocessor which accepts instructions and manipulates data via a high speed 92-bit data bus and 26-bit address bus, giving a 64 MB uniform address ‘space. The ARM supports virtual memory systems using ‘a simple but powerful instruction set with good high-level language compiler support. The ARMS version has 4KB ‘of on-chip cache memory, which greatly increases the ‘speed with which some data is handled (typically 2 - 3 times faster than ARM2). ‘across bus | A 10 s0vess #4 synchroniser . tL JL J. Address [clock = seceding synchronise i 0 Adcress bus + Paral! | Podules Part 1 - System description Issue 1, November 1990 eo port 4ott + I mt I i I I ‘Ovelabes 1[Asoo 1 nz00 MEMC acts as the interface between the ARM, VIDG, IOC, ROM (Read-Only Memory) and DRAM (Dynamic RAM) devices, providing all the critical system timing signals, including processor clocks. Upto 4 MB of DRAM is connected to the ‘Master’ MEMC which provides all signals and refresh operations. A Logical to Physical Translator maps the Physical Memory into a 32 MB Logical address space (with three levels of protection) allowing Virtual Memory and Mult-Tasking ‘operations to be implemented. Fast page mode DRAM ‘accesses are used to maximise memory bandwidth. VIDC requests data from the RAM when required and boufers it in one of three FIFOs before using it. Data is requested in blacks of four 32-bit words, allowing efficient use of paged-mode DRAM without locking the system data bus for long periods. MEMC suppor Direct Memory Access (OMA) ‘operations with a set of programmable DMA Address Generators which provide a circular buffer for Video data, a linear butfer for Cursor data and a double butter for, Sound data, 1OC controls the /O bus and expansion cards, and provides basic functions such as the keyboard interface, system timers, interrupt masks and control registers. It supports a number of different peripheral cycles and all UO accesses are memory mapped. VIDC takes video data from memory under DMA control, serialises it and passes it through a colour look-up palette land converts itt analogue signals for driving the CRT ‘guns. VIDC also controls all the aisplay timing Technical Reference Manual parameters and controls the position and pattern of the ‘cursor sprite. In addition, it incorporates an exponential Digital to Analogue Converter (DAC) and stereo image table for the generation of high-quality sound from data in the DRAM VIDC is a highly programmable device, offering a very wide choice of display formats. The colourlook-up palette which drives the three on-chip DACs is 13 bits wide, offering a choice trom 4096 colours or an external video source. The cursor sprite is 32 pixels wide and any number of rasters high. Three simultaneous colours (again from a choice of 4096) are supported and any pixel can be defined as transparent, making possible cursors of many shapes. It can be positioned anywhere on the screen, The sound system implemented on the device can support up to eight channels, each with a separate stereo position, Additional memory is provided on daughter cards, in 4MB blocks. Each 4MB block is controlled by a separate MEMC. NOTE: MEMCs must be Acom Part Number 201,393, to ensure correct timing parameters. The I/O system The 10 system is controlled by IOC, MEMC and two PALs. The lO bus suppor all the internal peripherals, and the expansion cards. 74 Bh _ a : The 1/0 system ‘DATA BUS: pad ~ — Surrencowaot |. ‘ABE ] ya 7 INTERFACE \a (oor or toc ~ — m | ee ad 20 oe | ae : Serger la) eH a [feat] et ; eee wo snl BE jy tear! age | use | PO | vas OE | —— : | ‘ee = 1-2 Issue 1, November 1990 Part 1 - System description\Asoo / 200 This section is intended to give the reader a general Understanding of the VO system and should not be used to program the I/O system directly. The implementation details are liable to change at any time and only the published software interfaces should be used to ‘manipulate the UO system. Future systems may have a different implementation of the lO system, and in particular the addresses (and number) of expansion card locations may move. For this reason, and to ensure that any device may be plugged into any slot, all diver code tor expansion cards must be relocatable. References to the direct expansion card addresses should never be sed. It's up to the machine operating system, in Conjunction with the expansion card ID, to determine the address at which an expansion card should be accessed. To this extent, some of the following sections are for background information only System architecture ‘The li system (which includes expansion card devices) consisis of @ 16-bit data bus (BL{O:18)), a buttered adéress bus (LAl221)), and various contol and timing signals. The VO data bus is independent ofthe main 32- bit systam data bus, being separated from itby bidirectional latches and butters. In this way the UO data bus can un at much siower speeds than the main system bus to cater for slower peripheral devices. The latches between the two buses, and hence the LO bus timing, are controlled by the lO controller, IOC. IOC caters for four Gitferent cycle speeds (slow. medium, fast and synchronous). System memory map Read wee OM tah) scoess wander DMA adress enerators ROM (low), 2 Video Contrater InpwvOutput Conrotors Physically mapped RAM Logically mapped RAM Part 1 - System description Issue 1, November 1990 Technical Reference Manual ‘Atypical VO system is shown in the diagram on the previous page. For clarity, he data and address buses are omitted from this diagram. ‘System memory map The system memory map is defined by master MEMC and the master PAL, and is shown bolow. Note that all system components, including IO devices, are memory mapped. VO space memory map This !0C-controlled space has allocation for simple expansion cards and MEMC expansion cards. Data bus mapping The lO data bus is 16 bts wide. Bytewide accesses are used for B-bit peripherals. The li data bus (BD|O:18) connects o the main system data bus (0[0:31) viaa set of bidirectional data latches. The mapping ofthe BD[0:15] bus onto the D{0:31] bus is as follows: During a WRITE (ie ARM to peripheral) D[16:31] is ‘mapped toB0D(0:15} During @ READ (ie peripheral to ARM) BDIO:15] is ‘mapped to Dj0:15}. Byte accesses Byte instructions are used to access bytewide expansion cards. A byte store instruction places the written byte on all four bytes of the word, and so correctly places the desired value on the lowest byte of the I] bus. A byte or word load may be used to read a bytewide expansion card into the lowest byte of an ARM register. Hex address SFFFFFF ‘3800000 / 4018 daughter card 500000 / Sd slot MEMC (2) ‘3400000 i | ana daughter cars 2nd slot MEME (y) 3000000 4M daughter card ‘stsiot MEME (0) ud) 4M master MEMC (a) 10000000 13Asoo 1 200 Half-word accesses Technical Reference Manual Internal register memory map To access a 16-bit wide expansion card, halt-word instructions are used. When storing, the hal-word is Address placed on the upper 16 bits, 0[16:31]. To maintain aaa Upwards compatibility with future machines, half-word aa stores replicate the written data on the lower hall-word, et 10:18}. When reading, the upper 16 bits are undefined. szo0008H Expansion card identification '3200010H tts important that the system is able to identify what ‘3200014H ‘expansion cards if any) are present, and where they are. ‘3200018H This is done by reading the Podule (expansion card) ‘320001CH Identification (PI) byte, or bytes, from the Podule ‘32000204 Identification Field Seoonesnt VO address memory mapping 32000284 AIIUO accesses are memory mapped. |G is connected 20002CH as detailed inthis table: 32000304 ‘3200084H oe ‘3200038H oc aM 200030H ara 3200040 oe tat] 3200048 m1) Lavo} | s20004eH Tre) Lalts] 20004 Bal | Latta] ‘3200050H aa LAL] 2000544 Pro) tale] s200058H i '820005CH 32000604 s200064H 2000684 s20006CH 32000704 32000744 s200078H s20007cH 1-4 Issue 1, November 1990 Read Contro! Soval Px Data RO status A RQ request A 1RO mask A (RO status B IRQ request B 1RO mask B FIO status FIQ request Fla mask 0 count Low ‘To count High ‘1 count Low 1 count High ‘T2 count Low ‘T2.count High 3 count Low 173 count High Write onto! Serial Tx Data IRQ clear RO mask A RO mask 8 FIO mask TO latch Low To latch High 70 g0 command To latch command Tr latch Low Thatch High 1.90 command ‘latch command atch Low ‘T2latch High "72.90 command ‘T2 latch command 3 atch Low 73 latch High 73.90 command 3 latch command Part 1 - System description(Asoo 1 200 Peripheral address [Cycle] [Base type Bk address [rast Sync Syne 43340000, 43380000, sioe | 4 | ssoso00 fa | 2 | aszcnon oe | «| ssrron 49244000, 23204000 3344000 #3364000 Siow Med Fast ‘Syne Siow | 4 | 43248000 432C8000 Fast | 4 43348000 | syne | 4 | 83368000 Siow Med Fast | 4 4334000 Syne 4 a33¢C000 183246000 Fast | 5 | 8335000 Fast | 5 43350018 Fast 5 | 43350040 Fast | 5 | 83350008 Fast | 6 | 83960000 183360004 7 | 3270000 Part 1 - System description 22310000 | Podule 0 Podule 0 Posule 0 Poduie 0 Podule 1 Podule 1 Podule t Podule + Podule 2 Podule 2 Podule 2 Podule 3 83200000) Podule 3 Podule 3 Podule 3 sare Hos74 Hos74 | ners 16.8 1618 Podule2 Floppy disc controler Econet controller * ‘Serial line controlor Expansion stot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Expansion slot Printer Data Latch 8 (See next ‘page for detais) Latch A (See next age for detals) Latch C (See next age tor dotals) Podule interust request register PPodule interrupt mask register Extended external podule space: Issue 1, November 1990 Technical Reference Manual 15[As00 / 200 VO programming details External latch A External latch A is a write only latch used to control parts of the floppy dise sub-system: Techi External latch 8 al Reference Manual External Latch B is a write only register shared between several users who must maintain a consistent RAM copy. Updates must be made with IRQ disabled. ba [name | Fineton | fen [Name je - | sacar ratte Low | «| secadea | Ito si sero | teen 1 = Side 0 (ower) . om | repr meer | Tn atcouce ep dc Seraeountee eee Sei onc pedt ae | Woitnrden wont Spero : to wa faxna | 7 es External latch External atch is a wre on reister hats used to contol ido sre poly a dock spood esta ere ne Se Le | ei] a0] ver] vee ~[v lw. — L E oe ii3/a\s 1-6 Issue 1, November 1990 Function (co[02} enovid be proganmes 6o[0.2}LOWtorkawecoroatbty. Col conrols he toppy ase cata separator oma (Cott = Double Density Cols] = 1 Sng Dorey ‘This convo the Nlapoy ise controlor reat ino, When rograrsmed LOW, te contol is RESET. “This is usecto indicate vale data. on tn po outputs. should be set HIGH when val data as boon titan tore ptr port ang LOW ‘ster sooutS Cock speed To 0) emus 01 | 25a75mne 10 | Semi 11 | Resend Part 1 « System description[Asoo / R200 Technical Reference Manual Interrupts IRQ status A ‘The VO system generates two independent interrupt a requests, RQ andFIQ,iterupt requests canbe caused | B_—_| Name by events internal to IOC or by extemal events on the | +—— interrupt or control por input pins. ° Pasy The interrupts are controlled by four types of register: + status 1 " | + mask ieee 5 i || + clear The status registers reflect the current state ofthe various interrupt sources. The mask registers determine which a Vor Fyeaek sources may generate an interrupt. The request registers are the logical AND of the status and mask registers and 4 Power-on rset | indicate which sources are generating interrupt requests to the processor. The clear register allows clearing of ee aeons interrupt requests where appropriate. Tha mask registers are undefined after power up. The IRQ events are split nto two sets of registers, A and 7 B Thar eno proty encoding of tho sures, E Internat Interrupt Events ~ + Timer interrupts TM(O:1] + Power-on reset POR + Keyboard Rx data available SAx + Keyboard Tx data register empty ST + Force interrupts 1 External Interrupt Events + IRQ active low inputs IL{0:7] wired as (0-7 respectively) PFIQ, SIRQ, SLCt, not used, DCIRQ, IRQ, PBSY and il. + IRQ falling-edge input IF wired as PACK + IRQ rising-edge input IR wired as VFLY + FIQ active high inputs Fllf:1] wired as FFDQ and FFIQ + FiO active low input FL wired as EFIQ + Control port inputs C{3:5} Podule interrupt mask Podule IRQ can be masked by writing a 0 to the Podulo RQ mask register at &3360004. This will disable the interrupt. The request register at 83360000 is a logical AND of Podule IRQ and the mask register, iit st if Podule IR {snot masked. Part 1 - System description Issue 1, November 1990 Function ‘Thi bt insta thatthe rn is tus) ‘Ths inst that a ingng Inseaton hes bean detected bythe ona ine interac, ‘Ths bt inate that ape sckrowledgoment bt has ben rooehed ‘Tis tnceates tat a vera! yoack Tistitindcates hat power-on res as occured “Thos is inccate thal events have coord Noe latched intr ‘Thisbtis usedtofrce an IROrequet Ie usually owned by tha FIO oe[Asoo / R200 Technical Reference Manual IRQ status B Control port ‘The control register allows the external contro pins C[0:5] tobe read and written and the status of the PACK and Bit | Name Function a sr —____ VELY inputs to be inspected. The C05] bits manipulate 0 | Poduw Fla 16g | Thisbitindcates hata Podule FQ | the C[0:5] VO port. When read, they reflect the current Tews hes boo raced. shou sate of these pins. When written LOW the output pin is aunty be masked OFF riven LOW. These outputs are open-drain, an it + | srobutrenap | Tisbtinscaos thatthe MEMC soune | PrOGrammed HIGH the pin is undrivan and may be Dur ptr as boon roaetes treated as an input 2 | seiairocet | Ts bitidates tnt 65651 seri | __ON reset al bits inthe control register are set to 1 | centr moral na sured a 3 Helse interrupt | This bit indicates that a hard disc | pear Bt | Nome Function 4 | Discchanges | The btinate at th toppy ase cn | vavex | ows te sm otto VELYER) | inerrshas boon rove fr Test Modo sana tobe inspects intent his bit indicates that @ Podule i ee 5 | Pesimeree | etc | | vertalyeacand Ow dng Sepa. See VG ctasoo or 6 KeyoTeevet | Tis tins hate koyoars datas, Tht MUST be transmit oper empy array 8 proqarmed HIG ost romal rooadad | eration cna chi. 7 | Koybe Ric ovent| Tis tates that he kayo ce) | PACK 8 Test | Alows testator pata! priner tecpton rept ef and ay Do Nose ciromadge put be neces. toe ‘The Bt MUST be programmes WH a i a | ote real operation othe ch. cs) swure | Trsconrat te mang tne tat | poor hi programmed HIGH 9 Interrupt status FIQ ‘mute the speaker and LOW to enable a —— 11h spenar ema on reat. Function om vali o to Ruin UO a Foppy dsc | Tisbuindcatetatatoppyese | | ora Senne ee Gxtreauest Data Raqust tas ocaues epost 1 Floppy dite | Ts btindostes nat toppy se eaatincer er fsoruptaquet | rip Request hes ore es nt ro dos EADY 2 Ezonet trop | Tis tlndeates hat an Ezort | he cra | S0A,sci | Te cf prs re uses implant recpest iteruet Request has occured, ‘th 26 bus the bisecting! seria as | cos) 00106 cata hoe for eta [26 bus to wren te al Time Cock . Pode FQ rag. | Ti bt ndates tat poco | Fi Rquost has osoed a 7 | eco Ti it lows an 10 rtarpt Regus ote generated ue 1, November 1990 Part 1 - System description 18[Asoo / R200 The sound system ‘The sound system is based on the VIDC stereo sound hardware. External analogue ant-aliasfiters are used Which are optimised for a 20 kHz sample rate. The high quality sound output is available from a 3.5mm stereo jack socket at the rear of the machine which wil directly drive personal stereo headphones or alternatively an ampitier and speakers. One intemal speaker is fitted, to provide mono aucio. VIDC sound system hardware VIDC contains an independent sound channel consisting of the following components: A four-word FIFO butters 16 8-bit sound samples with a DMA request issued whenever the last byte is consumed from the FIFO. The ‘sample bytes are read out at a constant sample rate programmed into the 8-bit Audio Frequency Register. This may be programmed to allow samples to be output synchronously at any integer value between 3 and 255 microsecond intervals The sample data bytes are treated as sign plus 7-bit logarithmic magnitude and, after exponential digital to ‘analogue conversion, de-gltching and sign-bit steering, are output as a current at one of the audio output pins to be integrated and ftered externally VIDC also contains a bank of eight stereo image position registers each of three bits. These eight registers are sequenced through at the sample rate with the first register synchronised to the frst byte clocked out of the FIFO. Every sample time is divided into eight time slots and the 3-bit image value programmed for each register is used to pulse width modulate the output amplitude between the LEFT and RIGHT audio current outputs in ‘multiples of time slot subdivisions. This allows the signal to be spatially positioned in one of seven stereo image positions. MEMC sound system hardware MEMC provides three internal DMA address registers to ‘support Sound butter output; these control the DMA ‘operations performed following Sound DMA requests from VIDC. The registers allow the physical addresses for the START, PNTR (incremental) and END butter pointers to. block of data in the lowest half Megabyte of physical RAM to be accessed. These operate as follows: programming a 19-bit address into the PNTR register Sets the physical address from which sequential DMA, reads will occur (in multiples of four words), and programming the END pointer sets the last physical address of the buffer. Whenever the PNTR register increments up to this END value the address programmed into the START register is automaticaly \written into the PNTR register for the DMA to continue with a new sample butter in memory. Part 1 - System description Technical Reference Manual ‘A Sound Butfer interrupt (SIRQ) signal is generated when the reload operation occurs which is processed by IOC as. ‘a maskable interrupt (IRQ) source. \MEMC also includes a sound channel enable/disable signal, Because this enableidisable control signal is not ‘synchronised to the sound sampling, requests will normally be disabled after the waveforms which are being synthesised have been programmed to decay to zero amplitude; the last value loaded into the Audio data latch in the VIDC wil be output to each of the Stereo image positions at the currant Audio Sample rate. IOC sound system hardware 10C provides a programmed output control signal which is used to turn the internal speaker on or off, as well as an interrupt enable/status/reset register interface for the ‘Sound Start Butter reload signal generated by MEMC. ‘The internal speaker may be muted by the control ine ‘SMUTE whichis driven from the IOC output C5. On reset this signal will be taken high and the internal speaker will bbe muted, The stereo output to the headphone socket is not muted by SMUTE and will always reflect the current output of the DAC channels. Issue 1, November 1990 19Aéb00 1 8200 The keyboard and mouse ‘The keyboard assembly comprises a membrane keyswitch panel connected to an adaptor PCB, which serialises the keyboard and mouse data; connection to the ARM is made via a serial ink to the IOC. The ARM reads and writes to the KART registers in the IOC. The protocols essentaly half duplex, s0 in normal operation the keyboard will not send a second byte until ithas received an Ack. The only exception to this is during the reset protocol used to synchronise the handshaking, where each side is expecting specific responses from the other, and will nt respond further untl it has these. In addition to this simple handshaking system, the keyboard will not send mouse data unless spectically allowed to, as indicated by Ack Mouse, which allows the transmission of one set of accumulated mouse coordinate changes, or the next move made by the mouse. While itis not allowed to send mouse changes, the keyboard wil butter mouse changes. {similar handshake exists on key changes, transmitted ‘askey up and key down, and enabled by Ack Scan. At the tend of a keyboard packet (two bytes) the operating system will perform an Ack Scan as there is no protocol {or re-enabling later. Mouse data may be requested later by means of Request Mouse Position (ROMP), Key codes The keyboard identifies each key by its row and column adcress inthe keyboard matrix. Row and column codes are appended tothe key Up or down prefix to form the completo Koy code For example, Q key down —the complete row code is 11000010 (&C2) and the column code is 11000111 (cr) 1-10 Issue 1, November 1990 Technical Reference Manual Note: Eight keys have N key roll over. The operating system is responsible for implementing two-key rollover, therefore the keyboard controller transmits all key changes (when enabied). The keyboard does not operate ‘any auto-repeat; only one down code is sent, atthe start of the key down period. Data protocol Data transmissions from the keyboard are either one or ‘wo bytes in length. Each byte sent by the keyboard is incividually acknowledged. The keyboard will not transmit a byte until the previous byte has been acknowledged, unless itis the HRST (HardReSeT) code indicating that a power on or user reset occurred or that 1 protocol error occurred; see paragraph below. Reset protocol ‘The keyboard restarts when it receives an HAST code from the ARM. To initiate a restart the keyboard sends an HRST code to the ARM, which wil then send back HAST to command a restan. ‘The keyboard sends HRST to the ARM if + A power-on reset occurs + Auser reset occurs + A protocol error is detected, After sending HRST, the keyboard waits for an HAST cade. Any non-HRST cade received causes the keyboard to resend HRST. The pseudo program on this page ilustrates the reset sequence or protocol. Note, the on/off state of the LEDs does not change across a reset event, hence the LED state is not defined at power on. The ARM is always responsible for selecting Part 1 - System description[Asoo / R200 the LED status. After the reset sequence, key scanning will only be enabled Ifa scan enable acknowledged (SACK or SMAK) was received from the ARM. Data transmission When enabled for scanning, the keyboard controller informs the ARM of any new key down or new key up by sending a two byte code incorporating the key row and ‘column addresses. The first byte gives the row and is acknowledged by a byte acknowledge (BACK) code from the ARM, If BACK was not the acknowledge code then the error process (ON error is entered. the BACK code was received, the keyboard controller sends the column Information and waits for an acknowledge. If either a NACK, SACK, MACK or SMAK acknowledge code is, received, the keyboard controller continues by processing the ACK type and selecting the mouse and ‘scan modes implied. the character recelved as the ‘second byte acknowiedge was not one of NACK/MACKISACK/SMAK then the error process is, ‘entered Mouse data Mouse data is sent by the keyboard controller it requested by a ROMP request from the ARM or if a ‘SMAK or MACK has enabled transmission of non-zero values. Two bytes are used for mouse position data. Byte fone encodes the accumulated movement along the X axis while byte two gives ¥ axis movement, Both X and Y counts must be transferred to temporary ‘registers when data transmission is triggered, so that accumulation of further mouse movement can occut. The Technical Reference Manual X and Y counters are cleared upon each transfer to the transmit holding registers. Therefore, the count values are relative to the last values sent. The ARM acknowledges the first byte (Xcount) with a BACK code land the second byte (Ycount) with any of NACK/MACK/SACK/SMAK. A protocol failure causes the keyboard controller to enter the error process (ON error). When transmission of non-zero mouse data is enabled, the keyboard controller gives key data transmission priority over mouse data except when the mouse counter overiunderfiows. ‘Acknowledge codes ‘There are seven acknowledge codes which may be sent by the ARM, RAK1 and RAK? are used during the reset ‘sequence. BACK is the acknowiedge to the first byte of a 2-byte keyboard data set. The four remaining types, NACKIMACKISACK and SMAK, acknowledge the final byte of a data set. NACK disables key scanning and therefore key upidown data transmission as well as, setting the mouse mode to send data only on ROMP request. SACK enables key scanning and key data transmission but disables unsolicited mouse data. MACK disables key scanning and key data transmission and enables the transmission of mouse count values if either Xor ¥ counts are non-zero. SMAK enables key scanning and both key and mouse data transmission. It combines the enable function of SACK and MACK, While key scanning is suspended (atter NACK or MACK) any new key depression is ignored and will not result in a key down transmission unless the key remains down after scanning resumes following a SACK or SMAK. New key down data. Encoded Row (fst byte) and column (second byte) numbers. Encoded Row (st byte) and column (second byte) numbers for a now key up. [Encoded mouse count, X (byte) then ¥(byte2). Only from AFI to keyboard. Code values Memon] mab | ib | Comments HAST [1111 | 1111 bjt command, Keyboard reset RAK: | 1111 | 1110 1-byte response in reset protocol Rake | 1111 | 1101 byte response in reset protocol | arD jer | mex | nt A nde etn post | 1110 | xxx | byte from keyboard, echoes four data is of ROPD. OID 0010-0000. -_-byte ARM request or keyboard ID. KBIO | 10% © xx |e rom keyboard encoding keyboard ID. KODA 1100, xxx KUDA | 1101 x0 ROMP | 0010 0010_-|-t-byte ARM request or mouse data MOAT | 00x xe BACK | O011—«1111_—_—_Adkor fist keyboard data bye pate. NACK | 0011 0000 _Last dat byte Ack, selects scarvmouse mado. SACK | 0011 0001 |Last cata byte Ack. J mmc font | ono | amet tt Mak | 0011 0011 |Last data byte Ack LEDS 0000 xx —_bitfag to tun LED{6) ont | past 001 | 9010 From ARM, 1-byte command, doos nothing xis a data bitin the Codo; 0.9, 0's a four bit data fils Part 1 - System description Issue 1, November 1990(Asoo / 200 Technical Reference Manual Similarly, a key release is ignored while scanning is off. Commands may be received at any time. Therefore, ‘commands can be interleaved with acknowledge replies ‘rom the ARM, eg keyboard sends KDDA (first byte), keyboard receives command, keyboard receives BACK, keyboard sends KDDA (second byte), Keyboard receives command, keyboard receives SMACK. Ifthe HAST command is received the keyboard immediately enters the restart sequence. The LEDS and PRST commands may be acted on immediately. Commands which require a response are held pending until the current data protocol is complete. Repeated commands only require a single response from the keyboard. ARM commands: Mnemonic Function HAST | Reset keyboard. LEDS —_| Turns key cap LEDs ont A three bitfield Inicates wnich state the LEDs should bein, Logic 1 is ON, logic 0 (zoro) OFF. 0 controls CAPS LOCK D1 controls NUM LOCK D2 controls SCROLL LOCK ROM Froquest mouse postion (X,Y counts) OID —_|_lequest keyboard identification code. The ‘computer is manutactured wit a 6-bit code to idonity the keyboard type tothe ARM. Upon | teceipt of RAID the keyboard controller transmis KBID tothe AFM. PRST | Reserved fr future use, the keyboard controller curenty ignores this command, Mouse interface ‘The mouse interface has three switch sense inputs and two quadrature encoded movement signals for each of the X axis and ¥ axis directions. Mouse key operations are debounced and then reported to the ARM using the ‘Acorn key up / key down protocol. The mouse keys are allocated unused row and column codes within the main key matrix. [sweet low code-7 Column code - 0 ‘Switch 2 (middle) Row code-7 Column code - 1 | switch 3 (ight) Row code-7 Column code - 2 For example, switch 1 release would give 11010111 {&D7) as the complete row code, followed by 11010000 (D0) fo the column code. Note: Mouse keys are disabled by NACK and MACK acknowledge codes, and are only enabled by SACK and 'SMAK codes, i they behave inthe same way as the keyboard keys ‘The mouse is powered from the computer SV supply and may consume up to 100mA. Movement signals Each axis of movement is independently encoded in two ‘quadrature signals. The two signals are labelled FEFerence and DiRection (eg X REF and X DIR). The table below defines the absolute direction of movement. Circuitry in the keyboard decodes the quadrature signals ‘and maintains a signed 7-bit count for each axis of mouse movement ROPD | For future use. The keyboard control wll a oS ae ‘encode the four data Bs into the POAT code etait data old and then send PDAT tothe APM. 4 | | DIR | | —| fh fe + | 0 | 0 | 0 | trerease count by one 0 | 0 0 | 1 | foreach change of sat o fa ia i4 1 |a fe |r 0 | 1 | 0 | 0 | Decrease count by one 0 0 | + | 0 | foreach ehange of sat. 1 | oft {a When count overtiow or underflow ocours on either axis both X and ¥ axis counts lock and ignore futher mouse ‘movernent until the current data has been sent to the ARM (Overflow occurs when a counter holds its maximum positive count (0111111 binary). Underfiow occurs when € counter hold its maximum negative count (1000000 binary). 1412 Issue 1, November 1990 Part 1 - System descriptionA’s00 / 200 Technical Reference Manual Base Keyswitch mapping (UK 103 key keyboard) Key Key | Row size name | code ese A Fe Fa Fa FS Fe 7 Fe Fo Fito Fin Fi2 Print Seroi Break fe Backspe Insert Home Pou Numlock Part 1 - System description ol code o Sen OTMOO MSS aT aaeUN TS Key | Key | Row | Col. Notes Notes size name code code fslee | ree 1c) 6 1 1 1 a 2 7 2 1 wo 8 2 1 BE 2 9 2 1 RO 2 A a 1 T | 8 2 1 ola fe je bs 1 \ 2 E S 1 o 2 F 2 1 Pp i3 ° 2 1 |3 1 2 1 D3 2 2 181A 3 3 2 1 Delete 3 4 1 13 ' Copy 3 5 1 1 1 Podwn 3 6 1 1 1 7 3 7 1 88 8 1 a la 8 1 3 ala iw | cu |s e |4a 1 a 3 © 1 s |3 . i o |s E 1 Fe 3 F 1 a | ° i 1 HO i4 1 1 J ia 2 1 ke ole 3 1 Loa 4 H 4 5 1 4 6 225 Reum 4 7 Ja 1 1 sia 8 1 1 5s | 8 12 1 3 \4 A 1 1 + |4 B ft 14 1 ow and colin codes arin exadecina 1 Notes: Koy cloud ory. 2 Roy coloy da fey 5 ep ponbon win Wkly otovr ’ Siaen CED vce tay 220 Issue 1, November 1990[Asoo / R200 Keyswitch mapping (cont.) key ‘size 2 1 1 1 1 1 1 1 1 1 275 1 1 18 15 70 18 15 1 1 1 20 1 20 ow and columns cages ar Nowe: key Name shit Zz x © v 8 N ™ shit erstUp Row | Col code code 4 ° 4 E 4 F 5 a 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 8 5 A 5 8 5 © 5 oD 5 e 5 F 6 o 6 1 6 2 6 3 6 4 6 5 6 6 6 7 ey colour - ve gey ey colour are Sey Soson mith ky rollover. Stban ED under key cp. Notes 14 13 Issue 1, November 1990 Technical Reference Manual Floppy disc drive ‘The floppy disc drive used on the workstations (except discless) is a one-inch high drive, taking 3.5 inch double- sided double-density floppy discs. Performance ‘capacity 11M (unformatted) Trackto rack step rate | Ome Sock sete time 15ms Wie to ead ming +2008 Powerontodtive ready | 1000ms | Power suppty +8V (= 5%) Maximum power 2 Wats continuous) Power connector The power connector is a 4-pin, 2.5mm pitch type. Pin Signal ssv | ov ov +12 Interface connector The interface connectors a 94-way, 2 row, 0.1 inch pitch type, with pinouts as shown below: Pin Signal Dir Retn | Signal main (PCB) 1 2 Disc change 1 3 4 Inuse i 5 | 6 | Drveselect 3 ° r ie Index ' es | 10 Drive select 0 ° w |e Drive select 1 ° |aa | 14 Drive select 2 ° 16 | 6 Motor ON ° wv fa Direction | 0 19 | 20 StepDiscchgrst | 0 | a | Wate cata ° 23 | Wate gate ° 2 | 28 rack 0 ' 27 |B write protect 1 29 | 30 Road data q a1 | 82 Side 1 solect ° 33 t Ready ' “Optionally +5V Input = Output Part 1 - System description(Asoo / 200 Power supply Performance characteristics Performance | in| Nom| Max | Units 198 | 220 | Joe }110 | 132 ) vec Input votag (7-53 He} “Input votage (57-69 He) eae aio lai | rere eee aae ol isy) nae | eer | | [os [ue ceases very ee at epee eee a oe alo ue fal lpia ae conte fon) | as meas | cee ete ena ome ae mca eoceeeete ee eae eee als |slee | coaencs [one | es | kee Output ripple and noise VOS- | 50. | mvpkipk eee | | [os |e — a one el oe |. |- | so ftomeve “Maruocuting option DANGER, ‘THE POWER SUPPLY IS A SEPARATE REPLACEABLE MODULE, AND CONTAINS NO USER ‘SERVICEABLE PARTS, ALL ACORN POWER SUPPLIES CONTAIN HAZARDOUS VOLTAGES AND MUST NOT BE MODIFIED OR REPAIRED BY ANYONE OTHER THAN AUTHORISED ACORN SERVICE CENTRES, POWER SUPPLY UINTS MAY ONLY BE FITTED BY ‘AN AUTHORISED ACORN SERVICE CENTRE, ‘SAFETY EARTH CONTINUITY TESTING MUST BE CARRIED OUT WHEN ANY POWER SUPPLY IS FITTED. Part 1 - System description Technical Reference Manual Hard disc drive ‘The hard disc drive used on the workstations {except discless) is an internally-ited SCSI device. For more information on the types of SCSI drive usable, see the ‘SCSI Expansion Card User Guide. Case colour specification ‘The colour of the eream plastic moulsings, the main case and the back panels which are painted, is Pear! White RAL 10130. ‘The colour ofthe light grey front sub-moulding and the light grey keyboard keycaps is Pantone warm grey 3. The colour ofthe darker grey keytops is Pantone warm arey 6. Issue 1, November 1990 1-15‘A800 / 2200 Technical Reference Manual Issue 1, November 1990 Part 1 - System description[Asoo / R200 Part 2 - Interface cards Ethernet interface Where an Ethernet interface is ited, itis provided by one cof two different types of Ethernet expansion card, identified as Ethernet | and Ethemet Il. Both cards can ‘support either a thick’ or thin’ (Cheapernef) Ethernet interface. Overview Ethernet was developed by the Xerox Corporation in the early 1970s and a specification made available in 1980, This specication known as the ‘Blue Book’ was used as the basis for the IEEE and ECMA standards. All new equipment (including this produc) is or should be designed to the IEEE standard, This allows networking with existing Ethernet equipment, a least at the physical level ‘An understanding of the basic architecture of the EthernevIEEE 802.3 standard is assumed. The Intel publication The LAN Components User's Manuals particularly useful and contains a suitable introduction to local area network standards. tis recommended that you ‘obtain a copy if you require a wider understanding, as reference to it is made in this document. Technical Reference Manual Ethernet | expansion card Basic operation and block diagram The figure below is a block diagram of the EthernetiCheapernet podule. ‘The main functional blocks are: ‘+ the net controller: Intel 82586 (LANCE) + the serial interface adaptor: Intel 82501 (SIA) + wansceiver: Intel 82502 ‘+ attachment unit interface (AU!) socket (D-type) + isolation transformers and power supply + bus butlers and transceivers + the FAM butter + the RAM page register + a PROM based ‘extended’ podule ID. + the control register ‘+ the PAL based state machine. Figure 1: Ethernet | expansion card block diagram eo) RAM DATA aUS 00-15 Ba 30k X16 Sha | | { west, fate 5 | eo RAM ADDRESS BUS Pooue bus Part 2- Interface cards STATE, wine] 12¥| tov ——} LU pc-re sy ov 10 BASE 2 A00.15) BNC. > o2see | leasor_ HEL easoo} fo] Lance | Sta Cad 20mHZ (sway D) Issue 1, November 1990 24AAs00 1 200 The Intel chip set AAs the Xerox and !EEE standards have become widely ‘accepted, a number of systems companies have produced VLSI devices that considerably reduce the design effort required to implement a connection. The most notable of these are by Advanced Micro Devices (AMD) and intel. ‘The intel chip set comprising the 82586 local area network ‘coprocessor, the 82501 Ethemet serial interface, and the £82502 Ethernet transceiver chip has been used inthis, design. “The 82586 and other similar local area network controllers are generally referred to by the acronym LANCE, even though this is a trademark of AMD. ‘The 82586 LANCE performs media access control, {raming, pre/postamble generation and stripping, source address generation, CRC checking, and short packet detection. In addition diagnostic functions such as Time Domain Reflectometry (TOR) can be performed. The 82501 serial interface adapter (SIA) performs Manchester encoding/decoding, receives clock recovery and directly drives the attachment unit interface (AUI) to the cable mounted Ethernet transceiver. In addition the 82501 operates a watchdog to prevent continuous. transmission (a fault condition), and provides a loop-back test facility. A second source for this device is SEEQ who ‘manufacturer a similar part, the DQ8023A, This part however is nat identical and will not perform TDR correctly. ‘The 82502 transceiver applies transmit data to, and removes receive data from the Cheapemet cable interface. This devices performs a similar function to the cable mounted Ethernet transceiver. The dual port memory The LANCE is a true coprocessor and is designed to perform scatter-gather DMA. in common with other LANCE chips the 82586 wil uilise a significant bus bandwidth when operating on a net running at 10 Mbps (note: this is not simply the serial data rate divided by the parallel bus width), This bandwidth cannot be provided by the ARM processor over the podule bus and so a dual-port memory system has been implemented. All communication between the ARM and the LANCE is carried out through command blocks in the dual-port RAM {there are no visible registers in the 82586 LANCE). These ‘command blocks and associated data structures are defined and described in inte's data sheet. Toissue a command to the LANCE the ARM appends the ‘command to the command block lst (CBL) in the dual-port RAM, Itthen raises the channel attention (CA) signal othe LANCE signaling the presence of the new command. The LANCE responds to CA by reading the command from the BL and executing as required. The LAN Components User's Manual contains a considerably more detailed and comprehensive description of the operation of the LANCE, 22 Issue 1, November 1990 Technical Reference Manual The control register ‘The control register contains four bits Reset (RST) Bit 0 This bit controls the RESET pin on the LANCE. This bits set (LANCE reset) on system power-upihard reset or writing tothe control register with this bit logic 1. Ths bit is cleared (and the LANCE released from the reset state) bby writing to the control register with this bit logic 0 Loop-Back (LB) Bit 1 This bit selects the loop-back mode of 82501 SAI chip. This bitis set and the SIA chip put into loop-back mode by the ARM writing tothe control register with this bit ogi 4. This bitis cleared (SIA taken out of loop-back mode) ‘on system power-upvhard reset or writing to the control register with this bit logic 0. Channel Attention (CA) Bit 2 ‘This bit generates a correctly timed CA pulse when the ‘ARM writes to the control register with this bit logic 1. No CA pulse is generated ifthe ARM writes tothe control register with ths bit logic 0. Clear Interrupt (CLI) Bit 3 This bit clears the podule interrupt lag and removes the podule interrupt when the ARM writes to the control register with ths bt ogic 1. The podule interrupt and flag are unattected i ine ARM writes tothe contol register with this bit logic 0 Each bitin the control register isnot independent and ‘when writing toa particular bit, the remaining three must be valid. The remaining 12 bits are ignored by the hardware (2er0 is recommended). Podule identi PROM The padule identification PROM contains the following information: + the Acorn podule identity number (03) + the interrupt (IRQ) flag bit + the PCB revision number + the six byte IEEE globally assigned address block +a CRC to allow the PROM to be validated The contents and operation of the interrupt flag are described in Interrupts in Detailed description below. Detailed description Address map The Ethernet | expansion card address map (offset relative to slot base) is shown in Table 1 below. The RAM buffer occupies the upper haif of the podule address space. The ID PROM, page register and control register occupy the lower halt. Part 2- Interface cardsAsoo 1 200 ‘The LANCE The 82586 LANCE is a ‘scatter-gather’ DMA controler type device and is designed to intertace to 80186 type processors using a HOLD/HOLDA protocol to resolve arbitration for access to shared memory. ‘The ARM podule bus cannot easily support a HOLDIHOLDA type interface. This is because the ARM is ‘dynamic device and cannot be stopped forthe required time. (This can be longer than 10 ns during the intertramevinterpacket spacing time.) The ARM cannot be siven priority and HOLDA deasserted because this will result in the net controller failing to meet the timing requirements ofthe net protocol due tothe increased bus latency. For example, this could resultin the failure ofthe net controler to take part in the back-off and retry sequence following a collision on a heavily loaded net. In this design HOLD and HOLDA are wired together and ‘ARM cycles cause wait states to be inserted into the LANCE bus cycle. This is achieved by removing the READY signal to the LANCE while the ARM is active. Technical Reference Manual ‘Adopting this scheme avoids the problems outlined above. The ARM is never stopped and the LANCE sees minimal bus latency. ‘The LANCE ARDYISRDY input used can be programmed to be either asynchronous! ARDY and internally synchronised, or synchronous/SRDY and ‘externally synchronised. In this case itis SRDY mode ‘that must be selected. This is achieved by issuing a configure command with the ARDY/SRDY bit set to logic 1. This is important as the LANCE powers-up in ARDY mode In certain circumstances the LANCE needs to perform read-modity-write bus cycles with lockout. Using READY to insert waltstates does not allow this. However lockout is only required when the LANCE updates error counts (statistics) and even then a problem only arises when a count overtiows and the ARM resets ito zero while the LANCE is in the modily phase of a read-modity-write cycle, This is solved by the ARM reading back the count after it sels it to zero. Ifthe count is stil indicting an overflow then a read modify-write cycle was in progress Table 1: Ethernet | expansion card address map READ warre | PAGED PAGED 4Ke | Raw Raw | 2 byt ID PROM GUTCA [eB [Ast] Cont Register i pra]pnelpni leno] Page Resister IDPROM (Base) = Slotbase _(Type 3 access) + 0x0000 (Read oniy) Page Register lot base (Type 2 access) + 0x0000 (Write only) Contro| Register Slot base _(Type 2 access) + 0x000¢ (Write only) Dual Port RAM lotbase (Type 2 access) + 0x2000 (Readiwrite) Part 2 - Interface cards Issue 1, November 1990 23[Asoo / 200 land the ARM has to correct the count. Error counts this high indicate a major problem that will require correction so should be a rare event. ‘The memory bus of the LANCE is operated in ‘minimum ‘mode’ asthe timing parameters for LANCE outputs inthis mode are subject to less spread between devices. The pull-up resistors on WR", RO°, and BHE are required to prevent RAM cycles when the LANCE is inactive. The LANCE communicates directly with the SIA (IC24) Via a serial channel comprising seven signals: TXC, TXD, XC, RXD, RTS, CRS and CDT. The function of each of these is described in the LANCE data sheet. The Clear- to-Send (CTS*) input is not supported by the SIA and is connected to OV (enabied) Dual port RAM ‘The podule bus provides only a limited space in the ‘address map (8 KB) for each podule. This is insufficient ‘and so a paged scheme has been implemented. Viewed from the ARM side the RAMs are paged into the top half of podule space by a ‘page register. The four bit ‘page register is split across two PALs (see the section The PALs below). Sixteen pages each of 4 KB provide 64 KB in total. This is organised as 32 k x 16 bits (two 32 kx 8 static RAMs). An alternative RAM size of 8k x 16 bits (two 8 k x 8 static RAMs) can be supported (see the section Links below), ‘The podule address bus (LA2-13) is buffered by two HCT244 (1066 and IC5B) and the podule data bus (BDO- [BD 15) is butfered by and two HCT245 transceivers (IC15 and IC54). The direction of the data bus transceivers is determined by the podule RiW signal, while both output enables (AAOE and BDOE) are generated by the bus ‘control PAL (IC36} Viewed from the net controler side, the FAM willbe ‘contiguous from location 0x0000 to OxFFFF. The initialisation root for the controller is OxOFFFFF6 which is mapped into the RAM at OxFFF6, The high order address bits are not decoded. The LANCE addressidata bus (ADO-AD15) is demultiplexed by two HCT245 (IC17 and 1622) which use the LANCE ALE signal to latch the address bus. The data bus only requires buffers and two HCTS73 transceivers (IC10 and 1032) are used. The direction of the data bus transceivers is determined by the LANCE DT/R signal while the output enables are generated by the bus control PAL ((C36), ‘The LANCE is capable of operating on an eight bt bus land is reset to this made. The LANCE initialisation root (read when released from reset) contains a bit that defines the bus width and this must be set to 0 (=16 bit bus). Until the LANCE reads this it deasserts Byte High Enable (BHE") and outputs address bits on AD8-AD15 {or the entire cycle. To avoid a bus clash BHE* is used to disable the high order data bus transceiver via the bus control PAL (IC36). 24 Issue 1, November 1990 Technical Reference Manual (Once initialised to a byte wide bus the LANCE only ‘operates on half words (never bytes) so it not necessary to decode the least significant address bit (ADO) to produce separate write strobes for each byte. Podule identification PROM The device used is a 32 byte PROM 271819 (IC14) ‘Typical content of an ID PROM is shown in Table 2 overieat The ID PROM shares address and data bus butters with the RAM. Viewed from the ARM side the ID PROM is byte wide and word aligned. ‘The podule specification detines two bits inthe ID byte to be interrupt flags. This design requires oniy 1RO imerrupts so the FIO flag is always zero. The IRQ lag is ‘generated by connecting the podule interrupt signal tothe ‘most significant address pin. The content of the upper half i similar tothe lower half but has the IRQ flag bit set, inthis way the interrupt flag is muttiplexed ‘into’ the ID byte. Bytes 09 - OE are the six byte Ethernet address unique ‘across all Ethernet equipment from manufacturers worldwide, ‘The CRC (Bytes 1C - 1F) is calculated on the rest of the PROM (Bytes 00 - 1B) using a 32 bit Autodin - | CRC. polynomial. This is the same algorithm as the LANCE Uses to perform multicast address fitering (see the ‘section PROM CRC calculation below). Since each PROMis unique the CRC is used to perform verification. ‘The output enable is generated by the bus control PAL. (1c36). The PALs Three PALS are used in this design: + the main state PAL (IC29) + the interrupt and channel attention PAL (IC78) + the device enable control PAL (IC36), ‘The main state PAL (128) Thie PAL implomonte a state machine which provides timing information for the other two PALS in the design. Inaddition it produces the two least significant bits of both the page register (PRO and PRt) and control register (RSTO and LOOP), ‘The interrupt and channel attention PAL (1C78) This PAL implements the two most significant bits of both the page register (PR2 and PR3) and control register (CL and CA), The device enable control PAL (IC36). This device decodes the address map to provide various device output enables, Part 2- Interface cards[Asoo / 200 ‘able 2: Podule identity PROM Technical Reference Manual 7] 06] 05] «| 03] 02] 01 ] oo] NOTES: wielelejcfelelefe]| ‘| “ lelelclelelelelc > leleletetetete e| GRC on bytes 00-18 [se le[ele[ele|[clele 18 Bytes 11 10 1B = 00 (01 no FIGs, IRQ= 1 00-RSVD Unique 1D 09 00 (01 - POB rev. eg one | (00. UK Aeon Ethernet 00- RSVD (0 - no boot code 00- no FIQs, IRQ = 0 Part 2- Interface cards Issue 1, November 1990 25(Asoo 1 200 The state machine and operation The state machine has four states; IDLE, SA1, SA2, and SAS and is clocked from state to state on the falling edge of CLK, the 8 MHz podule bus clock. The figure below is the state diagram. The idle state The state machine enters this state on power-up, hard reset (RST* low), or from the SA3 state. In this state the bus buffers on the ARM side of the dual-ported RAM are disabled and those on the LANCE side enabled. Other ‘outputs such as the page and control register bits remain unchanged. The state machine remains in the idle state until the ARM starts an access (podule select - PS active). ‘The SAI state This state is entered from the idle state only. In this state the LANCE READY signalis disabled, forcing the LANCE to insert wait states if itis active on the bus. The RAM write strobe (RAMWE" is disabled to prevent writes while the LANCE side of the dual-port RAM is disabled and the ARM side enabled. The state machine exits to the SAZ state unless a reset occurs. The SA2 state ‘This state is entered trom the SAt state only. In this state the ARM access is performed and the corresponding device enables are active eg, it a RAM write is performed then the RAM write strobe (RAMWE")is active. Similarly iffa RAM or ID read is required than the RAM or IDOE is active. Writes to the page register or control bits are also Technical Reference Manual performed during this state. READY is still inactive. The state machine exits to the SAS state unless a reset occurs. ‘The SA3 state ‘This state is entered from the SA2 state only, The RAM write strobe (RAMWE")is disabled to prevent writes while the LANCE side of the dual-port RAM is enabled and the [ARM side disabled. The state machine exis to the idle state where any LANCE acoass that was in progress is ‘completed, Podule bus cycles ‘The podule specification requires all ID PROM access to bbe made using type 3 (sync) !OC bus cycles. All other ‘accesses to the Ethernet podule must be made using type 2 (fast) OC cycles. Figure 3 overeat illustrates a readiwrite to RAM wrile the net convolleris active. The cycle starts with podule select (PS) active and puts the state machine nto the SAt state ‘on the next clock edge. A description of each state that follows is given above. It should be noted that Ready is aways deasserted for three cycles, even ifthe LANCE is ile, A podule bus ‘access can ‘colde' with a LANCE access in ive diferent ways, depending on what state the LANCE is in when the ppodule bus access starts. These are: PS" while the lance is in states T1 to T4 or idle. The actual number of wait states that the LANCE will insert depends on which of these cases apply. Figures 4, 5, 6 and 7 ilustrate the possible cases, Figure 2: State diagram 26 Issue 1, November 1990 Ast IDLE Part 2- Interface cards[Asoo / 200 Technical Reference Manual Figure 'ypical podule bus cycle ARM FAST CYCLE | sm | a fale | 2506 ovcue [ote | re jw [we | wo] 73 | 4 | STATE MACHINE | wLE | wLE | sar | saz | SAB | IDLE | 1OLE | OLE | CuK TFLF LIL Ld J TLI1S1 Bs = ee Ri ——__- we I wi ss READY, ——.~ _~ ~ ¥— oes OO 00-18 (wAITE) DATA |AD0-15 (READ) DATA NeMOR ARE | Ns RAM ADDRESS ‘AD BUS. ‘AD BUS e001sqwaite) | <> 20016 READ) OL me ree RAM DATA BUS: - ‘AD BUS" ‘BD BUS ‘AD BUS ri | Wao | aan AaIIOE | woe PRO, LOOP, ASTO. OLD VAIUE Xr | CA, CLRINTO iY — Part 2 Interface cards Issue 1, November 1990 27Asoo / R200 Figure 4: Access coll ARM CYCLE 82586 CYCLE STATE MACHINE READY RAM DATA) ADDRESS Technical Reference Manual In cases PS* while LANCE is in T1 erated Je | re | twa rwol to | te | rove | sar | saz | sas | mLe | PS* while the LANCE is in T1 ‘The LANCE samples READY deasserted at the ond of T2 (SA2), and then again at the end of TW1 (SA3}, so in this case two wait states are inserted. 28 Figure 5: Access collision cases PS* while LANCE is in T2 ARM CYCLE 82586 CYCLE STATE MACHINE READY RAM DATA ADDRESS | sur [aja le | fom | [rw | we fre | ve |e | | ote | sat | sae | sas oe | ne "=e ew ae Xi PS* while the LANCE Is in T.2 ‘The LANCE samples READY deasserted at the end of T2 (SA), TW1 (SA) TW2 (SA3), so the maximum of three wat states are inserted, Issue 1, November 1990 Part 2- Interface cards‘A500 / R200 Technical Reference Manual Figure 6: Access collision cases PS* while LANCE is in T3 fe | om Ja fale ewome [1 |r| wl ulin [el wu STATE MACHINE | wre | sar | saz | sas | tue | READY. a VL ; . RAM DATA nce aa ADDRESS a PS* while the LANCE is in T3 In this case READY is stil active when the LANCE samples it at the end of T3 (idle). This is the last time that the LANCE does this for the current cycle so the LANCE cycle completes before the podule bus cycle starts. Note that the LANCE is not active on the RAM bus during T4. Figure 7: Access collision cases PS* while LANCE is in T4 ieee ee eee aed easoscrae | T| | 3 | ™ | om ml m| rm] | ‘STATE MACHINE | | wore | sar | saz] sas | rove | READY = — RAM DATA’ PaDRESe LANCE ARM PS* while the LANCE is in T4 Since the LANCE does not require the bus during T4 no further wait states are inserted in the current cycle. However Tt of the next cycle could follow T4 and ‘one wait state willbe inserted into this LANCE access, Part 2 - Interface cards Issue 1, November 1990 29PS* while the LANCE is idle Ifthe LANCE remains idle while the podule bus cycle ‘occurs then there is no collision and the LANCE ignores the READY signal. This case is not ilustrated ‘A.ead trom the podule ID PROM or write to the control or page register is similar to a RAM cycle. To simplify the ‘bus design the LANCE is removed from the RAM buses during cycles to these devices. Bus design note ‘The cycle stealing scheme should guarantee that the LANCE never has insulticient bus bandwidth or sees excessive bus latency to the extent that it cannot service the net or fails to meet the IEEE timings. Even when the ‘ARMM continuously accesses the RAM. The following ives the reasoning behind this statement: ‘Assumptions: Net Clock = 10MHz Bus Clock = MHz LANCE FIFO size = bytes HOLDA is wired to HOLD so: Bus Latency = Deycles IEEE Interframe Space Time = 9.6uS Criteria: 1. FIFO must not over/underrun. FIFO filvempty time from serial side: = 8 (bits) * 16 (bytes) * 100-9 (bit time) = 1284s FIFO omptyiil time from paralel side: = 8 (Word transfers) * (4 (standard 8 MHz cycles) + Nwait (wait cycles) “1256-9 = 4us (it Nwait = 0) 7s (it Nwait = 3) 8s (if Nwait = 4) 2 The LANCE must be in a position to transmit by the tend of the interframe spacing time. With a FpIFs ratio of 8 MHz/10 MHz (0.8): 16°Nwat + Nlatancy must be less than or equal 1080. it HOLDA = HOLD then Nlatency = 0 and Nwait <= 5 So this strategy works if we can keep the number of wait states (Nwait) less than or equal to five per access. In the ‘current design three are used and this is unlikely to change. Interrupts ‘The podule interrupt (PIR) is level triggered. However, the interrupt signal (INT) from the LANCE is designed for Use with edge triggered interrupt controllers. Ifthe net controller detects a second interrupting condition just after the firs is raised, it will drop and reassert INT. The situation could arise where the podule manager (software) may scan the slots and find no IRA flag set The above problem is prevented by latching INT in the interrupt and channel attention PAL (IC78) and using the latched signal INTO to generate the flag, The clear interrupt (CLI) bitin the contro! register is used to clear the latch, Latching INT introduces another problem, which is eliminated by a feature of the 82586 LANCE. If a second interrupt occurs after the processor has read the status word in the SCB, but before the first is cleared, then the second interrupt would be missed. However, ifthe interupt is cleared at the same time as the channet attention (signalling the acknowledge command) is issued, the LANCE will respond by deasserting INT and reasserting ithe second interrupt was not acknowledged because it was missed. It is recommended to set CA whenever CLI is set Figure 8: Example interrupt cycles UU wo SO LS Pirro Ay LATCHING als 8) CLEAR INTERRUPT Issue 1, November 1990 JUL “\S ee C7 ~\L ie ©) EDGE SENSITIVE Part 2- Interface cardsTechnical Reference Manual Figure 9: State diagram for INTO/PIRG* ooo iz >) scr ores — we ; oo INT INTEN OLE Figure 10: State diagram for INTEN* INTO [ enasteo r a DISABLED H Part 2- Interface cards Issue 1, November 1990 241(Asoo / p20 Links ‘The Ethernet I PCB should be viewed from the ‘component side withthe 96 way podule bus connector on the loft and the rear panel on the right. When viewed like this, west isto the left, east the right, north the top and south the bottom. LK1 and LK2 select the RAM size 32 KB devices are fitted (normally) the links should both bbe south. 8 KB devices will not normally be fitted but in this case LK and LK2 should be north. LK3 to LK8 select Ethernet or Cheapernet. For Ethemet operation the links should be west (ink pin ato pin b). For Cneapemet operation the links should be east (link pin b to pin) LK9 is tracked south and not fitted on production units. ‘See data sheets for the 82502 for use. PROM CRC calculation The following is a code fragment inthe C programming language that calculates and validates the Ethernet PROM checksum, Technical Reference Manual 212 Issue 1, November 1990 Part 2- Interface cards(Asoo 1 A200 Ethernet Il expansion card “The IEEE 803.2 standard supports two different versions for the media ‘+ 10BASES (commonly known as Ethernet) + 10BASE2 (thin-wire Ethernet, or ‘Cheapernet’). ‘These can be used separately, or together in a hybrid form. Both versions have similar electrical specttications land can be implemented using the same transceiver Cchip. Thin-wire Ethernet is the lower cost version and is user-installable. Main differences are in the segment longth, network span and nodes per segment, with thin- wire Ethernet having only one-third ofthe performance. ‘The capacitance per node and the cable cost are however much less. ‘The Ethornet expansion card has been designed to provide the physical and media access control layer functions of the local area network as specified in IEEE 802.3 standard, This standard is based on the access ‘method known as Carrier-Sense Multiple Access with Collsion Detection (CSMA/CD). In this scheme, if a network station wants to transmit, it fist ‘listens’ to the ‘medium; if someone else is transmitting, the station deters until the medium is clear before it begins to transmit. However, two or more stations could stil begin transmitting at the same time and give rise to a collision. When this happens, the,two nodes detect this condition and back off fora random amount of time before making another attempt System considerations Bus Latency is the maximum time between the NIC (Network interface Controller) assertion of BREQ and the ‘system granting BACK. This is of importance because of the finite size of the NIC’s FIFO, If the bus latency becomes too great, the FIFO overflows during reception, land becomes emply during transmission. The Bus Utilization isa fraction ofthe time the NIC is the master of the Ethemet podule internal bus, and this should be minimised. The lowest bus utlization occurs when the bursts of data across the podule interface are as long as possible. This requires the threshold as high as possible, ‘and EmpiyiFill mode is used. The determination of the. threshold is related to the maximum bus latency the system can guarantee. ‘A DMA set up and recovery time is associated with each burst, hence when longer bursts are used, less bus ‘bandwidth is required to complete the same packet. Hardware overview The Ethemet Il expansion card has been designed around the National Semiconductor Chip Set. This provides all the functions necessary to implement an IEEE 802.3 (Ethernetthin-wire Ethernet) interface on @ host computer ora peripheral device. As there is no direct DMA memory path across the podule bus, data is Part 2- Interface cards Technical Reference Manual transferred via a static RAM local butfer. Since both the ‘ARM and the DMAC will have access to the Ethernet Il ‘expansion card internal bus, some arbitration is required. Dual-port memory equivalent This configuration makes use ofthe NI's emote OMA capabities, and requires only a local bufer memory ang 2 bidirectional YO port. The high prioniy network ‘bandwidth is decoupled from the system bus, and the systom interacts withthe local butfer memory using a lower prion bi-directional VO por. When a packets received, the local DMA channel rater tito the buffer memory, part of which has been configured as the receive butter ring. The remote DMA channel ransters the packet on a byte by byte basis to the VO port. At this point the data is ranslered trough an asynchronous protocol into main memory. Remote DMA The remote OMA channels work in both directions; pending transmission packets are transferred into the local buffer memory, and received packets are transferred out ofthe local buffer memory. Transfers into the network memory are known as remote write operations, and transfers out ofthe local butter memory ae known as remote read operations. A special remote read operation, Send Packet, automatically removes the next packet from the receive buffer ring. Both the starting address and the length are set before initiating the remote DMA operation. The remote DMA operation begins by setting the appropriate bits in the Command Register. When the remote DMA operation is complete, the ROC bitin the Interrupt Status Register (ISA) is set land the processor receives an interrupt, When the Send Packet command is used, the controller automatically toads the starting address and byte count from the receive butter ring for the remote read operation. Upon completion t updates the boundary pointer for the receive tour ring. Only one remote DMA operation can be active at any time, Hardware components ‘The Ethernet Il expansion card can be divided into five ‘major blocks ~ see the circuit block diagram below. The five major blocks are as follows 1 Decode and cycle access control: Carrying out address and register decoding, control ofthe local butfer(laiched or transparent mode) and all the required readiwrite signals. The type of access cycle required may be extended if bus arbitration is needed 2. Podule and Ethernet identification: ‘A PROM containing the ID of the type of podule (expansion card) thats fitted, with the address of the Issue 1, November 1990 243(AAs00 / 200 Interrupt location, the Ethernet ID of the particular ‘board (each PROM is programmed with a diferent number) and required driver code to run under RISC (OS. Itis page addressed by writing to ‘mode’ latch. ‘System reset sets to page zero. 2 Data Butter: Static RAM memory. Memory access is completely Technical Reference Manual 4. NIC controler: Provides the required data rate with a minimum of control overhead. This is a key element in the design. ‘Once set upit performs many ofthe Ethernet functions, without requiring processor help, only producing an interrupt when a packet has been completely received or transmitted controlled by the NIC controller which performs the «8 IEEE802.3 Intertace Components: memory management. Data is ransterred between Providing the Manchester ancoding/decoding, high the controler and SRAM using local DMA, and voltage isolation and line drivers forthe thin-wiro between the SRAM and the PORT by remote DMA Ethernet interface Ethernet block chagram aa oma (i50) Be Poagoid | age some tie cyieacse crane ine ane" = we varie, r ea a 7 Controter 214 Issue 1, November 1990 Part 2 - Interface cards[Asoo / 200 Circuit component details Decode and cycle access control ‘The Ethernet Il expansion card has hardware in both podule space and Module space. The podule section Consists of the ID/RISC OS driver EPROM, the interrupt status register and the EPROM page register. The podule hardware is kept isolated from the Module hardware so that aocesses to the Interrupt Status Register and Page Register do not atfect any DMA transfers in progress on the Ethemet podule intemal bus. ‘The podule memory map is shown below: ‘aaaressPo | tia] U2 use axusoo | 1 | 12 WHITE ae csscamoo | 1 | 0 WRITE not antes READ rept satus oaoaro00 | o | 1 arsaoo0 | o | 0 PROM ‘The Interrupt Status register is as follows: wos y Neue page register is not cleared by the ‘software internal fe 2k The page register is as follows: oe x - — ——— bts ‘Srst (active low) ‘When the Ethernet il expansion card generates an bat interrupt, the ‘podule manager’ will interrogate the status pu Invesco bo ARM neem | SE: FRU SRE, ‘controler and the data transter YO Port. When a local be EPROM Face across Bt DMA transfer between NIC and SRAM is in progress, the BS o> EbRoMpebe sarees manner, simply by reading and writing to them. All moe EPROM page adress bx Strand eg ares oe Ere The ne £6 reget roma acted ura poner Part 2 - Interface cards Issue 1, November 1990 2415 Tech al Reference Manual file length in 16 bit wide words. The individual bytes being transferred automaticaly between the Port and Network via the NIC and SRAM. The Module memory map address is shown below: ‘aires Po | tia] U2 ee oxoogmco fr ft NC conto: Bang AS LAZ ovoozme | 1 | o Data vanster v0 Port eao000 | o | 0 Podule and Ethernet identification ‘The IDIRISC OS river PROM has been laid out to give {rom 8kB to 512kB of code space. The host cannot directly address the full PROM and therefore is operated in a page mode by writing the required page to the page register. The page register is set for page zero by power ‘on reset. The top two bits of the page register being used for Lr_w (access to the VO Portis set for reading or writing a packet) and ‘Srst’ (software internal reset). TheAAs00 200 Local Buffer Memory ‘The butter memory consists of two Bk x 8 (up to $12k x8 for SRAM source flexibility) static RAMs which give a 16 bit data transfer across the podule interface, hence maximizing the podule bandwidth. The data butter is, ‘completely controlled by the NIC controller. which performs all the memory management in a ring butter format. Pointers to the memory are updated as required (but can be accessed via the NIC registers i necessary). ‘The data buffer is transparent as far as data transfers, across the podule interface are concerned. NIC Controller ‘The National Semiconductor Network Interface Controller provides all the functions necessary to implement all Media Access Control (MAC) layer functions for transmission and reception of packets in accordance with the |EEE 802.3 standard, All bus arbitration and memory support logic and two DMA Channels are integrated into the NIC. The local OMA channel transfers data between the internal controller FIFO and local memory. On transmission, the packet is, transferred from local memory to the FIFO in bursts. Should a collision occur, the packet is re-transmitted with ‘no processor intervention. On reception, packets are transferred from the FIFO to the receive buffer ring. A remote DMA channel is provided to transfer between local butfer memory and system memory Full details for ‘operating the NIC are contained inthe data book (see the Bibliography at the end ofthis section). 1EEE802.3 Interface Components These are the components concerned with the Etherne/Thin-wire Ethernet interface. They include the 20MHz oscillator (providing the required transmit and receive clack), the Manchester encoder/decoder, DP8391 (to produce the required signals), the transceivariline drivers,DP8392 (required to provide thin- wire Ethernet signals) and components to provide isolation such as the DC to DC convertor, line transformers, termination resistors, capacitors and a diode as required. PALs ‘There are four PALS used + Decode + Intout + Memepal + Natfix. Decode (0273,271) As its name suggests, this PAL decodes podule and module addresses to produce chip select signals. It enables reading of the EPROM, writing to the page register, reading interrupt status, and readiwrite ‘operations to the NIC controller main podule interface ‘unctions. It also defines whether podule or DMAC have control of the bus. The PAL's function is shown by the state flow diagram below. 246 Issue 1, November 1990 Technical Reference Manual Intbut (0273,272) ‘The ‘ntbut PAL, in conjunction with the ‘memcpa’ PAL, form the core tothe Ethernet podule bus arbitration logic. Intbuf produces the interrupt control and al the functions required to control the VO Port (HCTB46s, which are used in both latched and transparent mode, depending on tho type of access active). Memepal (0273,273) ‘Tse ‘memepal’ PAL, working in conjunction with the intbut’ PAL, produces all the podule interface (MEMO) required read and write pulses. The Ethemet controller hhas two main modes of operation - Bus Master (while performing DMA) and Bus Slave (while its internal registers are being accessed. These lwo modes require two differe types of access cycle (a different bus arbitration is used). Within these two modes a read or a write cycle may be in operation. The PAL's function is shown by the state diagram overiaat ‘The internal reset will set this PAL to the ‘Il’ state. It remains in this state until a MEMG cycle is decoded. From the ‘idl’ state it may enter one of four states: + Slave Read + Slave Write + Master Read + Master Write (On enty to one of these states, a complete cycle will {ollow. Whichever state ithas entered, twill remain in that state while the bus arbitration function is completes. ‘Once access has been granted, the cycle continues, producing read or write pulses and MEMC signals (including waiting during interrupts) as required. Natfix (0273,274) The National Semiconductor NIC Ethernet controller requires care to be taken when trying to access its internal registers via the control signal Chip Select, The PAL Nattix is used to monitor the controller's use of the bus and then hold back any access to the registers while the controller is using the bus. It similarly holds back the controller during a ragister access, and has the effect of ‘making sure that Chip Select doesn't bacome active on a rising edge of the 20MHz clock. Part 2- Interface cards(Asoo 1 200 ‘Summary ‘The Ethernet Il expansion card hardware design tries to be as transparent, in terms of data transfer, as possible. Where design requirements have allowed, flexibility has been given to the way the software can use this hardware platform, at the same time trying to maintain minimum system overhead. Much of the flexibility of the design is ‘achieved by the use of the DP8390 (NIC), which is a ‘complicated device containing several internal registers allowing software to dictate operation. Therefore access to the Etheret/Cheapernet LAN is achieved by software tivers that firstly prime the device by direct access and then leave the expansion card to run free, requiring only burst data transfers across the podule interface, an interrupt being used when intervention is required. Technical Reference Manual Bibliography ‘The following publications will bo of interest 0 tectricians and users wanting find out mare about Ethemet and the Acorn Ethemet I card + ANSVIEEE Sts 602.3 - 1985 ISO drat Intemational Standard 880213 ISBN 0:471-82749:5, Carter Sense Mutpie Access wi Colision Detection (CSMAVCD) access method and physical layer specifications + National Semiconductor datasheet fr the DPE390C NIC. Inthe National Semiconductor Data Communications, Local Area Networks and UARTS ‘Aévanced Peripherals Handbook, avalable rom National Semiconductor (UK) Lid, 201 Harpur Cente, Home Lane, Bediord MK40 1TR. + ‘Acseries Poduies’, specification issue 2.0 available as an application nate from Acorn Computers Limited {address at the front ofthis marwal) EthernetCheapernet links Part 2- Interface cards OLs ——I t | fiji Sn: lo py Let (l Soe StH T Vy Us Us Ut XB UC US Issue 1, November 1990 247(Ass00 / 200 SCSI interface Overview Workstation models which provide a SCSI interface do so by means of a SCS! expansion card (Podule) plugged into an expansion sict in the backpiane. ‘Tho Small Computer System Interface (SCS) is a high- speed interface for use mainly with mass storage devices such as hard discs, tape drives or CDs. itis an asynchronous bus capable of data transfer rates up to 4MB per second, The bus cable is a 50 way cable consisting of: + 30 Ground wires + 9 Control signals + 8 Data signals + 1 Data parity signal + 1 Terminator power line +1 Not Connected. ‘The pin allocation forthe two standard SCSI bus connectors can been seen on the schematic ‘Communication on the bus is between two devices, an initiator and a target. In the most common case the initiator will be the host computer and the target willbe a hard disc drive. The first task forthe initiator isto select the required target. There can be up to eight devices on a single SCSI bus, each having its own unique select code. This select codes simply a different single bit ofthe data bus allocated to each device on the SCSI bus. Generally the host computer uses select code seven (data bit 7) and the first target will use select code zero (data bit 0). Having selected its target, the host then transfers a small ‘group of bytes known as the Command Descriptor Block (CDB) to the target. The CDB defines the action to be taken by the target. In the case of a disc drive this will usually be to send some data to the host, or to receive some data from the host and write it onto disc. The SCSI bus will go through many ‘Phases’ during the ‘execution of such a command and the target may even release the bus (or ‘Disconnect’ during the execution of command (for example if a ‘Seek’ is required by a hard disc drive), thus allowing the host (or initiator) to initiate ‘commands on other targets, The complexities of SCSI Bus Phases, handling target disconnections ete, can be all taken care of by single chip SCSI controllers. For further details of the functions of the SCSI bus, refer tothe ANSI Standard X3.131-1986 and the data sheet for the SCSI controller used in the Acorn SCSI expansion card (see the Bibliography) 248 Issue 1, November 1990 Technical Reference Manual Circuit description of the SCSI expansion card (Issue 2+) Maximum performance is achieved from the Acorn expansion bus by the use ofthe STM (STore Multiple) ‘and LDM (LoaD Multiple) ARM assembler instructions to transfer data to ard from a peripheral device. These instuctons, coupled with the fulluse ofthe 16 bit VO data bus, wll provide a maximum data transfer rate of 8 MB per second, Unfortunately these commands cannot be Used o transfor data to and trom the SCSI controller chip directly, Because it cannot be predicted whether or nat the WD33C33A (the device used in this design) can accopt or provide the mandatory number of bytes for the relevant instruction Furthermore, the WD33C93A is an 8 bit device, hence ‘some kind of funnel hardware is required to couple the 8 bit bus to the 16 bit /O bus. ‘The solution to these problems is to have butter memory fon the expansion card, accessible by both the WD33C93A and the ARM processor. This dual porting of the butfer memory is the most complex aspect of the Circuit and is therefore dealt with separately The main elements of the SCSI Expansion card are:- + Western Digital WO33C93A SCSI Bus Controller + NEG 71071 DMA Controller + two 32K by 8 bit Static RAMS + EPROM containing the diver software + four PAL devices controlling ARM access to the card + SCSI bus connector, termination resistor packs, and filters + data and address bus buffers and latches. The SCSI Expansion Card (SEC) has hardware in both Podule (expansion card) VO space and Module YO space. The podule section consists of the ID/RISC_OS. driver EPROM, the interrupt status register and the EPROM page register. This page register is also used for the SRAM (Static RAM butter memory) page. The podule hardware is kept isolated from the Module hardware to allow accesses tothe Interrupt Status Register (ISR) and the Memory Page Register (MPR) not to interfere with ‘any DMA process that may be taking place between the ‘SCSI Bus Interface Controller (SBIC) and the SRAM. ‘The EPROM circuit permits from 8 KB up to 128 KB of cade space, the top two bits of the MPR being used for interrupt enable (IE) and user reset (UR). The IE is 0 by default and has tobe set to 1 before any interrupts can be generated by the SEC. The UR biti also 0 by default and it set to 1 will cause the internal raset ine (IRST) in the SEC to become active. The DMAC has a minimum reset period of 21CYK (250ns) and the SBIC has a minimum reset period of tus. The MPR is not cleared by the IRST signal. A link option does allow the SCSI bus reset to control the IRST, should the card be required to act as a target. The SBIC will inform the host processor that a reset has occurred, Part 2- Interface cards‘Asoo / 200 “The final section of the podule hardware is the interrupt control logic. There are two sources of interrupts within the SEC, the DMAC and the SBIC. The DMAC will issue a terminal count (TC) pulse at the end of a data transfer which willbe latched by the ISR, and may be subsequently read at any time by the ARM processor. SBIC interrupts are latched within the SBIC, but can be ‘monitored in the ISR. DMAC interrupts remain latched Unt the Clear Interrupt (CLRINT) addross is written to. SSBIC interrupts remain latched until appropriate action is taken by the host. The two interrupt sources are Combined in a PAL to form a common PIRQ. The address map for podule slot 0 fast access is given below: asdrssP0 | LAI LAI? use | een UR. | eas 18 042000 1 0 ote CLRINT 1341000, G4 EPROM (Peas Ony) i 3940000 oo B_| UPR BA Alecaton ISA Bi Atoeaton aoe Higgs | eR eta, | TM ee Reis | (eee ; oaks [EPROMSRAM Page Across #0 Requesting IRO In Module address space the ARM has access to the SRAM via 2 16 bit data bus and addresses it as 16 4KB pages (8K addresses 16 bits wide, every sth address), Using the MPR located in podule address space. LLA2 of the podule bus is connected to AO of the SRAM, 0 thatthe lower 16 bits of the ARM registers will be stored in consecutive addresses when an STM instruction is used. ‘The DMAC and the SBIC are also memory mapped but only have & bit data buses. The DMAC has many registers which are normally accessed using address bits ‘AO through A7 of the host processor address bus. Due to ‘the tunnelling required to exchange data between & bit Part 2. Interface cards Technical Reference Manual and 16 bit data buses, the DMAC addressing has had to bbe mapped rather unusually. A1 through A7 on the MAG are connected to LA2 through LAB, and AO on the DMAG is connected to LAS. ‘Thus the mapping becomes: veneer | meg se || itn a me Hedees a | | ieee e | & | eee, Be | we | Be emeee m | ef eae eee eee ere a | ef | See a | gs | eee ‘The SBIC is used inthe indirect addressing mode where LAzis used as AOto select between control registers and the addrass register (see data shee!) When a DMA transfer between SBIC and SRAM is in progress, the ARM may stil access the DMAC, SBIC or SRAM in the normal manner simply by reading or writing tothe appropriate address. All arbitration required to gain ‘access to the SEC internal buses is carried out transparently by stretching the MEMC V/O cycle (see the due bus specification). In the case of an STM and LOM instruction only the first access is stretched to gain control of the SEC buses. The ARM will normally retain control of the SEC buses during video DMA interruptions. Module Address Map: TTT 7 | — / I mac. | LP ; | jews om | ‘99000000 o ° | ‘SRAM paging is exactly the same as EPROM paging. Component identification on the SEC EPROM address lines from the ARM podule bus are Unbuffered. This allows them to operate during DMA. The extra address lines are provided by the MPR (1017 Issue 1, November 1990 219(Asoo / £200 HCT273), which are directly connected to the EPROM, ‘out isolated from the SRAMs by IC3 (HCTS41). The EPROM (ICS) and the ISR (IC15, PAL 0273,215) also hhave an 8 bit data bus butter (IC2 HC245) separate from that used for the SRAMs, DMAC and SBIC. Again, this allows ARM access independent of DMA activity. IC4 (H0245) and IC6 (HC245) provide 16 bits of data bus btering for the SRAMs (IC13 and 1C11), as well as the DMAG and SBIC. IC7 (HCT573) is used to hold the upper 8 address bits for the DMAC during DMA transfers, and ICB (HC245) routes the data to the correct SRAM, depending on the state of AO. The DMAC ‘sees’ the ‘SRAM as 64K by 8 bits, whereas the ARM ‘sees’ the ‘SRAM as 32K by 16 bits. IC17 (uPD71071) is the DMAC and IC16 (WD33C99A) is the SBIC. All address decoding is taken care of by IC9 (PAL. (0273,216). The task of arbitration for access to the SRAM is shared by 1C16 (PAL 0273,213) and IC14 (PAL (0273,217), 1C18 (PAL 0273,219), and IC12 (PAL (273,218). IC15 [IC14] also generates the |OGT and BL signals required by the podule Bus, while 1C12 handles the VO and memory read and write lines (IORD, IOWA, MEMR, MEMW). There are various link options on the SEC and they are listed below: EPROM oz. EPROM KI LK2 ome co ie 88 wee 9k gen 8 E 0-Ope0 c- Closed tL Factory fitted links set the size of the Issue 24 POB to 27256. LLK6 and LK7 allow the OMAC to perform memory-to- memory transfers LKB and LKG allow for larger SRAM devices, but these could not be fully addressed by the ARM processor. LK10 and LK11 switch the reset line for initiator or target mode: Intator ° ¢ ter & 5 The PCB is factory configured for initiator mode. ‘The SCS! bus signals are connected from the SCSI bus ‘connector to the SBIC, via fiter capacitors clearly visible ‘onthe circuit board, The SCSI bus requires termination at teach end of the bus cable on all signal lines. These are 220R to +5 volts and 330R to 0 volts. Where no internal 220 Issue 1, November 1990 Technical Reference Manual ive is fitted, termination is provided internally by a plug- (on terminator PCB assembly, which is mechanically polarised. Power to these termination resistors is provided via diode D1, to allow target devices on the SCSI bus to power them should the initiator be switched off. The initiator may also power the terminators atthe far tend of the SCSI bus cable. Fuse FS1 limits the current to ‘a maximum of 1 Amp. TR1 provides an open-collector drive to the SCSI reset signal when the SEC is used in initiator mode, The SCSI expansion card state machine When the ARM system memory clockis run ata different speed from that of the VO clock, a period of synchronization (minimum 1 VO clock cycle) is required at the beginning and end of each VO cycle. These extra clock cycles cause the earlier SEC design to relinquish ‘and re-arbitrate for SRAM access on every register transfer of an STM or LOM command, degrading potential performance. The solution to this was to cause the Issue 2+ state machine to hold access to the SRAM for the ARM for a number of clock cycles after the Completion of the UO cycle. This allows for synchronisation clock cycies and wil, conveniently, span ‘video DMA interruptions too. Ths is achieved by the use ‘of a three bit counter builtin to the RWPAL and count ‘decode logic in the new PAL ADDPLUS. Figure 1 shows ‘two accesses to the SBIC. The first access is a write to the address register in order to pre-select a register. The ‘seconds a register read. Note that because LA13 is high the second access is an E-cycle, even though the ARM has control. Figure 2 shows an LDM from SRAM. Note that LAA13 is low throughout this command, When the ‘extended cycle is complete the RW_DN signal is activated and the counter starts to count from zero again. However, each time an IORQ is received, itis reset to zero. Hence we see the counter oscillating between zero and one until the end of the LOM, when it counts out 10 seven, and the bus contro is relinquished. Figure 3 shows an STM spl up by video DMA accesses and the counter reaching a higher count before being reset to zero. Part 2- Interface cards[Asoo / R200 Technical Reference Manual Figure 1 FADE Ting verre nerters [Tine] t tig ms fecumiste to tig (205) at eer) Tineroiv (300s ] —detey [150-05] ° Figure 2 Tiniag veto ravers [line] te tig [ET] 1a ws fccamiate wing (ama) m [Caner ine [S05] oot C67] ° Part 2- Interface cards Issue 1, November 1990 221(Asoo 1 200 Technical Reference Manual Figure 3 RCE Lng Havers teres 0 ris SH 1s fevutete (GEE}o tw tug (3.2@05} at re tine/oiv [320 ns] oetey [7.300 ws] o Issue 1, November 1990 Part 2 Interface cards[Asoo / 200 Glossary of terms for PAL signal names sos! ‘Small computer systems interface SBI ‘SCSI bus interface controller DMAC Direct memory access controler SRAM —_Static random access memory PCLKEM —8MHz clock CLRINT Clear interupt INTE Interrupt enable To ‘Terminal count INTRO Interrupt request ARMA ARM processor access Ms Module select uRST User reset RST Reset ABE ARM bus enable RST Internal reset Ra Interrupt request OINT DMA interrupt FI Fast intorupt SINT SCSI interrupt sAST SCSI reset PIRa Podule interrupt PRE Podule read enable PWE Podulle write enable Lar Latched address 12 Las Latched address 13 Ps Podule solect Dack DMA acknowledge no ‘Address ine 0 23 ‘Address ine 23 PRM EPROM SRLO ‘Static RAM low SHI Static RAM high PAGE Page registor INTRD Interrupt read AEN ‘Address enable (ora Inputioutput request Part 2- Interface cards Issue 1, November 1990 Technical Reference Manual HLDRQ Hold request STAGE Move to next stage PNRW ——Podule not read, write BL. Butfer latch Let Latched buffer latch Lioct Latched IOGT REL Release EXTRW Extended read write HUDAK Hold acknowledge lot Input output grant RAT SRAM address 7 REFAM Reference 8MHz clock MEMW Memory write ce Counter bit 2 a Counter bit + co Counter bit iowr UO device write 10RD VO device read vo InpuvOutput MEMR = Memory read CNTRO Counter bit CONTRI Counter bit CNTR2 — Counter bit AWD Read write done en Butfered ‘signat UDE Upper data enable Ne Not connected Bibliography + WD33C83A SCSI Bus Interface Controller Data Book (document no. 79-000199). Availabe from Western Digital (UK) Ltd, The Old Manor House, 17 West ‘Street, Epsom, Surrey KT18 7RL. + NEC Microprocessor and Peripheral Data Book, ‘covering the uPD71071 DMA controller. Available from NEC Electronics (UK) Lid, Cygnus House, Linford Wood Business Centre, Sunrise Parkway, Linford Wood, Milton Keynes MK14 ONP. + “ASeries Podules'- specification of the Acorn podule bus, available as an Application Note from Customer ‘Services (address as at the front ofthis manual), + Acorn SCSI Expansion Card User Guide, supplied with the SCSI expansion card. 223Technical Reference Manual Rey vane © prem ¢ ) ah a chy laa) ch ta (os ' + Chas \ d rea, \ 224 Issue 1, November 1990 Part 2- Intertace cards[Asoormz00 Technical Reference Manual Part 3 - Links, plugs and sockets Main PCB Links Link | Fitted | et Tetaut ti | ita | es Dota Lit |Yee | Intra) auliny veo ay | om Lct0| No | intemal testing, allowing phage | Tik 1-2 Sees Simi oe Rove Eas ers LK | No neal ast ling pase | 2 ie Seneca? | Bo Bore Uita) No | Alonso Sv sppy mite | 1429 2 Sei fey etcna tee | Secrae mW eh ena end | ure |yex | pres ton trvideo | srunta See a Perea ete einetiesen | ama | fre'Groon wo at a_| Se) Uta || Cetgaton itr ner] Now vos Soot Besar | aoe boy Nate at Ho ae ucts] veo | conneotongeintecrowen | None | kite 3 pont angst ramen | | teerenpeb Luss, Yer| Gonsckcomcten mt | shun 2 |Lk3 Yes | Used to contigure the signal on | Shunt 2-3, eee int paSsi Radas sacl | asa ert By Yoneavane fe YoreuSes pe ov oie laseeon Senet e ee ate: Mao a onl apa Bie Rw Sees te re me OR xe Yor | Testcopmcritosin | None Sst eS SE | conjunction with Acorn | Stlgnet sgdron So Hat UD UES | |B Be, W AR | | Po Latte a % 2 33 few Lk24 Yes | See LK23. Aa pes a Reeeceesee aaeerermemne er fae LK25 Yes | Used in conjunction with LK27 | Shunts 1-2 LKB Yes Used to configure the signal ‘Shunt 2-3 {0 select ROM TYPE: Sant Smevaaoeadet | Sync = —— | Bi HSynciSyne | fon. NK et Rigen || AERC nou SE 18 Ur | No | Testpontornanslate | None nana Bao la: orc 2.x sw | ein v425| Yos | seo x29, rod Ut No | TexipontorrTo cock | None ace Lia You | Son ras, ro L129 | Yor | Net aocts urs | os | imma auiansause | None x2 vor | Testpotgr Mec ee | Steeda eons "Geeta Sods | sent a pare Bw qencn 2) yionstet | e ee Bo iimen | Bene | 28 | Evens | NOTE; me xt x22 ee | | neti ted Part 3- Links, plugs and sockets _Issue 1, November 1990 a[Asoo 1 200 Technical Reference Manual Plugs Sockets Plug Fitted Function/Specification | ‘Skt | Fitted | Function/Specification | Put Yes Sonal Por. (BM PC-AT Pinout Ski | Yes | Stero heagphone ouput eee | | ‘This is a 3-way 3.5mm stereo jack socket most oe aoa HS : 5 w ‘This is a 9-way D-type socket providing an Tass De sel Yes Floppy disc power connector. | Links 2, 3 and 6 can be used to alter the i ee | i | Pa tev | ‘Syne voltage levels are >= 2.0V (TTL). LETRA TAA SH fe a (UFC PSA PLA Yes | Floppy Oise Drve Data Connector. This isa | ee | Yor | Some Ose Boe oea come nse, bk eae Pin Signal Pin Signal SK3_ Yes | Parallel printer port. a ee | sewage ents est é use. yeaa -25-way D-type socket providing a parallel 7 34 Whitegate” sinter interface. 6 tester Ge | B 28 Wtlepeot Pin Signal Pin Signal Pin Signal | 3 fee ie eeen ree i Ea A ig bk S : | |i Be | ‘5719.11 optional power lines. See LK'2, sxe | oe | Eze sot PL5 | Yes | Powersupply connector. This is a 6-way | ‘socket for connecting to the DC power supply. ‘S-way DIN socket for connection to Econet_ aie | Eat sos P30 i2v ge ay ie eV ]: SS PLE Optional power supply connectors. | | . Cock & 43. [vos | Memory eparcon sockets aT ae ‘a | | 3 a | Sepa saa ah a 8 Se aeaee LI on ene SKB Yes | Econet upgrade module socket. Thou ofa commons pov a | Se re cat Sway eater vad cotton wh S10. eee ame reae Saran aed crit a S| ierethanage ese | | sKo Yes | eaciptan socket | sxio| Yee | Eoet py mode tat ora sans ct a mene ee retest meses igen aetna, 32 Issue 1, November 1990 Part 3 - Links, plugs and socketsAAb00 1 2200 Sockets (cont.) | skt_| Fives skit! Yes i kta! Yes i ‘SK13) Yes Sk14 | Yos Part 3 Links, plugs and sockets Funetion’Specitcation _ ‘.may min-DIN socket provging he conection pot ornekeyboar rogue, Standard Archimedes keyboard Blogged no ths sooket High resolution mono video output Brouses 8 0.7V mono video signal oto 75 | (hmm) ata dot rato of CMH. This requires | High resolution mentor tobe connected High resolution mono vertical sync. Provides compositavertcal synchronisation | pulses or the high resolution mano output High resolution mono horizontal sync Provides horizontal synchronisation pulses tor) the high resolution mono output Technical Reference Manual Internal expansion Interface Introduc ‘The computer supports an expansion card (podule) interface. The maximum power available per slot can be Calculated from the folowing + The +5V supply rails rated at a maximum oft A + The +12V supply rail is rated at a maximum of 250mA + The -SV supply rail is rated at a maximum of S0mA Refer to the application note ‘A Series Podules' for a full ppodule interface specification, available on request from ‘Acorn Computers. e Description J. | ov Ground 1 jw | 2 wats) | -sv 3 iN) ov ound | 4 Lag) | ov Ground | 5 | LAp2] | reserved 6 tan | Maio | MEMC Pogue select 7 | Lalo) | reserves 8 | tai] | reserved 9 LABS) reserved | 10 war} | reserved | i [tat] sees | 12 LA] | RST! | Reset see note below) [19 | xa) PR | Readinot wie | 141A] | PWE We srobe 15 ua | PRE | easton 16 Bo1is) | PIRGY | Normal nerupt [ir [eone | ert | Postmen 18 | BO[13] ‘Sie 49 spr | ct 20 Bo[It] | co \2 apy) siz 1c serial bus clock 1c seria bus data Extomal Podule select | a fime | er | vee rng a Pelle dae eles Val eeca lees lar eee eee Aes eee 29) BDZ] | REFEM |BMHz Reference clock | = eae a [sv sav | Note: The RST" signals the system reset signal, diven by 1OC on poner up or by the keyboard reset switch. tis an open-collectr signal, and expansion cards may dive also | if tis is desirable. The pulse with should be atleast 50m. Issue 1, November 1990 33(As00 / 200 34 Issue 1, November 1990 Technical Reference Manual Part 3 - Links, plugs and sockets(Asoo p20 Part 4 - Parts lists _ The part lists in this chapter detall the components used in the manufacture of workstations and upgrades, ‘The parts lists are given under the following headings: + Main PCB + 4MB RAM upgrade card + Backplane + ARIM3 daughter card (PGA) + "Keyboard and adaptor card (membrane keyboard) + "Keyboard assembly (Keyswitch keyboard) + *Ethemet | card + "Ethernet Il card + SCSI interface card. “Note that either one of two different assemblies may be fitted There is a circuit diagram for each ofthe above items, All the circuit diagrams are included at the back of this manual Contact the Spares Department of Acorn Computers Limited (account holders only}, or its authorised dealers, ‘and Approved Service Centres, for information as 10 which parts are available as spares. Part 4- Parts lists Issue 1, November 1990 Technical Reference Manual Main PCB assembly parts list Description BARE PCB PCB ASSEMBLY OG (1 pr bat, PGB CIRCUIT DIAGRAM (por batch) MAIN POS REAA PANEL CONR aw SHONT 0" Frrmsto U2. 36, 1802), 23.27 Wine 22swe cn TIN AR OF, x2, xt Wine 2sswe CPR TIN 23), UABeL SERIAL Poe FOAM PAD (1}z24m (BT) ‘S47 16-200 SUPA C21) Sat 0 200-7 SUPA (C39) SSkT Ic 22106" SUPA (C47) 'SKTIC 2206 SUPA (eas SkTIC 300.6" SUPA Ie4S) STIG 300.6" SUPA CSO) Ser Ie esp PLCC (C58) SkT IG 0p Pte ts) Skt le BaP PLCC (Con) kT IG 2003" SUPA 186) Skt le 200. SUPA ICT) BAT NL-CAD 1v2 260MAH PCB GPCTA OU TANT 10¥ 20% 5° GecTR 10U TANT tov 20% 50 Gere 10u TaNT tov 20% Se (GPGTR 10U TANT 10V 20% 5 Spore 2a0u ALEC tev RAD (GPCTR 2200 ALEC 16V RAD GecTR «TU ALEC 16 RAD (CPGTR 4U7 ALEC 1BV RAD horn a7U ALEC 16v RAD {GPGTR 1000 ALEC 250 RAD GPCTR 10y ALEC 16 RAD GPCTA 10U ALEC 16V RAD {GPCTR 2200 ALEC tev RAD PETA aU? ALEC 16V RAD {SPCTR 000 ALEC 251° RAD EPCTR AYU ALEC 16V RAD ‘GPCTR 1000 ALEC 25V RAD GPCTA JOU ALEC 16” RAD Geet 2200 ALEC T6V RAD GPCTR 2200 ALEC tev RAD (GPCTR 2200 ALEC tv RAD GecTaarN Cen so aor (GPCTR ATU ALEC eV RAD GegTR a0 ALEC 16V RAD GecTa arn CER 30V 80%. GecTa 7U ALEC tev RAD (GhTa 2200 ALEC tev RAD Ghora ain Cen sov x hora 4/0 auec tev RAD (Sporn 2200 ALEC 16 RAD Gora tou ALEC 1ev RAD Pore 47N GER 0 80%, pera 47U ALEC tev RAD (GPGTR 100 ALEC tev RAD Sporn 2200 ALEC tev RAD GPCTR fou ALEC 18V RAD {GPCTR 2200 ALEC 16V RAD Geern sau oceLnoz GPCTR 22N MPS SOV tox ‘GPGTR 22N MPSTA SOV Ione SPCTR Yoo Mbsr= soy Tox SPCTR 100M MPSTR SOV 10% GeCTR toon OGPLR suDI2t0 Seeth s008 GPL a0Y 2 GeCTR 470P CPLT aay Tox SecTR s00N BPLR SMDT210 GecTR arp CPLT aov v0 Geeta ta cpr sav 25. GeGTR 108 CPLT a0V 2 Geena anz crc sov rose sp Ghorn ane GPct anv tome SP Gere 33n DOPLA sD I210 (Germ 2n2 CPLT s0V 10% SP Gpore ane crc aov 10% 5P Gere 100r cpu aov 2%. at(As00 / 200 tom | Description | a 56 | ceo 2N2 CPLT 30V 0% 5 4 ES Gein ane cect ov 2 , Se Shera Aroe cPLT ov tow, i cs Ne S$ opera rooe cect sov 26 | Get Sperm tooe Gect ov ae i Gee Sher tooe cect gov 2 ne ei CRETALA7OP CPLT OV 10% ;a} cea al 65 oper w oPLT 90v 105. . Gee CcTA tooe ePLT ov 2% : ber he {668 CROTR 00» cPLT 20¥.2% : es Secrmare cet 9ov 2%. : 10 Gectm ane ePLT Ov 0% 5 i Eh Geomance sev som : E22 | Gectm se cPLT 9ov ‘ ca he E24 | pom one opt 304 2% ' Gis Ghote a oPtr sav 2%. : oe ne G77 | crore acer aov 10% : Gre Epc are optr sov i Ge | Geer ince av tom 1 eo Gpcre toop cPcT Sov 2% : cor ne | G2 crea sn cer sov 0% : G5 Gren sre cpt sov 5 1 Get Germ sn coer o0v 1a 1 5 Gpcrn tone cect ov ae i Ge Sper ce gov tox : GF Gpermarececr ov a6 i Ge CET SN opty so 10 : 5 Geer i GPtt Sov som i Go | GRETA IN GPLT sou to, 4 | Gey GpetA inceLr Sov tox ja G2 CPETR Tooe CALT 30 ae 1 G3 GET NCAT OV Tom \ os Ne G28 | oper ro0e ceur aova% : Gos | GEIR INGALT Ov tom : ca he G93 | cPcTA 1o0P cPLT ov 2% : 9 Lhe E100, opera ra0e GPLT ov 2% : Eton) SeGtm tae eect Sov 25, ' Give) Sper aan opin So: 310 1 ios) Gece san BcPLA Sb' 0 i ioe) Gest aan BcPun Smbi2t0 H {Clos| pera san DCPLA Swbi20 1 los) Geeta san peril svbiai0 1 Gor) pcr san DEPLA SuDia0 1 ioe) pcr san DcPLA SwDi20 i ios) Geer san DcPuR sub! 210 1 E80) Gecra an DcPLA SwD‘a%0 ‘ Ghis| Geera gan DePLR SMD'20 1 Eii2) Gere san pceLR sub'210 i | Glib) Greta Sen ocein swoi2i0 1 | Gila) Gpern San poetn sub;20 i | Gils) Gpern sen ocrur subset : Gié) Greta San ocPuR swDI2%0 i Ei?) Gpera san borin sb 240 ‘| Siig) Cher Sen pceLs subiat0 : Eig) cpern san popia swoi2%0 : Gras) Cher Sen bceLA subsa%0 : Glat| Sper san oceta suDI2%0 : Size, Cher Son OCALA suBIaI0 i] Glas, Gpern son ocptR suD:210 : lat) Geeta gin ooPLn Subra0 : Gias| Seca gn ocPLR Suor210 1 ize, Spcta man cPLA Swbi210 i iar) Geer sav ePLR Subi20 i ize) Geera ain DCPLA Subiat0 ‘ ize) Gece aI DGPLA SuDieI0 1 130) GeeTa aa DPLA SuD120 4 Gist Geeta a ooeuR Suoi20 4 Eras) Sactm eh Berth subs0 1 G55) Geeta san oceLn swbi2%0 i | Gia) Gpern sen beats subset | | Glas) Sperm son beeuR suDi2%0 i | Sige) cron 3 Bort Supiara ne Elae| SRETASON BELA SNDI2I0 ta 42 cist ‘s Bae: Issue 1, November 1990 Technical Reference Manual Description ‘GPCTR 39N DoPLA sMor210 (GPCTR S3N DopLR suo tao ‘EPCTR S5N DCPLA SMOI2I0 ‘GPCTR SON DGPLA SMO IZIO GPCTR S0N DcPLR SubI20 [SPCTR 59N DgPLR so r2i0 GPCTR S0N OGPLR SMD N20 | ‘GPCTR 30N DGPLR SMOIZI0 GpcT son DoPuR skiDr2i0 GPCTA S0N DPLR shDr2i0 GPcTR Son OGPLR SMI 210 (GPCTR 20N OCPLA SMD I240 GPCTR Toon OGeLR SMOr230 =F PETA toon BEPLR Shiot2:0 GecTR 10ON DPLR shoT2%0 Geer tOon BePLR ShBtz10 Pera HOON DoPLR Suot210 GPeTR HOON DEPLA SuBI210 ‘GPCI 100N DCPLA SMDI21O ‘GPCTR 35N DePLA SMOT2I0. (GPCTR 10ON DEPLR SMDI2I0 EPCTR 100N DEPLA SMBI2I ‘GPCTR 100N DcPLA suo1210 ‘GecrA Sen DcPLA SMOr210 ‘GPCTR toon OCALA SMDTZI0 GPCTR 1ooN DcPCR SMO IZ SPCTR toon DgPLR SMO tEx0 Gpcra sen DcPLA Sura SPCTR toon OcPCR shOF2s0 SPCTR toon DePcR SMIat0 {SPCTR toon OGPLA sMOr2i0 Geern sen oPLA surat GPGTR 100N OGPLR SMO r230 GPCTR toon DGPLR sh:2"0 GPGTR 100N DGPLR Sho 1240 GPCTR 1O0N OCPLR Sho 1230 GPTR HOON OGPLR ShOT210 GhcTR HOON OGPLR Shior2t0 GPGTR HOON OGPLR Shlor210 (GPGTR TOON OGPLR SuOT210 (GPGTR HON OGPLR Su 210 GectR 100n DePLA Suot210 GecTa WOON DCPLR suo1210 GPTR TOON DGPLR sD 1210 Secrn Son ocPin suorzi0 Gere aN DPLR sto1210 Sere #0 TaNT tov 20% 9° GeCTR #00 TANT tov 2450 (GPCTR $0U TANT 10V 20% SP (GPGTR !0U TANT tov 20% 3b ‘GPCTR SOU TANT 10V 20% SP ‘GPCI 10U TANT 10V 20% 5? (GPCI 10U TANT tov 20% 8° (SPGTR 100 TANT tov 20% 8 SRST OU TANT aS ‘opcrr ssw oper sé r210 ‘Bro0e St N4aos GON A DIODE siinr48 BODE gt Weta DIODE St eta BIODE 8t Nera DIODE St Nata Grobe St NataB DIODE Sh Nata lobe Bares Sou Diode St Ne DIODE SI INs8 DIODE St IN DIODE St NA DIODE SI INA Diode St INaS FUSE 2A0F AX LEAD LAC Ic 7anierva cus 140 5 I esest ACIA CMOS az Ie tines Cos 140 IG Pancrs24 Cos 160" IG Psro9 asose RU 1G Toiae sede ROVA Part 4- Parts listsAsoo 1 200 tem ‘cr "8 ‘co icra ic ee era tie ers ice ic? ie ice i620 ica iGo Ice Ia (2s 70 1S Description Ic T4acT245 coos 2003" IG PaacTss GMOS 180° IG Pancrs73 Cos 200 5 IG yahets73 GMOs 2000 > IG ORAM shit ZoziP BONS IG ORAM thx 2021P BON IG ORAM ih 20z1P BON IG DRAM ter ZoziP Bons IG Dhak ie 2ozte eons IG ORAM her ziP sons IG eevee Roscova29 ORV IG ORaw nb oz sons IG DRAM chet 2ozip BONS IG DRAKE het oz BONS, IO SLOW PAC (o780.203) Gasea hrc Ran 0S" 1G DRAW thbet 2ozP Bons IC ORAM hoe 2ozP Bons IG ORAM hoes 2ozP BONS TE DRAM thbxt 20z1 20NS TG DRAM hoe 2ozi oONS IC ORAM ox aoa BONS IG DRAM thoxt Boz BONS IE DRAM hex? 20z1 BONS 'C ORAM thox: 2OZI BONS IE DRAM 1M 2071 BONS IG DRAM xs 20z1P Bon IG DRAM tx 20ziP Bons IG DRAM tM 20z1P BONS IE DRAM 1x 20ziP Bon I DRAM the Zazte Bons IE DRAM the 2021P 8ONS FiMteic ADD PAL (0760209) IG DRAM ih 2521P eons IG DRAM ‘Nxt 2021 SONS IG DRAM Abe 20210 60NS, IG DRAM Nhe 20z1P GON IG DRAM hbk Zaz BONS IG DRAM ithe: 2021 GON IG DRAM Nhe: 2021 GON. isc 08 201 ROM! Fise Os 201 ROME isc Os 201 ROMS isc Os 201 Rows Ieraacos cwos 1409 I 7aacoa Cwos 140.3 WG 7ancrs enos 120.3, (6 7aso0 TTL 40 WG fap TTL eos WG 7aagay TT wos" We faasra TT 1403 Coc Pusre IG 7anc32 oMos 140 3 IG MeMesa ewe PLSTC IG Tarts Fast t603, IG TaHG00 ews *40s* IG T4acse GMOs 1403 IG ving wapuste Ie Hine175 CwOS 160° MENG EAST PAL (0720205) Ie 7anesy cwos 2003" IG Tanesr3 Gwos 200.3" IG Taves73 Cuos 2003" I trrsroc eens. MENG SYNC PAL (0780 205), te74acr?4 cuos 1403 IG Juncsre ewos 200.3 IG Tanerars cMos 200.5" IG faneras cw0s 1803 IG Tancrers cmos 200 Ic 7anesra coos 2003" IG Uae QUAD OF aM IG vausare Tr 200 Ie Leas AUDIO AME HOKE RF 2USH Ax O90 ShioKe soortcoez HOKE soormutooMiz HOKE soomtooMz ‘SHORE SOOM Oona ‘CHORE BoOHMDoMIZ Goke soorncniz ‘CHOKE BOOHM/TOOMZ Part 4 - Parts lists ty ter uz us ue ur ut re as as os as ie es ies es ss ust 83s a Ey Ed Ed me EY ma aS rie an & a | (8 3 & Se 38 38 Se S S = s = 5S = mo mg ms HF me me me ms a m S S S m s i Technical Reference Manual Description (CHOKE eon rooNtz ‘CHOKE eoonutoontaz (CHORE eoormutoowtaz ‘CHOKE eoorutoontaz ‘CHOKE eoorautoowtaz (CHOKE coors toon (CHOKE soorsu cont HOKE Rr Uo2H Ax G95 7x3 CHOKE RF S30H AX Goes Onn eW WAFR O"- ST PC EQNR SW WAFR OST Pos CONR 3W WAFR 0" ST PCE CONR SW WAR ST PCE CONR 2W WAER 04" ST PCE EONR aw WAFR 0." ST PCE ‘CONR 10W WAER 2ROW 0.1" (CON 2W WAER 0.1 ST LK Gon aw WAER 01> STL GON 16W WAR 2ROW 0.1" Sona awivarna st pce GONA aw WAFR 01 ST PCB (CON 2W WAER 0 ST PCS SONA aW WAR O° ST PCS GONR 2 WAER 01 ST PCS ‘GONA GW WAR 0. ST PCB GONRO SWELG FA PCBLAFIoL GONAaW PUG Pes st cise P ‘CONR gow Puc ST Pc FeV SONA 34¥ 80x 0c LP St GONR ew PLG Pca OCPWR FSTN TAB SaMNKOS St PCB FSTNTAB oouNxo8 ST PCE Rang sebak NPN TOR? 3° ‘TRANS 2NGODS NPN TOS? 2 “TRANS 2N3906 PP Tous > ‘TRANS Bo220C NEN TOGS 2° TRANS 24G@09 PNP Tose 2 ‘TRANS 243009 PNP Tose 2° ‘TRANS 23008 PNP TOSe ‘TRANS 2N3006 PNP Tox ‘TRANS 23006 PNP TO32 ‘TRANS BC208C NPN Toad. ‘TRANS BC238C NPN TOoe > ‘TRANS BC239C NPN Tome > RES aK? SMD Se ONS 1206 RES ak SMD 5% DN25 1206 ES ak? SUD 53 OND 1208 FES ak? SuD 5 N25 1208 FES ak? SMD 5% ON25 1206 RES a? SMD Sx N25 1206 RES ah SMD 5% N25 ‘208 RES 29K SMD 5% DW25 208 RES sks SD Se N25 1208 RES 10K SMD 5% OW25 1208 Fes son SMO Set ONES 1208 FES 22R SMO sv N25 1208 ES 1K? SMO Sx OW25 1208 FES 10K SO Sot OW25 1208, RES 2208 SMO 5. 01125 1205 FES ak? SMO s5 OWS 1208, FES tho SMO Set OW2S 1208 RES 2k? SMO Sx OW25 1208 FES an? SMD Sst OWS 1208, FES aach SMO se O25 1206 FES exe Su ss oW25 1208, FES eaR SMD S5t NDS 1208 FES 1mo SMO Su: OW25 1205 FES 180H SMO 9% O25 1206 FES tock SMD Sot oW25 1205 FES 10 SMO os OW25 1208, Fes tho SMO st OW25 1208 RES 2200 SMO 9% 025 1206, Fes ro SMO ssc oW25 1208, FRES GBR SMD S%,0N25 1208 Issue 1, November 1990 — Ne NF 43(Asoo 1 200 ee | Description ES 29R SMD 5% 0025 1208 FES 1Ko SMO $3 OW25 1208 FES 1008 SMD S% Owes 108 FES 100% SMO S25 OWS 1208 FES 1000 SMO S3. N28 1208 RES 1Ko SM 39: oWv25 1208, FES tox SMb so oWves 1208 RES 10k Sb sy OW 1205 BES Son SMO ss, owes 1206 BES 100K SMO So OW25 1206 BES GOR SMO om ow 1200, BES (00k SMO oh oW2S 1206 RES ak? SMD 5 0W25 1205 RES 1Ko SMD Soc N28 1208 ES 47K SMO 59 OW 28 1205, ES ‘00K SMO Sie OWS 1208 RES 33P SMD Sy. owas 1208 RES Sah SMD Se OWS f208 RES S3R SMD S925 1208 RES 1KO SMO 50 OW25 1208 FES 10K SMO ss OWS 1208 RES 23R SMD 59: ONS 1208 FES a SiO 5 as 1200 RES GOR SMO Suc OW26 1208 FES "Ko SMO Sx oW25 1206 FES took SMO Sx. ow25 1206 RES 242 SMD S90 OWES 1208 FES Goh SD 5 ov 1206 RES GaP SMD Se 25 1208 RES 6aR SMD Sv 25 1208 RES 937 SMD Se 25 1208 RES 68h SMD 5% 025 1208 FES SKO SMO su W25 1200 ES 10K SMO Set ONES 1208 FES oa SO SO !208 FES ako SMO sx OW25 1208 RES Tok SMO S2 OW2S 1206 FES oa0R SMO 88. 2 1205 FES 1m SMO Ss OWwaS 1208, FES tox Sb sx. OW25 1208 FES 100K SMO Sse 0W25 $205 RES 290R SMO so: 0125 1208 RES Gah SMD 5% O25 1208 RES SO SMD 58 OW2S 1208 BES 22R SMD 5% 025 1206 FES 6af SMD 5% 025 1200 RES 68h SMD Ss OW25 1208 ES OBR SMD 5% OW25 1208 FES SaP SUD 5% OW25 1206 FES San SMD S9% OW25 1208 FES TKO SMO 53 OW25 1208 RES tho SMB Set oWva5 1208 FES S68 SMO Sit OND 1208 RES San SM set owas 1200 RES Oko SMD 6% OW29 1206 FES 60R SMO 5s OW25 1208 FES 66H SMD ss OW5 1208 ES S50F SMO 5. OWS 1205 FES 3KO SMO 9% OW25 1206, RES t00k SM Se W125 1205 RES 100 SMO Si ON2S 1208 ES 220 SMD S M25 1208 FES ea SMD 5 04125 1200 RES 1KO SMO Sa: OWS 1208 FES 22R SMD 5% ONES 1208 ES cam Su sc wes 1208 RES 6oR SMO 5a: OWES 1208 RES G6F SMD Sac OWS 1208 FES Som SMO sa oW25 1208 RES a9R SMO 80 OWS 1208 RES Jan SMD Savas f208 FES 20H SMO Sei ite RES 39K SMO 63 ON2S 1208 Technical Reference Manual Description ES 3k3 SMO 5% 0125 1208 FES 3A SMD 5% 025 1206 RES oeh SMD Saves 1208 FES Sk? SMO 525 O45 1208 FES "00K SMO Sie OWS 1208 RES 100K SMD 59: ON2S 1208 RES E2P SMD Se owas 1208 ES Gm SO 5 Oi ae ES ak? SMD ss: oWv25 1208 FES can SMD 53 owas 1208 ES 62R SMD 59. aW25 1208 FES can SM oy. owes 1208 ES 29F SMD Sec OW {208 FES 3aR SMO 58: OW 1205 ES 628 SMD Sec GW 1208 RES "KO SMD 59% O25 1208 RES 2k SMD 53 N25 1208 PES aR SMD 9% O25 1208 RES GBA SMD soe 25 1208 RES Sk? SMD 58: O25 1205 FES 100K SMO 5% O25 1208, RES 100k SMD 5 28 1208 RES GBR SMD Sv 01725 1208 RES 22R SMD Ss ONS Y208 FES 2k? SMO su OW25 1208 ES G0R SMD St ONES 1208 FES art SS Oa 1208 RES 297 SMO se OW23 1208 FRES 237 SMD 5% OW25 1206 FES eah SMD 5% OW25 1206 FES "0K SMD 53 N25 1208 FES 3K SMD 5 N25 1208, RES 200 So oe oW25 1206, RES 68h SMD Sy O25 1208 FES S00K SMO 58, O25 1206 RES s00K SMD Se 2S 1208, RES GBR SMD Se OWS 1208 FES eof SUD 5% 25 1208 RES 22” SMD Se ONS ‘208 Fes 27x SMO sa OW25 1208 ES ean SMD See ONS f208 FES 698 SMD su N28 1208 FES 688 SMD suc N25 1200 | RES ean Sua 5 ows 1208 RES 297 SMO ot OW25 1208 ES 23 SMD 5% OW25 1206 RES ak? SMD 5% ONS 1208 FES 10K SMD 5 ON25 1208 RES 4K? SMD 59 ONES 1208 RES GBR SMD 5% O25 1208 FES S00K SMO 58. OND 1206 FES GBR SMD 5% 025 1208 RES GaP SMD Soe OWS 28 FES ak7 SMO Sa owes 1208 RES can SMD Soc Wes tage FES GaP SMO 535 N25 1206 | ReS ean sub 5 owzs 1206 PRES GOR SMO Sic ONES 1206 BES SaR SMO sac N28 1208 FES SoH SMO Sa: 0W25 1200 | RES aan suo sows t20e RES 339 SMD 5% O25 1206 RES 10K SMD 2: Wes 25 RES 4k? SMD Sic ONS 120 RES GBR SMD 8% 00725 1208 FES Saf SMD 5% OW25 1206 RES 22R eM So. owes 05 RES ak7 SMO Sa OW25 1208 FES can SMD 53. W25 1208 FES 6am SMD 59: OWS 1298 FES SaR SMD 53: W125 1205 FES 69 SMO suc OW 1208 ES Gan SMD sac awa Y20e FES Gat SMD ss. ows 1205 RES 998 SMO se: OW25 1208 RES oa SMD 5% O25 1206 RES 22f SMD Se OWS 1208 Issue 1, November 1990[Asoo / R200 Technical Reference Manual Description aty tem Description ES GOR SMO 51 oW25 1205 RES 4K7 SMD 5% OW25 1206 BES 3oR SMO Sac owas 1208 RES GBA SMD 9% OW25 1208 ; ; FEE) RES 240 WE 1% Og 6, 1 F200 | RES toon Sk Sx owas 1206 1 1 1 1 + ‘ RES 68A SMD 8% OW25 1200 FES JGR SMO Ss: OW 1208 00 1 RES 68A SMD 9% O25 1206 RES 308 SMO Ss oW25 1208 : F201 | RES GBR SMO ss OW25 1209 BES 33R SMO Sa owas 1206 1 F202 | RES SoA SMD S3 OWS 1205 | FES G9R SMD 88 OW25 1208 1 eos | RES 22h SMO sot ows 1208 RES 298 SMO Sa OW2S 1208 4 Foot | RES 4k7 SM Sx OW25 1206 ES 68R SMO sa oW25 1208 : 205 | RES 68R Smo ss OW25 1200 BES 1KO SMO 5x OWS 1206 : Foe | RES SSR SMO sot OWS 1205 | RES 1RO SMO 6x OW25 1208 1 aor | RES ime St su ow25 1208 RES 35n SMD 5% 025 1206 4 ‘Ra08 | RES 10k SMD 5% oW25 1206 | ‘GONR JKSKT 3W 3,5MM RAPCB 1 abu | RES 1Ko SMO sxc OW29 1208 CONRAD gWSKT RA PCB-AFIAL ; R210 | RES 2KO SMO sx OW25 1205, | CCONRD 25W SKI RAPCBSREL 3 Rett | RES 1Ko SMO Sy OW25 1208 | GONR SW SKTON SCRNPCE 4 Ret2| RES 49R2 MF 1% OW2s E96 (CONR ew Skr St ABE PCB } Rata RES <9R0 ME 30 OW25 E90 | CONR Sew Skr ST ABE PCB ; Rata) RES 22K3 MF Isc OW25 E96 ‘CONR 96W SKT ST ABC PCB | ROIS | RES 20K" ME Toc OW2S E96 (CON SW Scr H&G 01" PCB He Rot6 | RES 22K: NF 1% OW25 £96 CON 96W SKT ST ABC PCB } Rot? | RES 200R SMO Ss. OW25 1206 Sk10 | CONRT7W SkT HSNG. 1-208. ; Fov6 | Res «one wr ‘> 0W5 E98 SkIY | STOW MINDIN RA Po8 FE : Rove | RES 22K1 ME Inc owas E96 Sc12 | CONRENC SkY RAPC METAL 1 Fa20| RES 220R SMD Sx OW25 1206 Sk13 | CONRBNC SKT RAPCD METAL : Fes | RES {00K SMO Sx Ow25 1206 Sk14 | CONRBNC SKI RAPCB METAL t Face | RES 2ont he se owos E96 xr" | Xrav vena Nota st Or 1 Fabs | RES 2OKt MF 1% OW29 E96 Xo | MAL hecaumiz ners ; Foes | RES ‘son Sua So oW25 1206 33 XTAL ae oonnz oo 00s : Fess RES Gn SUD as 1208 Xa | SIAL OSC reo i402 i Fase | RES 1ko0 he se owes E56 Xs Xe | tar osc as oom 1403" X7 | XTAL OSG 25 794n2 1403, | Fase Res soon to-owes Boo fas: AES ‘Heo Ne ‘seones cae exe ES anon Suo sv owes 1200 RES | eS im wo owas 1208 fats| RES KOON 1scows Eee Fase FES s60R SuO Sw on25 200 Fas? RES sok SMO sh ons 1208 fase Fes Seon ur ocowas coe Rese RES SKOOME teow Eee Faas FES rS0n Su Sones 06 Rate BES seki he tows coe EtG FES she Smo ok ons 1208 Rats FES ston su sons 1286 ats FES tox mo oon 108, Fate BES toon suo 9% Ov 00, Fae7 FES toon SMD 9% ones 1208, Fats RES toon SMO 9 O25 208, Fats ES tom SMO Sx On 1208, Faso RES tors ov ones 1208 Fes tno Sb son 208 Fase | FES tno SMO 9m On 1208 FES tho SMO 9 oe 1208, FES tho SMD os 10 ES Zon Sb Son 1208 Fase FES SON SuD Somes 1208 Seep RESzen Sue St ons 1258 ase FES son suo Sons 1208 Foes | Res zen suo se anes 1200 Faso | RES 2m su sh Ow75 1208 Fast | RES a suo owas 1208 Fase | RES sm S60 S025 1208 Fass | ES an suo st owes 1200 Fact | RES am Su se owes {208 Fees | FES an sh soe 208 : | Faer | RES sn sos ones 1208 : Faso RES sah SO Sh owe5 1208 i Faso ES Sm Sw sh owes 1200 i Fart RES san ew somes 1208 \3 Fare) RES san suo 5 owes 1208 : | fara| Res aan BHO 5 ols os 1 fare FESeen su Sr owes 1208 1 Rare, BES Sen Su Sones 1508 i FET | ES San SO ozs toe 1 Fave ES 20R SMO Si ons 1208 1 Part 4 - Parts lists Issue 1, November 1990[Asoo 1 200 Technical Reference Manual 4MB RAM card (optional upgrade) —_—Notes on MEMC: 4 is a e & ce cs ce & & cto cn cra ter co res ice cr Ic icto) u Puy Rt Re Re er Fe | fe Rio BIZ Ra Ria Bre Fes Fee rar rae es Description BARE PCB Poa aSSeMaLy on Pea Cinco AGRAM Tabet SERIAL Pe Grom a7U TANT SUD GecTA47U TANT SUD (PCTRATU TANT SUD ‘SecTa 47U TANT SD PTA 33N DCPLA SMD1210 Gera 3N DCPLR SuD1210, (CecTA aN DCPLA SuD1210 Ghcra 33N DCPLA suD1210, Ghote aan DCPLA SuD12"0 Gora 3an OGPLA s¥D210 (Ghcrm 338 OGPLR s6D1210 Grotm aan BcPLA SuDI2"0 Grora aan bcPLA suD12"0 Ehora aan ScPLn sub 1210 I timxs DRAM BONS SOL I thine DRAM Bos SOM I thie BRAM BoNS SOM IG 1x4 DRAM BONS SOM IC 1x4 DRAM BONS SOM IG 1hixa DRAM BONS SOM I Mike DRAM BoNS SOM I 1hixd DRAM BONS SOM IG 74Xco4 CMOS 14? SMO IG MEMCSA t2u2 PLSTC (CHOKE 6oR‘OoMnZ Si (CHOKE 6ORooMHZ SD (CHOKE 6ORtoOMHZ St CONR sw PLGA Bc Pc: RES Ga SMD 5% 025 1208 RES GBR SMD 5% O25 1208 RES eaR SMD 59 ONS 1208 RES e8P SMD 59 ONES 1208 FES e8P SMD Se ONES {208 FES enh SMD Se ONES {208 FES 6BR SMD 59, 0W25 1208 FES 68R SMD 595 0425 1208 RES G8R SMD Ss ONS 1208 FES e8R GMD S90 ONS 1208 FES 68R SMD 53 0425 1208 RES G8R SMD 59, N25 1200 FES G8R SMD S% ONDE 1208 FES e@R SMD Sc ONDS 1208 FES eaR SMO 53. N25 1208 FES 6a SMO sic ONES 1205 FES 6aR SMD 535 ONES 1208 ES G2R SMO Sit ONDE 1208 ES €2R SMO 50 ONDE 1205 RES c@R SMD 59 ON2S 1208 RES e0R SMD Soc NDS 1208 FES car SMO Sic OWS 1208 FES GOR SMO S35 OW 1208 ES 688 SMO ss: OW25 1208 ES 608 SMD Sac OWES 1208 RES G0R SMD Sat OW2S 1208 RES eGR SMD sa oW2S 1208 FES e8n SMO 59: oWveS 1208 FES 6BR SMD sa OWS 1208 FES sah SMO sot oWvas 1208 RES Soh SMD so oWv25 1208 ‘RES 337 SMD Se 025 1208 RES 23P SMD Soe 025 1208 RES 337 SMD 0025 1208 RES 32h SMD Soe owas 208 RES a3R SMD S025 208 MEMCs MUST be Acorn Part Number 2201,398, to Qty ‘ensure correct timing parameters. To allow for future expansion, PLi pins A25,16 and 8 should be lett open circuit, nat connected to +5V. This change wil be carried out on any future issue of the PCB. | Backplane adaptor | - tem Description il _— 1 | BARE pce 2 | PCB ASSeweLY oF (PER BATCH {| Fes Crcur Oagnau (ren oarcHy ts | CRBC SERIAL pce tensor | & | cbeimasem ocrenos" | Ge | Ghcrmasam ocpun oF | Gecra saw ocpun oO Gt | Geeta aru ALEC ev Ax & | Gecra7UALec iev Ax Ge | GecrRa7U ALEC tev AK fer | erancr9 wos "90a" IG2 | SpINT ASK PaL(oreoac9) (63) BPINTNASK PAL(o760009) PLI | GON GOW PLGA ABC POB Ri | RES tox Cmte see owas Re | RES tom GME sx owas Fe RES tok GI sx Owes fa | RES tok CIM Sx OW25 Sk1 | CONA ew SxT Sr AC PB SH ‘Sk2 | CONR&W SkT ST AC PCB SH Ska | CONReaw Sar st ac Pee si Ske | CONRaWSxT ST AC PCB SH Issue 1, November 1990 Part 4- Parts lists‘A800 / R200 ARMS (PGA) Daughter card tem Description 1 | ane pce 2 | POBASSEMALY ORG 3. | pepcincur omaram 3s TABEL SERIAL Po G1 | CecTRarU alee vow ax G2) Gectaary ates tov ax & | Geeta zee Ceur soy a Gt CPGTR ON OCPLA SMDI210 S| ChCTASaN DopLASMO:210 G& | GecTR aN DePLA sMOieI0 ©) | GecTAaIN DeeLASNOI210 Ter | ARMS CPU PGA) G2 | ICTHACT?a MOS 1403, RY | Res tox Sve ssc owes +206 2 | RES SBR SMO set ONDE 1208 Fe | RES f00R SMO Si OWS 1200 | BS | ReSzm sibs ones woe RY | RES 20R SMO ss WDE 1208 Fa | RES sor SMO set owas 1208 Fi Res 2m SHO Sot aoe | BIT | RES 20m SMO ssc OW2S 1208 Bid | RES 20m SMO su OW2S 1205 ig | RES 207 SMD ssc NDS 1208 Rid | RES 22R SMO set OW2S 1208 Big | RES 22R SMO su OW 1205 Rie | RES 20m SMD sec WES 1200 iy | RES 20m SMD oi ON 1205 ig RES 20R SMO su OW, 1205 tg | RES 29m SMO ssc OWS 1205 ao | RES 22R SMO sac N25 1208 | Ret | RES 20R SMD sac owas 1208 ES 228 SMO su OND 1200 a3 | RES 22F SMD sit OWos 1205 Foe | RES 208 SMO sur OWS 1208 os | RES 227 SMO sec W2s 1205 | Be | RES 20m SMO sac owas 1208 Fo? | RES 22R SMO set Was 1205 aa | RES 208 SMO sat N28 1208 FES 228 SMO Sac N25 1208 ao | RES 22R SMD sac WBS 1208 Fat | RES 22” SMD Si ONDE 1205 Faz | RES 20R SMO su OW25 1208 aa | RES 22R SMO 53: NDS 1208 FES 22R SMO 53. N25 1208 as | RES 22R SMD sac NDS 1208 Fae | RES 20R SMO sot OW2S 1205 Fa? | RES 207 SMO Si ON2S 1205 | Fig | RES 22n SMO suc owas 1208 ES 228 SMD Sac ONES 1208 FES 227 SMO 51 N26 1205 Ret | RES 20R SMO sot ONBS 1208 ep | RES 22m SMO su N25 1208 | RES 22n so sx owas 1208 et | RES 22m SMO 53 OND 1205 fis | Res 227 SMO ssc N25 1208 eg | RES 207 SMO su ONDE 1205 Re? | RES 20R GMD sac NDS 1208 | Bag | RES 22m SMO sa ows 1208 us | RES 22f SMO ssc N25 1205 so | RES 22R SMO sec OW 1208 et | RES 22R SMO Set OW2S 1208 52 | RES 228 SMO Su ONDE 1205 fsa | RES 22R SMO si OW 1208 ES 20R SMD Sat OWNS 1208 SS | RES 20R SMO su OW2S 1205 Fe | RES 20n SMD sot N25 1208 FS? | RES 22R SMO Sa OWDS 1208 Fise | RES 227 SMo sot N25 1208 se | RES 29R SMO sx OWS 1205 Feo RES 22R SMO set OW25 1200 | Bet RES 22R SMB ssc OW2S 1208 Fez | RES 22R SMO set OWo5 1205 Fea | RES 29R SMO ssc OWS 1208 et RES 22R SMO sx OWS 1205 és RES 22R SMO Sst oW25 1205 Foe RES 22R SMD sx OW 1205 Per RES 29R SMD set OWaS 1208 ee RES 228 SMO Sx OW25 1208 Ski CONR Sew SKT RAPER REV xt | Kiavose rao 2 Part 4 - Parts lists Technical Reference Manual Keyboard adaptor PCB (membrane keyboard) tem Description ARE PCB PCB ASSEMBLY Die.» PER BATCH) PCB CIRCUIT DAGRAI "PER BATCH) KEYSOARD CABLE ASSEMBLY Cgetseniat pce RE 258W0 CPR TIN (AR x1) SKT IG 4006- SUPA C3) GECTR IN GPLT 20V "0% GPCTR INGPLT 3ov 105 GPETR INGPLT 30V ‘05. GPGTR IN GPLT Sov ‘05 GPeTR APU ALEC 10v 8x GPCTR S247N DOPLR OZ GPCTR ssu7N DoPLAOZ Geeta 27p CeLT ov 2% per sau7n DopuR Oz Gecrn 27 cPLt sav 2% SPST Sawn DopLROZ Gpora sam popu Oz Geore sum Dopor oz Pern au? ALEC tov ax GPCTR a7U ALEC 10v AK SPcrR INGPLT 30v 10% Grote INGPLT 3ov 0% Gere INGPLT 3ov S05 GPCTR IN GPLT soy “05 Pera INGPLT 30¥ 10s GPCTR INGPLT 30v 105 Gere INGPLT abv tos GPCTR IN GPLE Sov “05. Se ranctaost CuOS 180." IG 7avicT4051 GMOs 1603" IG KBD IRL [o7o8.051) IG axe CMOS 140 NG 7ahoT+4 cmos tao: RES 2208 CMe sx ow2s RES a00R CM 5a OWS RES 47K Cr 5% OW 25 RES 47k CMF sx. owas RES «7h Gur Sx owes RES «7k GU 55 0W25 ES «7k Gar sec owas RES 47h GF Sm OW25 RES «7k GF aW25 RES 47k GRU su owas RES 47k GM Shc OW25 RES 47k GM Sm OW25 RES 47h Gav 50OW25 RES 2708 CMF 5% N25 RES £7K Cir soe ows RES «7k GM OW 25 RES 47k GME 5%: OW 25 RES ak? GU 5 OW28 RES SOK CM Sic OW RES 3308 Come 5% OW25 FES a908 Guar Sx owes RES 10K CMF 5% 0W25 Fes 3808 CMF 5% 0425 FES ‘OK CoM 59. oWas, Ries g20n cm Sones RES 2708 GM Se OW28 RES 10K CMF 59 OW25 RES 10k GME sy: OW25 RES 10k GME Sy: OW25 RES 22k GM 5m, oW25, Res soon Gur Sones RES S008 GF 5% O25 Issue 1, November 1990 a7[Asoo / R200 Technical Reference Manual Keyboard adaptor PCB (cont) Ethernet | (membrane keyboard) ry ieee a tem Description ay, Bane pce A 1 ASE Sty oRAWING i x2 | Conn ow Fuex pce hs GincutT oAGRAM 5 Se | Gowtawont worn ne : IEGAL | (oreo rap) : Sivt | Sit nowco Pe RA Pcs 1 IG Gat (ovens reP| : ai | Krab Bowne Here Hy IG GAL a (ovens Tap, : IC Paowe (oraeio TBA) : CB SUPPORT MOUNTING BRKT i fig. | RES 4K? Cour ou owas i Keyboard assembly (keyswitch Biz19) RES sone Me 1% oW25 E—e 4 keyboard) Be"? | Res sare Me Icons ESS $ Bie" Res he rivet se owes ma This is @ service replacement item. Part numbers: | Regent ara : G2 | Gpern crt sin sav 2 2 (186,012 (keyboard subassembly) GiSo, GPETAALEC a7aF 1 RAD 5 rare 0086,900/A (complete keyboard unit). ce CPCTA CML 220n 25v 20% 1 Giasg, Greta cen 1ons00v 20% 2 G13") GPoIRWPSTR 2 a0V 10% : 6) | Geermctasy ton zsov om : Skice, SRCTR OCALA Samo fe ie fer 1Gio{ 1c e2056 sam soos 2260 2 vexe | IGe250" Sa NMS oar ‘ (err | tC eeone Tran nos veo i Gy” IG aesns LAN wos sao i (62a | IC rneraes Mos soos 2 I6e9, | 16 tacts Mos a0 i os Is | 1c zaHersra cuos ano: 2 (Gio | (C raacravo cos sous ; Bot | (wa De)0C:00 CON 12V TO sv.x0v 4 Sr (as teiytaans Sezao nen rose Cac 1 Biz | Siobe Neiso'stsov boas 3 Ohio | CoNR warn pW OY ST FoR i Uke, CON 2W SHUNT 8 ; % Sit 1c 1608 SUPA ‘ Gseouicrr ser | 1Gz000 SUPA 1 Use on cre ser | IGaaoeGupA 1 Use ovict SI Jugs PLCONR 15 SA RA PAARL 1 Pu Sothedwma hance i tide | conn warmeworrstfce a PLS” | Gonmae ser oN son NSU 1 | Saw’ sue Lock assy i USE ON Skt x1 XTALZounz Hose 20eF x. 1 Ty | Sotans isnot os i tne | 225n0 con IN An Use ON PLD | sow Mesee PANS Post ‘ USE ON 11637, Sow | Naxi9PANHD Post 2 USE Gurr nur | Mas Si ult zens 2 Use ow 100 Nur | MasrrUtL 2PAs 2 USe once 1 woun] was Sharir sr. 2 USE Onoe woaR) Ma Sone st. 2 {USE ON 6,109 “PER BATCH 48 Issue 1, November 1990 Part 4. Parts listsEthernet Il [tom Description 1 | eanerce 2 | ASSEMBLY ORAWING 3 | Cincom owcraw & | BOBSUPPORT MOUNTING BRKT Sy | Conn aw Shunt farce 13. | Skric’2n0s suPA irovarata 14 | Serica sure 1s | Sericeawetce ea 16 | Sericzawrvce 18 | TSWDSUDELOcK ASSY | set 23 | wine 220we cer TN XSi 22 | ScWhiz.s6 pan Ho Post Use Wirt Tes 17 6 23 | ScWaKOPAN HO Post USe WITH Tews .88'SK1 25 | NUTMasSTL FULL ZPAS USED vrraviem 25 26 | NUTAGSTL FULL ZPAS seo wr rem 2 2s | WenrW25 sear TST. USED wrt ren 22 20 WHR NG SPR IT STL USED wire rrem23 fr RES30R2 MF 1% OW25 696 Re | RES gene Me Ime oW25 E06 Fa | ReSeaR CMe sxc owas Bs | RES 100K crm ov owes Fe RES 29Re mit OW25 E96 RY | RES 1KOO MF 1% owas E96 Re | Res ins cM sx owas Fa | RES 274R MF ONGSEDE Bio | Res 220R Cnr 5% 0W25 Bit | RES iKs CM sic owes Riz | RES 274 Mr ONS EDS Bio | RES iKS GME sy OWS Ria RES IMO MIVOLT Sx, O25 BIS RESSAR CMF 5 aW25 RPL | RESNET 1Kex7 SIL P 2% 2 | RESNET 1K5x7 SIL BP 25 Cr | GPCTATOOUALEG 25v RAD G2 | GpeTmALeC a7uF tev RAD & GPCIRALEG a7uF tev RAD & Seca OceLAas4maz & | Gecmmoceunsaam os & | Grom been ssam oz & | Gectmoceunssamox G3 | GPcrR DGPLR samo | Gecrm DCPLR S847 02" Sto | eect Sepun soem os Si | Getnoceuassamos Sie | Germbertnsatmos Sis, Geet serta sae oF Sie | Gectnocninsoamoe Sis | Geernpcrtnsacn oe Sis | Sernportnsatmor Sis | Seernperun soem oe Gia Sperm bertasoarn oe Gls | Geetpcrtnsoarh oe Gos | Secrnportn soerh oe & | Seer Scrum sacmee GBs | Sst CaSy tontS0y som & | Seerm son entra a0 Sez | Seem au cr sivaox SS | Sen ish sv ae | SB | Secrmecr sob anv | SSetn cnt sv som a | Seerm cect sso Gs | Sperm esau wovsox Ceasiawoe NDOPce Part 4 - Parts lists ay} [tem Description 1 2 | Iceavca TANSCVA 160° & IGS | Gaseoc Nic ea pLcc r IG IG yancensewos 200 1 Is | iG zaNcass cwos 2903" : Ios | iG om forer 20 Tap) 6 ter | iG rere cos 200 5° fa | iG yanctars cmos 200 + ‘ ico | i zancts73 GMOs 200 | Ilo IG PAL (0760200 rap) 1 Ii | I eacTo4e CMOS 200° Tez | i yancTsra CMs 200 > 1 IGi3 | 16 Zeacre< para ADO-15 (READ) NETAOE,AAGE RAM ADDRESS BDO-15 (WRITE), << BDO-15 (READ) BDOE, LDOE, HOO RAM DATA BUS ADBUS apps apa. vai a> Wat eee ee eee Tani ST Ee ee RAMOE RD RD Boe —__ =p 7803, Loor, xs10 aE —— aE — CA, CLRINTO: ss Figure 21.3 : Typical podule bus cycle ‘Acorn Technical Publlhing Systom Technical Reference ManualEthernet pode : Detailed description It should be noted that Read) is always deasserted for three cycles, even if the LANCE is idle. ‘A podule bus access can ‘collide’ with a LANCE access in five different ways, depending on ‘what state the LANCE is in when the podule bus access starts. These are: PS* while the lance isin states 1 to T4 or ile. The actual umber of wait states that the LANCE will insert depends on which of these cases apply. The following four figures illustrate the possible cases. = ede rele || ses cvens Ju fp ote b A | STATE MACHINE wie sd sab sad wid | 5 ees ee ee ee ee ADDRESS” se {Ca = es Le sce Figure 21.4 : Access collision cases - PS* while LANCE is in TL ao | scare |x [a de | ssscveus | m1 [m2 [rw foe ahs poof | STATE MACHINE ths sh sal sasl wk | . a a —o~w. ve RAM DATA/ ADDRESS LANCE, LANCE, Figure 21.5 : Access collision cases - PS* while LANCE is in T2 PS¢ while the LANCE is in TI. Figure 21.4. ‘The LANCE samples READY deasserted at the end of T2 (SA2), and then again at the end of WI (SA3), so in this case two wait states are inserted. PS* while the LANCE is in T.2, Figure 21.5. ‘Acorn Technical Publishing System Technical Reference Manual "Ethernet podule: Detailed description ‘The LANCE samples READY deasserted atthe end of T2 (SA1), TW1 (SA2), TW2 (SA3),¢ the maximum of three wait states are inserted, Since three wait states isthe worst case this is shown in more detail in Figure 21.5. ARM CYCLE | asracre |e alee eee | reese eine eee STATE MACHINE thie shi sab sad iid | Figure 21.6 : Access collision cases - PS* while LANCE is in T3 fered | smr[a tak b | nsscras fi fm | | m1 [re dw foo fa | STATE MACHINE | whe sd: sab sad wid — | —_ or READY es eee RAMDATA/ Poona) LANCE LANCE Figure 21.7 : Access collision cases - PS* while LANCE is in T4 PS* while the LANCE is in T3, Figure 21.6. ‘Acorn Technical Publishing System Technical Reference Manual 1Bus design note Ethernet pode : Detaled description In this case READY is still active when the LANCE samples it at the end of T3 (idle). This i ‘the last time that the LANCE does this for the current cycle so the LANCE cycle completes before the podule bus cycle starts. Note that the LANCE is not active on the RAM bus durin 14. PS* while the LANCE is in T4. Figure 21.7. Since the LANCE does not require the bus during 4 no further wait states are inserted in the current cycle. However T1 of the next cycle could follow T4 and one wait state will be inserte into this LANCE access. PS* while the LANCE is idle. Ifthe LANCE remains idle while the podule bus cycle occurs then there is no collision and th LANCE ignores the READY signal. This case isnot illustrated. ‘A read from the podule ID PROM or write to the control or page register is similar to aRAM cycle. To simplify the bus design the LANCE is removed from the RAM buses during cycles t these devices. ‘The cycle stealing scheme should guarantee that the LANCE never has insufficient bus ‘bandwidth or sees excessive bus latency to the extent that it cannot service the net or fails to ‘meet the IEEE timings. Even when the ARM continuously accesses the RAM. The following _gves the reasoning behind this statement: ‘Assumptions: Net Clock = 10MHz. Bus Clock 8MHz LANCE FIFO size = 16 bytes HOLDA is wired to HOLD so: Bus Latency = Ocycles IEEE Interframe Space Time = 9.6 pS Criteria: 1, FIFO must not over/underrun. ‘FIFO fill/empty time from serial side: +=8 (bits) * 16 (bytes) * 100E-9 (bit time) = 12.8 us ‘FIFO empty/fill time from parallel side: = 8 (Word transfers) * (4 (standard 8 MHz cycles) + Nwait (wait cycles)) 1258-9 = 4 ys (if Nwait = 0) = 7s (if Nwait = 3 ) = 8 is (if Nwait = 4) ‘Acom Technical Publishing Syetom Technical Reference Manual 1Interrupts. IT Ethernet pod : Detailed description 2. ‘The LANCE must be in a position to transmit by the end of the interframe spacing time. With a Fp/Fs ratio of 8 MHz/10 MHz (0.8): 16*Nwait + Nlatency must be less than or equal to 80. IfHOLDA = HOLD then Niatency = 0 and Nwait <5 So this strategy works if we can keep the number of wait states (Nwait) less than or equal to five per access. In the current design three are used and this is unlikely to change. ‘The podule interrupt (PIRQ) is level triggered. However, the interrupt signal (INT) from the LANCBis designed for use with edge triggered interupt controllers. If the net controller detects second interrupting condition just after the first is raised, it will drop and reassert INT. The situation could arise where the podule manager (software) may scan the slots and find no IRQ flag set. ‘The above problem is prevented by latching INT in the interrupt and channel atention PAL (1C78) and using the latched signal INTO to generate the flag. The clear interrupt (CLI) bitin the control register is used to clear the latch. Latching INT introduces a further problem which is eliminated by a feature of the 82586 LANCE. If second interrupt occurs afier the processor has read the status word in the SCB but before the first is cleared then the second interrupt would be missed. However, if athe interrupt is cleared atthe same time as the channel attention (signalling the acknowledge command) is issued, the LANCE will respond by deasserting INT and reasserting ifthe second interrupt was not acknowledged because it was missed. It is recommended to set CA whenever CLI is set. Operation ofthe interrupt latch and the clear interrupt bit is illustrated in Figure 21.8, Figure 21.9 and Figure 21.10 below. UU UU SU ee ee eee mqavro —— ~\ we fo LS a A) LATCHING _B) CLEARINTERRUPT C) EDGE SENSITIVE Figure 21.8 : Example interrupt cycles ‘Acorn Technical Publishing System Technical Reference Manual “Ethernet pedule: Detailed description INT +INTEN CLRINTO +IDLE ENABLED SEARED INTO c H +INT INTO Figure 21.10 : State diagram for INTEN* LInkS The PCB should be viewed from the component side with the 96 way podule bus connector on the left and the rear panel on the right. When viewed like this, west is tothe left, east the right, north the top and south the bottom. LK1 and LK2 select the RAM size 132 kbyte devices are fitted (normally) the links should both be south. 8 kbyte devices will not normally be fitted but in this case LK and LK2 should be north. ‘Aco Technical Publishing System Technical Reference Manual 18Ethernet podule: Detailed description LK3 to LK8 select Ethernet or Cheapernet. For Ethemet operation the links should be west (link pin a to pin b). For Cheapemet operatio the links should be east (link pin b to pin c). |LK9 is tracked south and not fitted on production units. ‘See data sheets for the 82502 for use. PROM GRC calculation The following is a code fragment in the C programming language that calculates and validate the Ethemet PROM checksum. /* To calculate and check the PROM checksum */ int ROM_chk (vector) /* array 0..32 bytes *) u_char vector [32]; ( register int i,3; register unsigned chk = J* Set the CRC register *) J* to FEFFFFFF * register unsigned byte; 7* temp for (i = 0; 4 < 28; i++) ( J* ORC on bytes 0..28 +) byte = vector [i]; for (j= 07 3< 87 34) { if (((byte & 1) * (chk >> 31)) != 0)/* IF feedback = 1 a chk = (chk << 1) * (0x04C11DB7); /* shift and EOR taps*, else 7* ELSE chk = (chk << 1); 7* just shige ” byte = byte >> 1; 7* next bit ” , /* chk is now the calculated CRC */ /* Now get CRC from PROM */ byte = (vector [31] << 24) | (vector[30] << 16) | (vector[29] << 8) (vector [28] << 0); /* Test to see if the same */ if (byte != chk) return (FALSE); /* checksum errort/ else return (TRUE); ) ‘Acom Technical Publishing System Technical Reference Manual '