5

Project code: 91.4CH01.001

PCB P/N
: 48.4C901.001
REVISION
:08252- -SB

JV50-PU Block Diagram

DDR2

PCB STACKUP

667/800MHz

AMD Giffin CPU

S1G2 (35W)

667/800 MHz
16,17

DDR2

G792
35

LCD

OUT

IN

1D2V_S0(4A)

LAN

RJ45

27

26

INPUTS

49
OUTPUTS

DCBATOUT

1D8V_S3(11A)

RT8202

TXFM

Giga LAN

RT9025

27

49

5V_S5

1D1V_M92

8,9,10

PWR SW
W83L351YG
28

New card
Codec

A-Link
4X4

AZALIA

34

PCIex1

RT9161
3D3V_S0

Mini Card
Kedron

ALC888

a/b/g/n

28

G957

33

49

30

G9161

LPC BUS

AMD SB700

BIOS

ETHERNET (10/100/1000Mb)

OP AMP

ATA 66/100

Line Out
(SPDIF)

WPC773

MAX8731

DEBUG
CONN.37

37
36

1D2V_S5
(400mA)

CHARGER

LPC

MXIC
MX25L1605

KBC
Winbond

High Definition Audio

APA205729

49

3D3V_S5

USB 2.0/1.1 ports

INT.SPKR

1D5V_S0
(1A)

Mini Card

South Bridge

INPUTS

CHG_PWR
DCBATOUT

LPC I/F

Touch
Pad 38

PCI/PCI BRIDGE
11,12,13,14,15

SATA

MODEM
MDC Card
31

USB

Mini USB
Blue Tooth 24

HDD SATA
22

CardReader
Realtek
RTS5159
32
USB
4 Port

ODD SATA

Finger
Printer 31

23

50

OUTPUTS

ACPI 1.1

30

49
2D5V_S0
(200mA)

3D3V_S0

MIC In

DCBATOUT

LVDS, CRT I/F

INTEGRATED GRAHPICS

30

RJ11

1D1V_S0(7.5A)

BOTTOM

SYSTEM DC/DC

BCM5764

30

47
OUTPUTS

TPS51124
INPUTS

M92XT
53,54,55,56,57,58,59

AMD RS780M

INT MIC

21

30

SYSTEM DC/DC

GND

HDMI

North Bridge
CPU I/F

3D3V_S5(6A)

19

ICS9LPRS480BKLFT 71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03

18V

UP+5V

INT.
KB 36

5V

100mA

CPU DC/DC
ISL6265HR 45
INPUTS OUTPUTS
VCC_CORE_S0_0

MS/MS Pro/xD
/MMC/SD
5 in 1

0~1.55V

32

18A

VCC_CORE_S0_1

DCBATOUT

0~1.55V

18A

VDDNB
0~1.55V

18A

25
<Core Design>

Camera

Daughter Board
USB Board

Daughter Board
LED Board

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

BLOCK DIAGRAM
Size

A3
Date:
4

6.0A

Title

5V_S5(6A)
DCBATOUT

20

16X16

46
OUTPUTS

ISL62392HR
INPUTS

VCC

CRT

4,5,6,7

CLK GEN. 3

SYSTEM DC/DC

TOP

638-Pin uFCPGA638

667/800MHz

667/800 MHz
16,17

Line In

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

of

61

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

USB/PCIE Routing
Size

A3
Date:

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet

of

61

3D3V_S0

3D3V_CLK_VDD

3D3V_S0

DY
2

C511

3000mA.80ohm

3D3V_S0

Due to PLL issue on current clock chip, the SBlink clock

need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.

C506
SC1U10V2KX-1GP

1
2

3D3V_48MPW R_S0

2
2R3J-GP

SC4D7U6D3V3KX-GP

C504
SCD1U10V2KX-4GP

C492
SCD1U10V2KX-4GP

C462
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

C476

SCD1U10V2KX-4GP

C453

SCD1U10V2KX-4GP

C467

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY C502

C501

C500

R221

1 R215
2
0R0603-PAD

Clock chip has internal serial terminations

for differencial pairs, external resistors are
reserved for debug purpose.

1 R197
2
0R0603-PAD
1D1V_CLK_VDDIO

C508
SC27P50V2JN-2-GP

2008/11/10

VDDCPU
VDDCPU_IO

16
17
11

VDDSRC
VDDSRC_IO
VDDSRC_IO

35
34

VDDSB_SRC
VDDSB_SRC_IO

40
4
55
56
63

VDDSATA
VDD
VDDHTT
VDDREF
VDD48

26
26

LAN

51

PD#

CLK_PCIE_LAN
CLK_PCIE_LAN#

R193 1 0R0402-PAD
2
R194 1 0R0402-PAD
2

CLK_PCIE_LAN_1
CLK_PCIE_LAN#_1

R198 1 0R0402-PAD
2
R199 1 0R0402-PAD
2

CLK_NB_GPPSB_1
CLK_NB_GPPSB#_1
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1#_1

9 CLK_NB_GPPSB
9 CLK_NB_GPPSB#

NB A-Link

CLK_PCIE_SB_1
CLK_PCIE_SB#_1

MINI1

33 CLK_PCIE_MINI1
33 CLK_PCIE_MINI1#

R200 1 0R0402-PAD
2
R204 1 0R0402-PAD
2

NEW

34 CLK_PCIE_NEW
34 CLK_PCIE_NEW #

R205 1 0R0402-PAD
2
R206 1 0R0402-PAD
2

CLK_PCIE_NEW _1
CLK_PCIE_NEW #_1

MINI2

33 CLK_PCIE_MINI2
33 CLK_PCIE_MINI2#

R211 1 0R0402-PAD
2
R208 1 0R0402-PAD
2

CLK_PCIE_MINI2_1
CLK_PCIE_MINI2#_1

2008/11/05
54

54

R209 1 0R0402-PAD
2

CLK_27M_SSIN

DY

2 R353

CLK_27M_M92

22
21
20
19
15
14
13
12
9
8
42
41
6
5

CLK_SRC0T_LPRS
CLK_SRC0C_LPRS

37
36
32
31

2008/11/13
1KR2F-3-GP
R217 1 0R0402-PAD
2
R216 1 0R0402-PAD
2

9R352
CLK_NBHT_CLK
9 CLK_NBHT_CLK#
1K2R2F-1-GP

NB HT

54
53

CL=20pF0.2pF
R2141
R2131

ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS

30
29
28
27

CLK_PCIE_PEG_1 R1871
CLK_PCIE_PEG#_1 R1881
CLK_NB_GFX_1
R1891
CLK_NB_GFX#_1
R1901

CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

23
45
44
39
38

CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

CPUKG0T_LPRS
CPUKG0C_LPRS
SRC0T_LPRS
SRC0C_LPRS
48MHZ_0
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
REF0/SEL_HTT66
SRC2C_LPRS
REF1/SEL_SATA
SRC3T_LPRS
REF2/SEL_27
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC6T/SATAT_LPRS
GNDSATA
SRC6C/SATAC_LPRS
GNDATIG
SRC7T_LPRS/27MHZ_SS
GND
SRC7C_LPRS/27MHZ_NS
GNDHTT
GNDREF
GNDCPU
SB_SRC0T_LPRS
GND48
SB_SRC0C_LPRS
SB_SRC1T_LPRS
GNDSRC
SB_SRC1C_LPRS
GNDSRC

50
49

CPU_CLK_1
CPU_CLK#_1

GNDSB_SRC

33

GND

65

HTT0T_LPRS/66M
HTT0C_LPRS/66M

64

CLK_48

59
58
57

REF0
REF1
REF2

TP153
TP160
TP159
TP156
TP157

SMBC0_SB 12,16,17
SMBD0_SB 12,16,17

2 0R2J-2-GP
2 0R2J-2-GP
2 0R2J-2-GP
2 0R2J-2-GP

CLK_PCIE_PEG 53
CLK_PCIE_PEG# 53
CLK_NB_GFX 9
CLK_NB_GFX# 9
C

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

CLKREQ# Internal
pull Low

R222 1 0R0402-PAD
2
R220 1 0R0402-PAD
2

1
2

SC33P50V2JN-3GP

2 0R2J-2-GP
2 0R2J-2-GP

CPU_CLK
CPU_CLK#

RN65
4 SRN22-3-GP
3

2008/12/09

6
6
CLK48_USB

EC50

DY
43
24
7
52
60
46
1

DY

EC49

10
18
NB CLOCKS

For SB710
DY
110R2F-GP 2

3D3V_S5

PD#
R234

8
7
6
5

1
2
3
4

75R2F-2-GP
RUNPW ROK_D

RUNPW ROK_D

DY
1

SEL_27
REF2

R228
10KR2J-3-GP

DY

SEL_HTT66
REF0

27MHz non-spreading singled clock on pin 5

and 27MHz spread clock on pin 6

0*

100MHz differential spreading SRC clock

100MHz non-spreading differential SATA clock

0*

100MHz differential spreading SRC clock

2
2

66MHz 3.3V single ended HTT clock

0*

100MHz differential HTT clock

R223
10KR2J-3-GP

R224
10KR2J-3-GP

R225
10KR2J-3-GP

SEL_SATA
REF1

11

REFCLK_N

14M SE (3.3V)
NC

14M SE (1.8V)
NC

14M SE (1.1V)
vref

GFX_REFCLK

100M DIFF

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

NC

100M DIFF

NC or 100M DIFF OUTPUT

GPPSB_REFCLK

100M DIFF

100M DIFF

100M DIFF

* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.

REF0

REF0
REF1
REF2

100M DIFF
100M DIFF

42

DY

100M DIFF
100M DIFF

REFCLK_P
CLK_SB_25M

SRN10KJ-6-GP

R230
10KR2J-3-GP

CPU_CLK(200MHz)

R232
150R2F-1-GP
1

CLK_NB_14M

1
R235
75R2F-2-GP

<Core Design>

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CLKGEN_ICS9LPRS480
Size

A3
Date:
4

Wistron Corporation
OSC_14M_NB
RS780M 1.1V 158R/90.9R

2008/11/13

RS780

NC

R229
REF1

RN70

DY

RX780

HT_REFCLKP
HT_REFCLKN

2ND = 71.00880.A03

3D3V_S0

RS740
66M SE(SINGLE END)

3D3V_S0

NB CLOCK INPUT TABLE

71.09480.A03

R231
10KR2J-3-GP

12

CLK48_5158E 32

ICS9LPRS480BKLFT-GP

DY

CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1

2
3

CLK_SMBCLK
CLK_SMBDAT

C509

2ND = 82.30005.B11

SC22P50V2JN-4GP

R191 1 0R0402-PAD
2
R192 1 0R0402-PAD
2

GEN_XTAL_IN
GEN_XTAL_OUT

SC22P50V2JN-4GP

11 CLK_PCIE_SB
11 CLK_PCIE_SB#

SMBCLK
SMBDAT

61
62

48
47

X1
X2

VDDATIG
VDDATIG_IO

26
25

VDD_REF
3D3V_48MPW R_S0
PD#

SB A-Link

1
X5
X-14D31818M-35GP
82.30005.891

1 R238
2
0R0603-PAD
C505
SC1U10V2KX-1GP

U20
1D1V_CLK_VDDIO

3D3V_CLK_VDD

DY

10MR2J-L-GP

3D3V_CLK_VDD

SCD1U10V2KX-4GP

C495

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C464

C472

C461
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C454

C460
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C459

R218

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

1D2V_S0

DY
2

DY

1.5Amp

C177
SC180P50V2JN-1GP

SC180P50V2JN-1GP

DY

C174

C703
SCD22U6D3V2KX-1GP

C707
SCD22U6D3V2KX-1GP

DY
2

C706
SC4D7U6D3V3MX-2GP

C704
SC4D7U6D3V3MX-2GP

SC4D7U6D3V3MX-2GP

Place close to socket

C705

ACPU1A

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

HT LINK

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

8
8
8
8

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

N1
P1
P3
P4

8
8
8
8

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

AE2
AE3
AE4
AE5

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

HT_CPU_NB_CLK_H0 8
HT_CPU_NB_CLK_L0 8
HT_CPU_NB_CLK_H1 8
HT_CPU_NB_CLK_L1 8

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8

SKT-CPU638P-GP-U2

62.10055.111
2ND = 62.10040.471 3RD = 62.10040.501

SKT-BGA638H176

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_HT_LINK I/F_(1/4)
Size

A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

ACPU1C
MEM:DATA

Place near to CPU

1

DY
2

1
2

1
2

1
2

1
2

1
2

C252
SC180P50V2JN-1GP

C251
SC180P50V2JN-1GP

C256
SC180P50V2JN-1GP

0D9V_S3

C250
SC180P50V2JN-1GP

DY

C255
SC180P50V2JN-1GP

180P x 6
C249
SC180P50V2JN-1GP

DY

C254
SCD22U6D3V2KX-1GP

C258
SCD22U6D3V2KX-1GP

0.22u X 2
C263
SC4D7U6D3V3MX-2GP

DY

C737
SC4D7U6D3V3MX-2GP

SC4D7U6D3V3MX-2GP

SC4D7U6D3V3MX-2GP

DY

C736

C262

4.7u x 4

750 mA

CLOSE TO CPU
1D8V_S3

ACPU1B

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

16,18 MEM_MA0_CS#0
16,18 MEM_MA0_CS#1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

16,18 MEM_MA_CKE0
16,18 MEM_MA_CKE1

J22
J20

MA_CKE0
MA_CKE1

MEMVREF

W17

1
2

TP106TPAD14-GP

MEM_RSVD_M2 1

TP112

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

MEM_MB0_ODT0 17,18
MEM_MB0_ODT1 17,18

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

MEM_MB0_CS#0 17,18
MEM_MB0_CS#1 17,18

MB_CKE0
MB_CKE1

J25
H26

MEM_MB_CKE0 17,18
MEM_MB_CKE1 17,18

MEM_MB_CLK0_P
MEM_MB_CLK0_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N

MEM_MA_CLK0_P
MEM_MA_CLK0_N
MEM_MA_CLK1_P
MEM_MA_CLK1_N

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

MEM_MB_ADD0 17,18
MEM_MB_ADD1 17,18
MEM_MB_ADD2 17,18
MEM_MB_ADD3 17,18
MEM_MB_ADD4 17,18
MEM_MB_ADD5 17,18
MEM_MB_ADD6 17,18
MEM_MB_ADD7 17,18
MEM_MB_ADD8 17,18
MEM_MB_ADD9 17,18
MEM_MB_ADD10 17,18
MEM_MB_ADD11 17,18
MEM_MB_ADD12 17,18
MEM_MB_ADD13 17,18
MEM_MB_ADD14 17,18
MEM_MB_ADD15 17,18

16,18 MEM_MA_BANK0
16,18 MEM_MA_BANK1
16,18 MEM_MA_BANK2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

MEM_MB_BANK0 17,18
MEM_MB_BANK1 17,18
MEM_MB_BANK2 17,18

16,18 MEM_MA_RAS#
16,18 MEM_MA_CAS#
16,18 MEM_MA_W E#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

MEM_MB_RAS# 17,18
MEM_MB_CAS# 17,18
MEM_MB_W E# 17,18

16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18
16,18

RN48

1
2

N19
N20
E16
F16
Y16
AA16
P19
P20

16
16
16
16

VREF_DDR_CLAW

C391

C388
SCD1U10V2KX-4GP

T19
V22
U21
V19

Y10 VTT_SENSE

SC1KP50V2KX-1GP

RSVD_M1

VTT_SENSE

4
3

SRN1KJ-7-GP

MEM_RSVD_M1

MEMZP
MEMZN

C397
SCD1U10V2KX-4GP

AF10
AE10
H16

16,18 MEM_MA0_ODT0
16,18 MEM_MA0_ODT1

MEMZP
MEMZN

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

1D8V_S3

VTT1
VTT2
VTT3
VTT4

W10
AC10
AB10
AA10
A10

R381
39D2R2F-L-GP
1
2
1
2
R383
39D2R2F-L-GPTP111

D10
C10
B10
AD10

17
17
17
17

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

16
16
16
16
16
16
16
16

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MEM_MB_DATA0 17
MEM_MB_DATA1 17
MEM_MB_DATA2 17
MEM_MB_DATA3 17
MEM_MB_DATA4 17
MEM_MB_DATA5 17
MEM_MB_DATA6 17
MEM_MB_DATA7 17
MEM_MB_DATA8 17
MEM_MB_DATA9 17
MEM_MB_DATA10 17
MEM_MB_DATA11 17
MEM_MB_DATA12 17
MEM_MB_DATA13 17
MEM_MB_DATA14 17
MEM_MB_DATA15 17
MEM_MB_DATA16 17
MEM_MB_DATA17 17
MEM_MB_DATA18 17
MEM_MB_DATA19 17
MEM_MB_DATA20 17
MEM_MB_DATA21 17
MEM_MB_DATA22 17
MEM_MB_DATA23 17
MEM_MB_DATA24 17
MEM_MB_DATA25 17
MEM_MB_DATA26 17
MEM_MB_DATA27 17
MEM_MB_DATA28 17
MEM_MB_DATA29 17
MEM_MB_DATA30 17
MEM_MB_DATA31 17
MEM_MB_DATA32 17
MEM_MB_DATA33 17
MEM_MB_DATA34 17
MEM_MB_DATA35 17
MEM_MB_DATA36 17
MEM_MB_DATA37 17
MEM_MB_DATA38 17
MEM_MB_DATA39 17
MEM_MB_DATA40 17
MEM_MB_DATA41 17
MEM_MB_DATA42 17
MEM_MB_DATA43 17
MEM_MB_DATA44 17
MEM_MB_DATA45 17
MEM_MB_DATA46 17
MEM_MB_DATA47 17
MEM_MB_DATA48 17
MEM_MB_DATA49 17
MEM_MB_DATA50 17
MEM_MB_DATA51 17
MEM_MB_DATA52 17
MEM_MB_DATA53 17
MEM_MB_DATA54 17
MEM_MB_DATA55 17
MEM_MB_DATA56 17
MEM_MB_DATA57 17
MEM_MB_DATA58 17
MEM_MB_DATA59 17
MEM_MB_DATA60 17
MEM_MB_DATA61 17
MEM_MB_DATA62 17
MEM_MB_DATA63 17

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N

17
17
17
17
17
17
17
17

17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17

SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_DDR_(2/4)
Size

A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

The Processor has

reached a preset
maximum operating
temperature. 100
I=Active HTC
O=FAN

8
7
6
5

1D8V_S0

CPU_CLK
CPU_CLK#

1
C7341
C732
LDT_RST#_CPU
HDT_RST#

For HDT DBG

1
2
R74
0R0402-PAD

1D2V_S0

RN44

4CPU_TEST25_H
3CPU_TEST25_L

1
2

For leverage S1g3, please reserve

300 ohm resistor pulldown to VSS

SRN300J-3-GP

2008/11/03

DY

ACPU1D

VDDA1
VDDA2

A9
A8

CLKIN_H
CLKIN_L

B7
A7
F10
C6

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

AF4
AF5
AE6

SIC
SID
ALERT_L

45 CPU_VDD1_RUN_FB_H
45 CPU_VDD1_RUN_FB_L

R104 10R0402-PAD
2CPU_VDD1_RUN_FB_H_RY6
R105 10R0402-PAD
2CPU_VDD1_RUN_FB_L_R
AB6

1D8V_S3
TP93

RN43

4CPU_TEST25_L
3CPU_TEST25_H

TP105
TP103

1CPU_TEST25_H
1CPU_TEST25_L

E9
E8

8
7
6
5

CPU_TEST9

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

DY
LDT_PW ROK

DBREQ_L
TDO

1 R67
2
0R0402-PAD

H_THERMDC
35
H_THERMDA
35
2
C213SC3300P50V2KX-1GP
2008/11/03

CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L

1
1

CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L

E10 CPU_DBREQ#
AE9 CPU_TDO

TP99
TP100
45
45

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

TEST28_H
TEST28_L

J7
H8

CPU_TEST28_H 1
CPU_TEST28_L 1

TP92
TP98

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14

1
1
1
1

TP89
TP90
TP91
TP88

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

CPU_TEST29H
CPU_TEST29L

1
1

TP101
TP102
B

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

H18
H19
AA7
D5
C5

HDT Connectors

SKT-CPU638P-GP-U2

HDT1

DY
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

C205
SCD1U16V2ZY-2GP

Near CPU PIN

LDT_PW ROK

R376
2K2R2J-2-GP

C723
SCD1U16V2ZY-2GP

1D8V_S3

3
5
7
9
11
13
15
17
19
21
23

DY

1
2
R375 0R2J-2-GP

LDT_PW ROK
CPU_PW RGD_SVID_REG

PROCHOT#_SB 11

B 2

LDT_PW ROK_G

DY

TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

R81

84.T3904.C11
2ND = 84.03904.L06

H6
G6

AB8
AF7
AE7
AE8
AC8
AF8

DY 2K2R2J-2-GP

Q8
C
E
MMBT3904-4-GP

45 CPU_PW RGD_SVID_REG

1
1

1 R77
2
0R0402-PAD

RN42
SRN300J-1-GP

VDDNB_FB_H
VDDNB_FB_L

CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27

1
2
3
4

DY
2

R101
10KR2J-3-GP

TP96
TP95
TP187

VDD1_FB_H
VDD1_FB_L

TEST18
TEST19

H10
G9

CPU_TEST21
CPU_TEST20
1

SA

1D8V_S3
3D3V_S0

1
1

W9
Y9

TEST23

CPU_TEST18
CPU_TEST19

THERMTRIP#
PROCHOT#
CPU_MEMHOT#

internal pull high 300 ohm

VDDIO_FB_H
VDDIO_FB_L

AD7

45
45

2008/11/05
AF6
AC7
AA8

VDD0_FB_H
VDD0_FB_L

CPU_TEST23

CPU_SVC
CPU_SVD
2008/11/05

CPU_DBREQ#

THERMTRIP_L
PROCHOT_L
MEMHOT_L

W7
W8

DBRDY
TMS
TCK
TRST_L
TDI

1
1

A6
A4

THERMDC
THERMDA

G10
AA9
AC9
AD9
AF9

TP108
TP107

SVC
SVD

R366
300R2J-4-GP

DY

RN84
SRN300J-1-GP

M11
W18

HT_REF0
HT_REF1

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

SRN300J-3-GP

TP104
TP97
TP94

RN87
SRN1KJ-7-GP

KEY1
KEY2

F8
F9

8
7
6
5

3
4

1D8V_S3

45 CPU_VDD0_RUN_FB_H
45 CPU_VDD0_RUN_FB_L

SA

1D8V_S3

1
2
3
4

1
2

1 CPU_SIC
1 CPU_SID
1CPU_ALERT#

TP186
TP185
TP87

2008/11/11

1
2

CLKCPU_IN
CLKCPU#_IN

LDT_PW ROK
LDT_STP#_CPU
CPU_LDT_REQ#_CPU
TPAD14-GP
TPAD14-GP
TPAD14-GP

2008/11/03

CPU_HTREF0 R6
1
2
R84 1
2 44D2R2F-GP CPU_HTREF1 P6
R83
44D2R2F-GP
R110 10R0402-PAD
2CPU_VDD0_RUN_FB_H_RF6
R108 10R0402-PAD
2CPU_VDD0_RUN_FB_L_R E6

1D8V_S3

For leverage S1g3, please reserve

300 ohm resistor pullup to VDDIO.

DY

1
2
R386
169R2F-GP
2
2SC3900P50V2KX-2GP
SC3900P50V2KX-2GP

2008/11/03
CPU_SIC

C264

2
1

3
3

R364
390R2J-1-GP

C752

DY

SCD22U16V3ZY-GP

Cloce To CPU

C227

SC10U10V5ZY-1GP

1D8V_S3

C745

DY

SC3300P50V2KX-1GP

9 ALLOW _LDTSTOP

C739

SC4D7U10V5ZY-3GP

11 CPU_LDT_STOP#

2D5V_VDDA_S0

1 R401
2
0R0603-PAD

SC10U10V5ZY-1GP

1
R86
1
R79
1
R72

11,52 CPU_PW RGD

2D5V_S0

2
LDT_RST#_CPU 9
0R2J-2-GP
LDT_PW ROK
2
0R0402-PAD
2
LDT_STP#_CPU 9
0R0402-PAD
CPU_LDT_REQ#_CPU
2
0R0402-PAD

R78 1

11,52 CPU_LDT_RST#

LYAOUT:ROUTE VDDA TRACE APPROX.

50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491

1
2
3
4
D

C196
SC100P50V2JN-3GP

1DY

RN40
SRN300J-1-GP

THERMTRIP#

1
2
1D8V_SUS_Q2

Q24
E
C
MMBT3904-4-GP

SMC-CONN26A-FP
HDT_RST#
RSMRST#

<Core Design>

35,36

84.T3904.C11
2ND = 84.03904.L06

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

CPU exceeds to 125

Title
Size

A3
Date:
5

4
6
8
10
12
14
16
18
20
22
24
26

CPU_Control&Debug_(3/4)
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

DY

DY

DY

DY
2

1
2

2
1

1
2

2
1
2

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SKT-CPU638P-GP-U2

C351 C362 C385 C379 C375 C365 C358 C361 C347 C363 C378

SCD22U6D3V2KX-1GP

Bottom Side Decoupling

3A for VDDIO
1D8V_S3
Place near to CPU

SCD22U6D3V2KX-1GP

3A for VDDIO
1D8V_S3

DY

SCD01U50V2KX-1GP

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

DY

SCD01U50V2KX-1GP

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

DY

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

C193 C154 C308 C280 C253 C293 C312

SC180P50V2JN-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

Bottom Side Decoupling

SC10U6D3V5KX-1GP

C808

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

SC10U6D3V5KX-1GP

C324

K16
M16
P16
T16
V16

VCC_CORE_S0_1

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

SCD22U6D3V2KX-1GP

3A for VDDNB

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SCD22U6D3V2KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VDDNB

add 0.1U
C316

DY

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

SC180P50V2JN-1GP

DY

C239 C281 C286 C295 C206 C244 C315

SC10U6D3V5KX-1GP

C392 C398 C381 C356 C372 C349

DY

DY
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP

ACPU1E

Bottom Side Decoupling

SC10U6D3V5KX-1GP

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

36A for VDD0&VDD1

VCC_CORE_S0_0

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

ACPU1F

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

SKT-CPU638P-GP-U2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CPU_Power_(4/4)
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

ANB1A

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

4
4
4
4

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_NB_CPU_CLK_H0 4
HT_NB_CPU_CLK_L0 4
HT_NB_CPU_CLK_H1 4
HT_NB_CPU_CLK_L1 4

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP
PCE_CALRN

AC8
AB8

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

4
4
4
4

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

4
4
4
4

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

M22
M23
R21
R20
C23
A24

2 R344
301R2F-GP

HT_RXCALP
HT_RXCALN

Place < 100mils from pin C23 and A24

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_TXCALP
HT_TXCALN

4
4
4
4

4
4
4
4
4
4
4
4
4
4
4
4

Placement: close RS780

2 R343
301R2F-GP

Place < 100mils from pin B25 and B24

RS780M-GP-U2

Placement: close RS780

ANB1B

53 PEG_RXP[15..0]

26
26
33
33
33
33
34
34

2008/11/05
2008/11/05
2008/11/05

LAN
MINICARD1
MINICARD2
NEW CARD
TPAD14-GP
TPAD14-GP

A-LINK

11
11
11
11
11
11
11
11

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX5P
GPP_RX5N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
PCIE_RXP3
PCIE_RXN3
PCIE_RXP5
PCIE_RXN5

TP21
TP20

ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3

PART 2 OF 6

PCIE I/F GFX

53 PEG_RXN[15..0]

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

PCIE I/F GPP

PCIE I/F SB

RS780M-GP-U2

GTXP0
GTXN0
GTXP1
GTXN1
GTXP2
GTXN2
GTXP3
GTXN3
GTXP4
GTXN4
GTXP5
GTXN5
GTXP6
GTXN6
GTXP7
GTXN7
GTXP8
GTXN8
GTXP9
GTXN9
GTXP10
GTXN10
GTXP11
GTXN11
GTXP12
GTXN12
GTXP13
GTXN13
GTXP14
GTXN14
GTXP15
GTXN15

1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS
1
DIS

TXP0
TXN0
TXP1
TXN1
TXP3
TXN3
TXP5
TXN5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

C617
C616
C592
C593
C614
C615
C591
C590
C613
C612
C589
C588
C611
C610
C587
C586
C609
C608
C585
C584
C607
C606
C583
C582
C605
C604
C581
C580
C602
C603
C579
C578

C621
C622
C597
C596
C599
C598
C600
C601

1
1
1
1
1
1
1
1

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

2
2
2
2
2
2
2
2

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

GPP_TX5P
GPP_TX5N

TP16
TP17

ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3
PCE_PCAL
PCE_NCAL

C642
C640
C632
C637
C627
C629
C624
C625

1
R315 1
R16

1
1
1
1
1
1
1
1

PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15

2
2
2
2
2
2
2
2

RS780M Display Port Support(muxed on GFX)

DP0 GFX_TX0,TX1,TX2,TX3,AUX0,HPD0
DP1 GFX_TX4,TX5,TX6,TX7,AUX1,HPD1
GTXP0
GTXN0
GTXP1
GTXN1
GTXP2
GTXN2
GTXP3
GTXN3

PCIE_TXP1
PCIE_TXN1
PCIE_TXP2
PCIE_TXN2
PCIE_TXP3
PCIE_TXN3
PCIE_TXP5
PCIE_TXN5

UMA
UMA
UMA
UMA
UMA
UMA
UMA
UMA

ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3

MINICARD2
NEW CARD

11
11
11
11
11
11
11
11

2
2
2
2
2
2
2
2

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

HDMI_DATA2+ 21
HDMI_DATA2- 21
HDMI_DATA1+ 21
HDMI_DATA1- 21
HDMI_DATA0+ 21
HDMI_DATA0- 21
HDMI_CLK+ 21
HDMI_CLK- 21

2008/11/05

<Core Design>

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Wistron Corporation

1D1V_S0

Place < 100mils from pin AC8 and AB8

3

1
1
1
1
1
1
1
1

LAN 2008/11/05
MINICARD1 2008/11/05

26
26
33
33
33
33
34
34

Date:
5

C30
C29
C27
C26
C25
C22
C21
C19

TPAD14-GP
TPAD14-GP

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

2
2 1K27R2F-L-GP
2KR2F-3-GP

PEG_TXP[15..0] 53
PEG_TXN[15..0] 53

ATi-RS780M_HT LINK&PCIe(1/3)
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

STRAP_DEBUG_BUS_GPIO_ENABLEb

3D3V_S0_AVDD

2
1

220ohm 200mA

RN14
SRN3K3J-1-GP

C70
SBK160808T-221Y-N-GP
C71
DYSCD1U10V2KX-4GP
68.00119.111SC1U10V2KX-1GP

SCD1U10V2KX-4GP
11 NB_ALLOW _LDTSTOP

RN11

1
2

ENABLE External CLK GEN

C25
C24

HT_REFCLKP
HT_REFCLKN

E11
F11

REFCLK_P/OSCIN
REFCLK_N

CLK_NB_14M

3 CLK_NB_GFX
3 CLK_NB_GFX#

C97
SCD1U10V2KX-4GP

NB_REFCLK_N

T2
T1

GFX_REFCLKP
GFX_REFCLKN

CLK_NBGPP_CLK
CLK_NBGPP_CLK#

U1
U2

GPP_REFCLKP
GPP_REFCLKN

3 CLK_NB_GPPSB
3 CLK_NB_GPPSB#

21 GMCH_HDMI_CLK
21 GMCH_HDMI_DATA

GMCH_HDMI_CLK
GMCH_HDMI_DATA

C42

STRP_DATA

DY SCD1U10V2KX-4GP

V4
V3

GPPSB_REFCLKP
GPPSB_REFCLKN

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_CLK0/AUX0P
DDC_DATA0/AUX0N
DDC_CLK1/AUX1P
DDC_DATA1/AUX1N

B10

STRP_DATA

G11

RESERVED

GPIO MODE
VCC_NB

*1

RS780_AUX_CAL

1.1V 1.0V

GMCH_TXBOUT0+
GMCH_TXBOUT0GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT2+
GMCH_TXBOUT2-

19
19
19
19
19
19

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

B16
A16
D16
D17

GMCH_TXACLK+
GMCH_TXACLKGMCH_TXBCLK+
GMCH_TXBCLK-

A13
B13

19
19
19
19

1D8V_S0

VDDLT18_1
VDDLT18_2
VDDLT33_1
VDDLT33_2

A15
B15
A14
B14

VSSLT1
VSSLT2
VSSLT3
VSSLT4
VSSLT5
VSSLT6
VSSLT7

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL

1D8V_S0_VDDLP18

C649
SC1U10V2KX-1GP

C648 SBK160808T-221Y-N-GP
SCD1U10V2KX-4GP
68.00119.111

DY

2ND
L35 = 68.00217.521
1
2
PBY201209T-221Y-N-GP

1D8V_S0_VDDLT18
C652
SC4D7U6D3V3KX-GP

2ND = 68.00216.161
DY C653
SCD1U10V2KX-4GP

E9
GMCH_BL_ON
F7
G12 LVDS_ENA_BL

GMCH_LCDVDD_ON
GMCH_BL_ON 36
TP26 TPAD14-GP

RN10

2
1

19

3
4

SRN4K7J-8-GP
R31

MIS.
DDC_DATA0/AUX0N
DDC_CLK0/AUX0P

TMDS_HPD
HPD

D9
D10

NB_DVI_HPD

SUS_STAT#

D12

SUS_STAT#

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

DY

2 100KR2J-1-GP

HDMI_DETECT# 21
TP24 TPAD14-GP

2
R29
RS780_DXP3_1
RS780_DXN3_1

C8

1
10KR2J-3-GP

3D3V_S0
TP23
TP22

TPAD14-GP
TPAD14-GP

D13 TESTMODE_NB

AUX_CAL

R347
1K8R2F-GP

STRP_DATA

VDDA18HTPLL

CLK_NB_GFX
CLK_NB_GFX#

19 CLK_DDC_EDID
19 DAT_DDC_EDID

1
2

TPAD14-GP
TP180
TPAD14-GP
TP181

VDDA18PCIEPLL

SBK160808T-221Y-N-GP
C41
SC1U10V2KX-1GP

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

4
3

SRN1KJ-7-GP

68.00119.111
2ND = 68.00217.521

220ohm 200mA

D8
A10
C10
C12

3 CLK_NBHT_CLK#

B18
A18
A17
B17
D20
D21
D18
D19

VDDLTP18
VSSLTP18

PLLVDD
PLLVDD18
PLLVSS

VDDA18PCIEPLL1
VDDA18PCIEPLL2

2008/11/10 3 CLK_NBHT_CLK
1D1V_S0

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

DAC_RSET

D7
E7

NB_LDT_STOP#
NB_ALLOW _LDTSTOP

19
19
19
19
19
19

L34

VDDA18PCIEPLL

2
1

1
2

77.C1071.081
2ND = 77.21071.07L

NB_PW RGD

GMCH_TXAOUT0+
GMCH_TXAOUT0GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT2+
GMCH_TXAOUT2-

1
2

SBK160808T-221Y-N-GP
C86 DY
SC1U10V2KX-1GP

SC47U6D3V5MX-1-GP

12,42

DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA

H17

SYSREST#
C77

VDDA18HTPLL

L1

DY

68.00119.111
2ND = 68.00217.521

220ohm 200mA

1D8V_S0

C78
SC1U10V2KX-1GP

ST100U6D3VBM-5GP

L5

220ohm
200mA
SBK160808T-221Y-N-GP

A11
B11
F8
E8

VDDA18HTPLL

L4

68.00119.111
C82
DY
2ND = 68.00217.521

RED
REDb
GREEN
GREENb
BLUE
BLUEb

R33 2DAC_RSET
1
G14
715R2F-GP 2008/11/04
A12
1D8V_S0_PLVDD18
D14
B12

1D1V_S0_PLLVDD

C643
220ohmSBK160808T-221Y-N-GP
200mA
C644
DY SCD1U10V2KX-4GP

1D8V_S0

SC1U10V2KX-1GP
2

2ND = 68.00217.521
68.00119.111

1D8V_S0

L33

R69 BOM Option

TC1

1D1V_S0

6 ALLOW _LDTSTOP

NB_LDT_STOP#
2
0R2J-2-GP
R24
1
2 NB_ALLOW _LDTSTOP
0R2J-2-GP

LDT_STP#_CPU

DY

R14
1

G18
G17
E18
F18
E19
F19

A22
B22
A21
B21
B20
A20
A19
B19

20 GMCH_HSYNC
20 GMCH_VSYNC
20 GMCH_DDCCLK
20 GMCH_DDCDATA

R25
1KR2F-3-GP

2008/11/06

C_Pr
Y
COMP_Pb

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

GMCH_BLUE

E17
F17
F15

PART 3 OF 6

20 GMCH_GREEN
20

AVDD1
AVDD2
AVDDDI
AVSSDI
AVDDQ
AVSSQ

GMCH_RED

F12
E12
F14
G15
H15
H14

1D8V_S0_AVDDQ

77.C1071.081
2ND = 77.21071.07L

DY

1D8V_S0

C99
SCD1U10V2KX-4GP

C80
SC1U10V2KX-1GP

20

140R2F-GP

150R2F-1-GP

150R2F-1-GP

GMCH_RED
R38

GMCH_GREEN

R37

ANB1C

220ohmSBK160808T-221Y-N-GP
200mA

ST100U6D3VBM-5GP

GMCH_BLUE

TC2

Close to NB ball

2008/11/04

R36

1
2
3
4

68.00119.111
2ND = 68.00217.521

R43

1D8V_S0

0 : Enable

Selects Loading of STRAPS From EEPROM

the loading of EEPROM straps and use Hardware Default Values
*10 :: Bypass
I2C Master can load strap values from EEPROM if connected,
or use default values if not connected

CRT/TVOUT

C37
SC220P50V2KX-3GP

:Disable

SUS_STAT#

C89
SCD1U10V2KX-4GP

PLL PWR
LVTM

2008/12/08

GMCH_VSYNC
GMCH_HSYNC

*1

1D8V_S0_AVDDDI

CLOCKs PM

2
0R2J-2-GP

R41 2
1
0R0603-PAD
C88
SC1U10V2KX-1GP

SYSREST#

PLT_RST1#

1D8V_S0

D 11,26,33,36

DY

LDT_RST#_CPU

0R2J-2-GP

Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#)

:Disable
0 : Enable

*1

RS780: Enables Side port memory ( RS780 use HSYNC#)

2ND = 68.00217.521
R21
1
R17
1

3D3V_S0

L3

8
7
6
5

3D3V_S0

R294
150R2F-1-GP

RS780M-GP-U2

3D3V_S0

R19

<Core Design>

DY 2K2R2J-2-GP

Wistron Corporation

STRP_DATA

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

ATi-RS780M_LVDS&CRT_(2/3)

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

of

61

ANB1F

1
2

C46

C85

C76

DY

C79

DY

C60

1
2

C90

1
2

1
2

C74

DY

1 R316
2
0R0603-PAD

3D3V_S0

C66
SCD1U10V2KX-4GP

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

1 R30
2
0R0603-PAD
1

+3.3V_RUN_VDD33

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

DY

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M-GP-U2

C65
SCD1U10V2KX-4GP

2
1

AE10
AA11
Y11
AD10
AB10
AC10

RS780M-GP-U2

SC1U10V2KX-1GP

VDD_MEM

2
1

1
2

C36

1
2
1

2
1
2
1

1
2

1
2
1
2

1
2
1

1
2

POWER

1
2

1
2

2
1
2
1
2
1
2

C52

SC10U6D3V3MX-GP

VDD33_1
VDD33_2

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

H11
H12

1D1V_S0

RS780M: 1V ~ 1.1V, check PWR team

SC10U6D3V3MX-GP

C651

VDD18_1
VDD18_2
VDD18_MEM1
VDD18_MEM2

+NB_VCORE

Per check list (Rev 0.02)

SCD1U10V2KX-4GP

F9
G9
AE11
AD11

+1.8V_RUN_VDD18_MEM

VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6

C40
SC4D7U6D3V3KX-GP

10A per ANT Rev1.1, Page3

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

C68

SCD1U10V2KX-4GP

C47

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

1103

C55

DY

SCD1U10V2KX-4GP

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C49

SCD1U10V2KX-4GP

C61

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

1 R320
2
0R0603-PAD

DY

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

C83

DY

SCD1U10V2KX-4GP

C57

SCD1U10V2KX-4GP

C59

C101

DY

+1.8V_RUN_VDDA18PCIE
C53

SCD1U10V2KX-4GP

1D8V_S0

C62

SC4D7U6D3V3KX-GP

2ND = 68.00216.161

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

SCD1U10V2KX-4GP

C63

SC4D7U6D3V3KX-GP

220 ohm @ 100MHz,2A

80mil Width

SCD1U10V2KX-4GP

1
2
PBY201209T-221Y-N-GP

DY

SCD1U10V2KX-4GP

L2

SCD1U10V2KX-4GP

1D8V_S0
C

+1.2V_RUN_VDDHTTX
C104
C95

C111

SC4D7U6D3V3KX-GP

2ND = 68.00216.161

DY

300mil Width

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

SCD1U10V2KX-4GP

C673

220 ohm @ 100MHz,2A

SCD1U10V2KX-4GP

L38
1
2
PBY201209T-221Y-N-GP

DY

SCD1U10V2KX-4GP

1D2V_S0

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

2ND = 68.00216.161

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

SC1U10V2KX-1GP

C677

220 ohm @ 100MHz,2A

H18
G19
F20
E21
D22
B23
A23

PART 5/6

SC1U10V2KX-1GP

1
2
PBY201209T-221Y-N-GP

+1.1V_RUN_VDDHTRX
C674
C106
C102

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

SCD1U10V2KX-4GP

0.45A per ANT Rev1.1, Page3

L40

J17
K16
L16
M16
P16
R16
T16

SCD1U10V2KX-4GP

1D1V_S0

DY

1D1V_S0

ANB1E
SCD1U10V2KX-4GP

DY

SCD1U10V2KX-4GP

2ND = 68.00216.161

+1.1V_RUN_VDDHT
C659
C94
SCD1U10V2KX-4GP

220 ohm @ 100MHz,2A

C91

SC4D7U6D3V3KX-GP

C655

L36
1
2
PBY201209T-221Y-N-GP

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

GROUND

0.6A per ANT Rev1.1, Page3

1D1V_S0

ANB1D

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

AD16
AE17
AD17

MEM_BA0
MEM_BA1
MEM_BA2

W12
Y12
AD18
AB13
AB18
V14

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

V15
W14

MEM_CKP
MEM_CKN

SBD_MEM/DVO_I/F

PAR 4 OF 6
MEM_DQ0/DVO_VSYNC
MEM_DQ1/DVO_HSYNC
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ4
MEM_DQ5/DVO_D1
MEM_DQ6/DVO_D2
MEM_DQ7/DVO_D4
MEM_DQ8/DVO_D3
MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6
MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9
MEM_DQ14/DVO_D10
MEM_DQ15/DVO_D11

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP
MEM_DQS0N/DVO_IDCKN
MEM_DQS1P
MEM_DQS1N

Y17
W18
AD20
AE21

MEM_DM0
MEM_DM1/DVO_D8

W17
AE19

IOPLLVDD18
IOPLLVDD

AE23
AE24

IOPLLVSS

AD23

Wistron Corporation

MEM_VREF

AE18

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

AE12
AD12

MEM_COMP_P and MEM_COMP_N trace

width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

MEM_COMPP
MEM_COMPN

1D8V_S0

1 R339
2
0R0402-PAD

+1.8V_IOPLLVDD18

1D1V_S0

1 R341
2
0R0402-PAD

<Core Design>

+1.1V_IOPLLVDD

RS780M-GP-U2
Title

ATi-RS780M_Side Port&PWR&GND(3/3)

Size
A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

10

of

61

ASB1A

DY

2
10MR2J-L-GP

CLK_SB_25M

R440
2
0R2J-2-GP

R164
10MR2J-L-GP

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

1CLK_SB_25M_1L18
TP209
TPAD14-GP

25M_48M_66M_OSC

J21

TP210
TPAD14-GP

J20

25M_X1

25M_X2

NB_ALLOW _LDTSTOP
6 PROCHOT#_SB
6,52 CPU_PW RGD
6 CPU_LDT_STOP#
6,52 CPU_LDT_RST#

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

RTCCLK
INTRUDER_ALERT#
VBAT

LPC

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15
C3
C2
B2

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

TP124
TP119
TP198
TP115
TP197
TP117
TP121
TP118
TP192
TP120

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

TP201

TPAD14-GP

TP116
TP191
TP123
TP122

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

PM_CLKRUN# 36

PCI_LOCK#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
LPCCLK0_R
LPCCLK1_R

C407

1
1

36,37

PCLK_FW H 15,37
PCLK_KBC 15,36

SC22P50V2JN-4GP
ARTC1

C409

DY

TP148 TPAD14-GP
1
2
R158
1KR2J-1-GP
SCD1U16V2ZY-2GP

DY

LPC_LAD[0..3]

DY 2
DY 2SC22P50V2JN-4GP

C408

SC1U10V2KX-1GP

LPC_LAD[0..3]

RN51
4 SRN22-3-GP
3

1
2

INTRUDER#
RTC_AUX_S5_R

R126
10KR2J-3-GP DY

EC48
LPC_LAD0 36,37
EC47
LPC_LAD1 36,37
LPC_LAD2 36,37
LPC_LAD3 36,37
LPC_LFRAME# 36,37
LDRQ0#
TP213 TPAD14-GP
LDRQ1#
TP193 TPAD14-GP
PCI_REQ#5
PCI_REQ#5
12
INT_SERIRQ 36
RTC_AUX_S5
RTC_CLK
15,35

SB700-1-GP-U1
A

15
15
15
15
15
15
15
15

SCD1U16V2ZY-2GP

2008/11/069

X2

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

RTC

B3

CPU

82.30001.691

2 2ND
1 = 82.30001.861 32K_X2
C433
SC15P50V2JN-2-GP

X1

RTC XTAL

A3

X4

GPP_CLK1P
GPP_CLK1N

32K_X1

3
X-32D768KHZ-38GPU

2
1
C424 SC15P50V2JN-2-GP

2008/11/06
3

L20
L19

DY
1
R162

GPP_CLK0P
GPP_CLK0N

PCI INTERFACE

14
7

For SB710

J19
J18

CLOCK GENERATOR

SC1U10V2KX-1GP

SC1U10V2KX-1GP

73.07408.L16
2ND = 73.07408.L15
3RD = 73.07408.02B

SLT_GFX_CLKP
SLT_GFX_CLKN

32,33,34,37,53

TSLVC08APW -1-GP

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

PLT_RST1#_B

9,26,33,36 PLT_RST1#

P17
M18

NB_HT_CLKP
NB_HT_CLKN

M24
M25

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30

1
2
NP1
NP2

U16A

3D3V_S5

DY DY DY DY

NB_DISP_CLKP
NB_DISP_CLKN

TPAD14-GP

K23
K22

3 CLK_PCIE_SB
3 CLK_PCIE_SB#

TP138

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

Place R <100mils form pins T25,T24

PCI_CLK2
15
PCI_CLK3
15
CLK_PCI4
15
CLK_PCI_LOM 15

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

N25
N24

C811

PCIRST#_SB

PCIE_PVSS

PCI EXPRESS INTERFACE

PCIE_PVDD

P25

C810

2ND = 68.00216.161

220 ohm 2A

1
2
PBY201209T-221Y-N-GP

PCIE_CALRP
2 562R2F-GP
2 2K05R2F-GP PCIE_CALRN

1
1

N1

R144
R141
R137
R138

TPAD14-GP
TPAD14-GP

SC22P50V2JN-4GP

PCIE_CALRP
PCIE_CALRN

P24

R143
R147

>15mil Width 43 mA

PCIRST#

TP204
TP203
1
2
10R0402-PAD
2
10R0402-PAD
2
10R0402-PAD
2
0R0402-PAD

EC40

T25
T24

PCIE_VDDR

PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R

SC22P50V2JN-4GP

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3

P4
P3
P1
P2
T4
T3

SC22P50V2JN-4GP

U22
U21
U19
V19
R20
R21
R18
R17

8
8
8
8
8
8
8
8

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

EC39

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

+1.2V_RUN_PCIE_PVDD

L24

Part 1 of 5

SC22P50V2JN-4GP

1D2V_S0

SB700
A_RST#

EC41

2
2
2
2
2
2
2
2

N2

ALINK_NBRX_C_SBTX_P0
ALINK_NBRX_C_SBTX_N0
ALINK_NBRX_C_SBTX_P1
ALINK_NBRX_C_SBTX_N1
ALINK_NBRX_C_SBTX_P2
ALINK_NBRX_C_SBTX_N2
ALINK_NBRX_C_SBTX_P3
ALINK_NBRX_C_SBTX_N3

V23
V22
V24
V25
U25
U24
T23
T22

ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3

1
1
1
1
1
1
1
1

NB_RST#

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

EC42

8
8
8
8
8
8
8
8

C774
C777
C779
C787
C794
C791
C802
C801

PCI CLKS

R146
33R2J-2-GP
1
2

9,26,33,36 PLT_RST1#

PWR
GND
NP1
NP2

BAT-CON2-1-GP-U

62.70001.011

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_PCIE&PCI_(1/5)
Size
A3
Date:
5

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

11

of

61

1
R419

E1
E2
H7
F5
34,35,36,42,44,49,60 PM_SLP_S3#
G1
34,36,48 PM_SLP_S5#
H2
36,52 PM_PW RBTN#
H1
42
SB_PW RGD
PM_SUS_STAT# K3
TP208
TPAD14-GP
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
36
KA20GATE
W15
36
KBRCIN#
K4
36
ECSCI#_1
ECSMI#_KBC
K24
TPAD14-GP
GEVENT5#
F1
TP141
TPAD14-GP
SYS_RST#
J2
TP139
H6
26,34 PCIE_W AKE#
EC_TMR
F2
36
EC_TMR
SMB_ALERT#
J6
NB_PW RGD_R
W14

NB_PW RGD

2
300R2J-4-GP

DY

1
R411

FP_ID

2
10KR2J-3-GP

3D3V_S5

1
R445
1
R443
1
R442

DY

DY

DY

SB_TEST2
2K2R2F-GP
SB_TEST1
2K2R2F-GP

3D3V_S0

SB_TEST0
2K2R2F-GP

RSMRST#_KBC

ICH_PME#

2
10KR2J-3-GP

DY

DY

R410
1KR2F-3-GP

PCIE_W AKE#
10KR2J-3-GP
SMB_ALERT#

DY

10KR2J-3-GP

38

FP_ID
GPIO6
GPIO4

AE18
AD18
AA19
W17
V17
W20
W21
SMBC0_SB AA18
SMBD0_SB W18
SMB_CLK
K1
SMB_DATA
K2
DDC1_SCL
AA20
DDC1_SDA
Y18
SATA_DET#
C1
GPIO5
Y19
GEVENT7#
G5

FP_ID
TPAD14-GP
TPAD14-GP

GPIO0/HDMI

TP190
TP194

2008/11/06
RN97

8
7
6
5

PM_SLP_S5#
ECSCI#_1
ECSW I#
PM_SLP_S3#

1
2
3
4

28

ACZ_SPKR

SRN10KJ-6-GP

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

RN95

1 RSMRST#_KBC
2
ECSMI#_KBC
3
4 PCI_REQ#5

8
7
6
5

3D3V_S5
3D3V_S0

D3

USBCLK/14M_25M_48M_OSC

C8

USB_RCOMP

G8

PCI_REQ#5

TP196
TP199
TP149
TP200
TP218

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

11

RN47

1
2

31 ACZ_SDATAOUT_MDC
28 ACZ_SDATAOUT
28 ACZ_SDATAIN0
31 ACZ_SDATAIN1

ACZ_BIT_CLK
ACZ_SDATAOUT_R

4
3

SRN33J-5-GP-U
TPAD14-GP
RN96 SRN33J-5-GP-U TPAD14-GP
1
4
2
3

ACZ_SYNC
ACZ_RST#

ACZ_RST#_R

TP212
TP214
TP216

1
1
1

IMC_GPIO0
IMC_GPIO1
IMC_GPIO2
IDE_RST#

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

10KR2J-3-GP TP221
TP147
TP145
TP222

1
1
1
1

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

3D3V_S0

R152

1
5
6
7
8

NEWCARD /GLAN
RN53

4
3
2
1

SRN4K7J-10-GP

DY

1
1 DY2
DY 2CLK48_USB_R2 C432
R161
10KR2J-3-GP
SC10P50V2JN-4GP

Place these close SB700

E6
E7

USB_FSD12P
USB_FSD12N

F7
E8

USB_HSD11P
USB_HSD11N

H11
J10

USB_HSD10P
USB_HSD10N

E11
F11

USBPP8
USBPN8

19
19

USB_HSD9P
USB_HSD9N

A11
B11

USBPP4
USBPN4

33
33

Pair

USB_HSD8P
USB_HSD8N

C10
D10

USBPP3
USBPN3

25
25

11

CardReader

10

WEBCAM

USB_HSD7P
USB_HSD7N

G11
H12

USBPP1
USBPN1

25
25

USB_HSD6P
USB_HSD6N

E12
E14

USBPP2
USBPN2

25
25

USB_HSD5P
USB_HSD5N

C12
D12

USBPP5
USBPN5

24
24

USB_HSD4P
USB_HSD4N

B12
A12

USB_HSD3P
USB_HSD3N

G12
G14

USBPP6
USBPN6

38
38

USB_HSD2P
USB_HSD2N

H14
H15

USBPP9
USBPN9

34
34

USB_HSD1P
USB_HSD1N

A13
B13

USBPP7
USBPN7

33
33

USB_HSD0P
USB_HSD0N

B14
A14

USBPP0
USBPN0

25
25

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

Place R near pin14. Route it with 10mils

Trace width and 25mils spacing to any
signals in X, Y, Z directions.
USBPP10 32
USBPN10 32

SB_GPO16
SB_GPO17

USB
Device

MINIC2

USB4

USB3

USB2

Bluetooth

NC

OCP1#

Fringer print

NEW1

MINIC1

USB1

OCP0#

2008/11/05

15
15

Strap Pin / define to use LPC or SPI ROM

B

SB700-1-GP-U1

<Core Design>

C859
SC100P50V2JN-3GP

CLK48_USB

USB_FSD13P
USB_FSD13N

SMB_CLK
SMB_DATA
SMBC0_SB
SMBD0_SB

26,33,34
26,33,34
3,16,17
3,16,17

15

TO STRAPS

3D3V_S0
3D3V_S5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

2
1

2
1

2
1

1
1

DY

10KR2J-3-GP

DY DY DY DY DY

R151
SC12P50V2JN-3GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

10KR2J-3-GP

10KR2J-3-GP

DY DY

SC12P50V2JN-3GP

R439 R448

EC45 EC44 EC43 EC80 EC82

M1
M2
J7
J8
ACZ_SDIN2
L8
TP206
ACZ_SDIN3
M3
TP205
ACZ_SYNC_R
L6
ACZ_RST#_R M4
TP207
GPM8# L5
1

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

INTEGRATED uC

28
ACZ_BITCLK
31 ACZ_BTCLK_MDC

TPAD14-GP
USB_OC#5
TP151
USB_OC#4
25
USB_OC#4
34
CPPE#
USB_OC#2
TPAD14-GP
TP220
USB_OC#1
TPAD14-GP
TP150
25
USB_OC#0

INTEGRATED uC

RN49
SRN33J-5-GP-U
1
4
2
3

B9
B8
A8
A9
E5
F8
E4

USB OC

Close to SB700

ECSW I#

HD AUDIO

36

CLK48_USB
USB_PCOMP 1
R167
11K8R2F-GP

1%

RSMRST#

SRN10KJ-6-GP

28,31
28,31

Part 4 of 5

SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

36 RSMRST#_KBC

1
R154
1
R444
1
R441

1ICH_PME#
1 RI#
1 S2#

TP143
TP142
TP211

USB MISC

3D3V_S0

ASB1D

USB 1.1

NB_PW RGD_R
1
0R2J-2-GP

1D8V_S0

USB 2.0

DY

GPIO

2
R422

NB_PW RGD

ACPI / WAKE UP EVENTS

9,42

2008/12/17

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C857
SC100P50V2JN-3GP
Title

ATi-SB700_USB&GPIO_(2/5)
Size
A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

12

of

61

PLACE SATA AC DECOUPLING

CAPS CLOSE TO SB700
ASB1B

SATA_RXN1
SATA_RXP1

C449 1
C446 1

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

SATA_RXN1_C AD11
SATA_RXP1_C AE11

SATA_RX1N
SATA_RX1P

AB12
AC12

SATA_TX2P
SATA_TX2N

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

AE14
AD14

SATA_TX4P
SATA_TX4N

AD15
AE15

SATA_RX4N
SATA_RX4P

2008/12/11
1

R434
1KR2F-3-GP
1
2

Very Close to SB700

C373
XTAL-25MHZ-120-GP-U
SC15P50V2JN-2-GP X3 R127
10MR2J-L-GP

82.30020.A31
2ND = 82.30020.851
2

SATA_X2_R

1
R128

C367
SC15P50V2JN-2-GP
1D2V_S0

SATA_TX5P
SATA_TX5N

AE16
AD16

SATA_RX5N
SATA_RX5P

SATA_CAL

V12

SATA_CAL

SATA_X1

Y12

SATA_X1

SATA_X2AA12

SATA_X2

2
300R2J-4-GP
39

AB16
AC16

W11

MEDIA_LED#

PLLVDD_SATA

W12

XTLVDD_SATA

1
2

C785

DY

3D3V_S0
B

XTLVDD_SATA

SCD1U10V2KX-4GP

C784
SC1U10V2KX-1GP

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

P5
P8
R8

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

AVDD

F6

AVSS

G7

C778
SC1U10V2KX-1GP

CLK_ID_0
CLK_ID_1

Dummy CKG select

3D3V_S0

LAN_RST#
ROM_RST#

TP217
TP146
TP144
TP215
TP219

CLK_ID_1
CLK_ID_0

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

R407
10KR2J-3-GP

R412
10KR2J-3-GP

RTM

SEG

TP202 TPAD14-GP
TP140 TPAD14-GP

R416
10KR2J-3-GP

R413
10KR2J-3-GP

ICS+SEG

ICS+RTM

ALERT#

CLK_ID
(1,0)
ICS: 0,0
SEG: 0,1
RTM: 1,0

35

PSW _CLR#
B

PSW _CLR#
AVDD_HW M

>15mil Width
1 R428
2
0R0603-PAD

G6
D2
D1
F4
F3

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

2008/11/06

SB_SPI_MISO
SPI_MOSI_R
ICH_SPICLK
SB_SPI_HOLD
ICH_SPICS0#

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

SATA_ACT#/GPIO67

AA11

>15mil Width

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

M8
M5
M7

93 mA

PLLVDD_SATA

1 R426
2
0R0603-PAD

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SATA_TX1P
SATA_TX1N

23
23

SATA_TXP1_C AE10
SATA_TXN1_C AD10

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

C369 1
C368 1

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

SATA_TXP1
SATA_TXN1

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

SATA_RX0N
SATA_RX0P

23
23

Part 2 of 5

SATA_RXN0_C AB10
SATA_RXP0_C AC10

SATA_RXN0
SATA_RXP0

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

22
22

C687 1
C686 1

ATA 66/100/133

SATA_TX0P
SATA_TX0N

SPI ROM

AD9
AE9

22
22

HW MONITOR

SATA ODD

SB700

SATA_TXP0
SATA_TXN0

SATA_TXP0_C
SATA_TXN0_C

SERIAL ATA

SATA HDD

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

SATA PWR

C370 1
C371 1

3D3V_S5

G106

>15mil Width

RN98
MEDIA_LED#
PSW _CLR#
ALERT#

GAP-OPEN

C423

DY
2

1
2

SC2D2U6D3V3KX-GP

3D3V_S0

1
2
3
4

C418

SCD1U10V2KX-4GP

SB700-1-GP-U1

8
7
6
5

1 R163
2
0R0603-PAD

Layout connect to Cap then GND

SRN10KJ-6-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_SATA-IDE_(3/5)
Size

A3
Date:
5

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

13

of

61

ASB1C

SB700-1-GP-U1

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

1
2
1
2

1
2

1
2

3D3V_AVDDC

DY

1
1

17mA

C434
SC10U6D3V3MX-GP

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

C437

C436

2ND = 68.00216.161

>15mil Width

1KR2J-1-GP
D26

H18
J17
J22
K25
M16
M17
M21
P16

3D3V_S0

A
RB751V-40-2-GP

83.R2004.B8F
2ND = 83.R0304.A8F
3RD = 83.R3004.A8F

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
B

L17

SB700-1-GP-U1

47 mA

>15mil Width
1

C426
SC1U10V2KX-1GP DY

C425
SCD1U10V2KX-4GP

3D3V_S0

2 L26
1
0R0603-PAD

AVDDCK_3D3V

62 mA

1D2V_S0

C816
C817
SCD1U10V2KX-4GP
DY SC1U10V2KX-1GP

>15mil Width

L52 2
1
0R0603-PAD

<Core Design>

AVDDK_1D2V

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

R406

DY

C766

L28
2
PBY201209T-221Y-N-GP

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

5V_S0

3D3V_S5

E9

C417

DY

C769

AVDDK_1D2V

K17

PLL

AVDDC

J16

AVDDCK_3D3V

C421

USB I/O

1
2

DY

AVDDCK_1.2V

V5_VREF

SC1U10V2KX-1GP

C420

AVDDCK_3.3V

C422

DY

>10mil Width

AE7

SCD1U10V2KX-4GP

C415

SCD1U10V2KX-4GP

C416

SCD1U10V2KX-4GP

DY

SC1U10V2KX-1GP

C429

SC1U10V2KX-1GP

DY

SC10U6D3V3MX-GP

C428
SC10U6D3V3MX-GP

V5_VREF

2
A10
B10

C431

SC1U10V2KX-1GP

>50mil Width

2ND = 68.00216.161

1
1
2

3.3V_S5 I/O

2
C427

197 mA

SCD1U10V2KX-4GP

AVDD_USB

1
2
PBY201209T-221Y-N-GP

658 mA

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

>30mil Width

Use Plane Shape for +3.3V_AVDD_USB

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

C405

1D2V_S5

113 mA

SATA I/O

1
2

1
2

1
2

G2
G4

C419

DY

SCD1U10V2KX-4GP

S5_1.2V_1
S5_1.2V_2

DY

C414

SC1U10V2KX-1GP

1
2

A17
A24
B17
J4
J5
L1
L2

C404

SCD1U10V2KX-4GP

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

USB_PHY_1.2V_1
USB_PHY_1.2V_2

3D3V_S5
L27

C401

SC4D7U6D3V3KX-GP

DY

1D2V_S0

1 R148
2
0R0402-PAD

>20mil Width

SC1U10V2KX-1GP

AA14
AB18
AA15
AA17
AC18
AD17
AE17

C772
SCD1U10V2KX-4GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

SCD1U10V2KX-4GP

C366

SC1U10V2KX-1GP

C354

SCD1U16V2ZY-2GP

DY EC81

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

DY

SCD1U10V2KX-4GP

1
2
PBY201209T-221Y-N-GP
C770

C402

DY

SCD1U10V2KX-4GP

567 mA

L23

C786

32 mA

SC1U10V2KX-1GP

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

AVDD_SATA

= 68.00216.161 >50mil Width

DY

3D3V_S5

P18
P19
P20
P21
R22
R24
R25

1D2V_S0 2ND

CORE S0
CLKGEN I/O

IDE/FLSH I/O

POWER

CORE S5

1
2

1
2

1
2

C396

DY

SCD1U10V2KX-4GP

C395
SCD1U10V2KX-4GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

C389

DY

C400

DY

Part 5 of 5

C386

SC2D2U6D3V3KX-GP

C809

C403

DY

SC2D2U6D3V3KX-GP

C394

DY

SC2D2U6D3V3KX-GP

600 mA

>100mil Width

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

L21
L22
L24
L25

SC2D2U6D3V3KX-GP

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

PCIE_VDDR

220 ohm 2A

C814

CKVDD

A-LINK I/O

1
2

1
2

1
2

SCD1U10V2KX-4GP

Y20
AA21
AA22
AE25

1D2V_S0

2ND = 68.00216.161

DY

SB700

C815

>50mil Width
71 mA

L25
1
2
PBY201209T-221Y-N-GP

C805

SC10U6D3V3MX-GP

C773

C806

SCD1U10V2KX-4GP

C807
SCD1U10V2KX-4GP

DY

C799
SCD1U10V2KX-4GP

DY

C800
SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

C781

ASB1E

1D2V_S0

>100mil Width

L15
M12
M14
N13
P12
P14
R11
R15
T16

SCD1U10V2KX-4GP

C435

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

SC1U10V2KX-1GP

3D3V_S0

Part 3 of 5

PCI/GPIO I/O

3D3V_S0

510 mA

SB700
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

SC1U10V2KX-1GP

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

131 mA

GROUND

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_POWER&GND_(4/5)
Size

A3
Date:
5

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

14

of

61

REQUIRED STRAPS
REQUIRED SYSTEM STRAPS
D

DY

DY

R171

DY

R430

DY

R160

DY

R155

DY

R153

DY

R140

DY

R136

DY

3D3V_S5

R142

R145

3D3V_S0

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

2K2R2F-GP
PCI_CLK2
PCI_CLK3
CLK_PCI4
CLK_PCI_LOM
PCLK_FW H
PCLK_KBC
RTC_CLK
ACZ_RST#_R
SB_GPO17

RN52
SRN2K2J-1-GP

12

SB_GPO16

TPAD14-GP
TP137
TPAD14-GP
TP136
TPAD14-GP
TP195
TPAD14-GP
TP135
TPAD14-GP
TP134
TPAD14-GP
TP133
TPAD14-GP
TP130
TPAD14-GP
TP129

R166

DY 2K2R2F-GP
2

DEBUG STRAPS

4
3

10KR2J-3-GP

10KR2J-3-GP

RN50
SRN10KJ-5-GP

DY
10KR2J-3-GP

DY

10KR2J-3-GP

3
4

DY

4
3

RN46
SRN10KJ-5-GP

1
2

R429

R159

1
2

R139

2
1

R135

11
11
11
11
11,37
11,36
11,35
12
12

PCI_CLK2

PULL
HIGH

PCI_CLK3

WatchDOG
(NB_PWRGD)
ENABLED

CLK_PCI_LOM
CLK_PCI4

USE
DEBUG
STRAPS

PCLK_FWH
IMC
ENABLED

CLKGEN
ENABLED
(Use Internal)

RESERVED

PULL
LOW

PCLK_KBC

WatchDog
(NB_PWRGD)
DISABLED

IGNORE
DEBUG
STRAPS

IMC
DISABLED

DEFAULT

DEFAULT

DEFAULT

CLKGEN
DISABLED
(Use External)
DEFAULT

RTCCLK
INTERNAL
RTC

AZ_RST#
ENABLE PCI
ROM BOOT

DEFAULT

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

SB_GPO17 , SB_GPO16
ROM TYPE:

PULL
HIGH

H, H = Reserved
H, L = SPI ROM

DISABLE PCI
ROM BOOT

L, H = LPC ROM

DEFAULT

L, L = FWH ROM

DEFAULT

PULL
LOW

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30

11
11
11
11
11
11
11
11

PCI_AD28

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

USE
LONG
RESET
(DEFAULT)

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS Reserved

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

Reserved

USE
SHORT
RESET

PCI_AD23

PCI_AD30
PCI_AD29

Reserved

Note: SB700 has 15K internal PU FOR PCI_AD[30:23]

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_STRAPPING_(5/5)
Size

A3
Date:
5

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

15

of

61

ADIMM2

3D3V_S0

C458
SC2D2U6D3V3KX-GP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118

MH2

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
OTD0
OTD1

1D8V_S3

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH

MEM_MA_CLK0_P
C338
SC1D5P50V2CN-1GP
MEM_MA_CLK0_N
MEM_MA_CLK1_P
C331
SC1D5P50V2CN-1GP
MEM_MA_CLK1_N

DDR_VREF
1D8V_S3

VREF_DDR_MEM

C844
SCD1U10V2KX-4GP

RN100
1
2

4
3

SRN1KJ-7-GP
2

MH2

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

DY

(A0)

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

C456
SCD1U10V2KX-4GP

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

DY

C834

198
200

SMBD0_SB 3,12,17
SMBC0_SB 3,12,17

SA0
SA1

5
5
5
5
5
5
5
5

VDDSPD

199

MH1

1
2

195
197

MH1

114
119

SCD1U10V2KX-4GP

SDA
SCL

SCD1U10V2KX-4GP

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

201

13
31
51
70
131
148
169
188

MEM_MA_CLK1_P 5
MEM_MA_CLK1_N 5

10
26
52
67
130
147
170
185

GND

MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P

C847

164
166

GND

5
5
5
5
5
5
5
5

C845
SC2D2U6D3V3KX-GP

MEM_MA_CLK0_P 5
MEM_MA_CLK0_N 5

CK1
CK1#

VREF
VSS

11
29
49
68
129
146
167
186

30
32

202

MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N

VREF_DDR_MEM

MEM_MA_CKE0 5,18
MEM_MA_CKE1 5,18

CK0
CK0#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

5
5
5
5
5
5
5
5

5,18 MEM_MA0_ODT0
5,18 MEM_MA0_ODT1

CKE0
CKE1

MEM_MA0_CS#0 5,18
MEM_MA0_CS#1 5,18

79
80

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

110
115

CS0#
CS1#

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

MEM_MA_RAS# 5,18
MEM_MA_WE# 5,18
MEM_MA_CAS# 5,18

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

107
106

108
109
113

RAS#
WE#
CAS#

5,18 MEM_MA_BANK2
5,18 MEM_MA_BANK0
5,18 MEM_MA_BANK1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

NORMAL TYPE

5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18
5,18

C832
SC1KP50V2KX-1GP

LAYOUT: Locate close to DIMM

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SKT-SODIMM20020U4GP

62.10017.661
Title

2ND = 62.10017.A41

Place C2.2uF and 0.1uF <

500mils from DDR connector

LOW 5.2 mm

DDR_SO-DIMM SKT_1
Size
Document Number
Custom

Rev

SB

JV50-PU

Date: Friday, December 19, 2008

Sheet
1

16

of

61

ADIMM1

5
5
5
5
5
5
5
5

MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P

13
31
51
70
131
148
169
188
114
119

5,18 MEM_MB0_ODT0
5,18 MEM_MB0_ODT1

C855

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

C854

VREF_DDR_MEM

1
2

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

164
166

MEM_MB_CLK1_P 5
MEM_MB_CLK1_N 5

10
26
52
67
130
147
170
185

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

SDA
SCL

195
197

VDDSPD

199

SA0
SA1

198
200

5
5
5
5
5
5
5
5

SMBD0_SB 3,12,16
SMBC0_SB 3,12,16

DIMM2_SA1
1
R203

3D3V_S0

2
10KR2J-3-GP

C507 DY
SC2D2U6D3V3KX-GP

NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

OTD0
OTD1
VREF
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

50
69
83
120
163

1D8V_S3

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH
C

MEM_MB_CLK0_P

GND

GND

MH1

MH1

MH2

MH2

C348
SC1D5P50V2CN-1GP
MEM_MB_CLK0_N
MEM_MB_CLK1_P

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201

C499

DY SCD1U10V2KX-4GP

(A2)

81
82
87
88
95
96
103
104
111
112
117
118

202

11
29
49
68
129
146
167
186

MEM_MB_CLK0_P 5
MEM_MB_CLK0_N 5

CK1
CK1#

MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N

30
32

5
5
5
5
5
5
5
5

MEM_MB_CKE0 5,18
MEM_MB_CKE1 5,18

CK0
CK0#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CKE0
CKE1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MB0_CS#0 5,18
MEM_MB0_CS#1 5,18

79
80

5 MEM_MB_DATA0
5 MEM_MB_DATA1
5 MEM_MB_DATA2
5 MEM_MB_DATA3
5 MEM_MB_DATA4
5 MEM_MB_DATA5
5 MEM_MB_DATA6
5 MEM_MB_DATA7
5 MEM_MB_DATA8
5 MEM_MB_DATA9
5 MEM_MB_DATA10
5 MEM_MB_DATA11
5 MEM_MB_DATA12
5 MEM_MB_DATA13
5 MEM_MB_DATA14
5 MEM_MB_DATA15
5 MEM_MB_DATA16
5 MEM_MB_DATA17
5 MEM_MB_DATA18
5 MEM_MB_DATA19
5 MEM_MB_DATA20
5 MEM_MB_DATA21
5 MEM_MB_DATA22
5 MEM_MB_DATA23
5 MEM_MB_DATA24
5 MEM_MB_DATA25
5 MEM_MB_DATA26
5 MEM_MB_DATA27
5 MEM_MB_DATA28
5 MEM_MB_DATA29
5 MEM_MB_DATA30
5 MEM_MB_DATA31
5 MEM_MB_DATA32
5 MEM_MB_DATA33
5 MEM_MB_DATA34
5 MEM_MB_DATA35
5 MEM_MB_DATA36
5 MEM_MB_DATA37
5 MEM_MB_DATA38
5 MEM_MB_DATA39
5 MEM_MB_DATA40
5 MEM_MB_DATA41
5 MEM_MB_DATA42
5 MEM_MB_DATA43
5 MEM_MB_DATA44
5 MEM_MB_DATA45
5 MEM_MB_DATA46
5 MEM_MB_DATA47
5 MEM_MB_DATA48
5 MEM_MB_DATA49
5 MEM_MB_DATA50
5 MEM_MB_DATA51
5 MEM_MB_DATA52
5 MEM_MB_DATA53
5 MEM_MB_DATA54
5 MEM_MB_DATA55
5 MEM_MB_DATA56
5 MEM_MB_DATA57
5 MEM_MB_DATA58
5 MEM_MB_DATA59
5 MEM_MB_DATA60
5 MEM_MB_DATA61
5 MEM_MB_DATA62
5 MEM_MB_DATA63

110
115

CS0#
CS1#

107
106

MEM_MB_RAS# 5,18
MEM_MB_WE# 5,18
MEM_MB_CAS# 5,18

5,18 MEM_MB_BANK2
5,18 MEM_MB_BANK0
5,18 MEM_MB_BANK1

108
109
113

RAS#
WE#
CAS#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

REVERSE TYPE

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

5,18 MEM_MB_ADD0
5,18 MEM_MB_ADD1
5,18 MEM_MB_ADD2
5,18 MEM_MB_ADD3
5,18 MEM_MB_ADD4
5,18 MEM_MB_ADD5
5,18 MEM_MB_ADD6
5,18 MEM_MB_ADD7
5,18 MEM_MB_ADD8
5,18 MEM_MB_ADD9
5,18 MEM_MB_ADD10
5,18 MEM_MB_ADD11
5,18 MEM_MB_ADD12
5,18 MEM_MB_ADD13
5,18 MEM_MB_ADD14
5,18 MEM_MB_ADD15

C340
SC1D5P50V2CN-1GP
MEM_MB_CLK1_N

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DDR2-200P-22-GP-U3

62.10017.A61

Title

2ND = 62.10017.A51

Place C2.2uF and 0.1uF <

500mils from DDR connector

DDR_SO-DIMM SKT_2
Size
Document Number
Custom

HI 9.2mm

Date:
5

Rev

SB

JV50-PU

Friday, December 19, 2008

Sheet
1

17

of

61

Decoupling Capacitor

C516

1
2

1
2

1
2

C514

C513
SC10P50V2JN-4GP

C515

SC10P50V2JN-4GP

DY

SC1KP50V2KX-1GP

C496

SC1KP50V2KX-1GP

C497

SC1KP50V2KX-1GP

C498

SC1KP50V2KX-1GP

DY

SCD1U16V2ZY-2GP

C469
SCD1U16V2ZY-2GP

C468

RN55
MEM_MB_ADD4 5,17
MEM_MB_ADD11 5,17
MEM_MB_ADD5 5,17
MEM_MB_ADD8 5,17

1
2
3
4

SRN47J-4-GP
RN67
8
7
6
5

MEM_MA_ADD14 5,16
MEM_MA_ADD7 5,16
MEM_MA_ADD11 5,16
MEM_MA_ADD6 5,16

1
2
3
4

SRN47J-4-GP
RN56
8
7
6
5

MEM_MB_BANK0 5,17
MEM_MB_ADD10 5,17
MEM_MB_ADD1 5,17
MEM_MB_ADD3 5,17

1
2
3
4

SRN47J-4-GP
RN69
8
7
6
5

MEM_MA0_CS#0 5,16
MEM_MA_RAS# 5,16
MEM_MA0_ODT0 5,16
MEM_MA_ADD13 5,16

1
2
3
4

C484

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to 0D9V_S3

Place these Caps near DM2

1

C888

1
2

DY

1D8V_S3

Place these Caps near PARALLEL TERMINATION

0D9V_S3

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to 0D9V_S3

SC180P50V2JN-1GP

C483
SC180P50V2JN-1GP

C887
SCD01U50V2KX-1GP

C885
SCD01U50V2KX-1GP

C839
SC2D2U6D3V3KX-GP

C487
SC2D2U6D3V3KX-GP

MEM_MB0_CS#1 5,17
MEM_MB0_ODT1 5,17
MEM_MB_CAS# 5,17
MEM_MB_W E# 5,17

SC2D2U6D3V3KX-GP

SRN47J-4-GP
RN57
8
7
6
5

C481

C840

1D8V_S3

SC2D2U6D3V3KX-GP

1
2
1

C475

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

C489

DY

C488

DY

SCD1U16V2ZY-2GP

1
2
1

C479

SCD1U16V2ZY-2GP

2
1

C477
SCD1U16V2ZY-2GP

C443
SCD1U16V2ZY-2GP

DY

C491

SCD1U16V2ZY-2GP

C490

DY

SCD1U16V2ZY-2GP

C444
SCD1U16V2ZY-2GP

DY

C527

SCD1U16V2ZY-2GP

C442
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C526

SCD1U16V2ZY-2GP

C441

DY

SCD1U16V2ZY-2GP

C440

DY

C525
SCD1U16V2ZY-2GP

C478
SCD1U16V2ZY-2GP

DY

C524
SCD1U16V2ZY-2GP

Do not share the Term resistor between

the DDR addess and Control Signals.

C523
SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

SRN47J-4-GP

SRN47J-4-GP

2008/11/05

MEM_MB_CKE1 5,17
MEM_MB_ADD15 5,17
MEM_MB_ADD14 5,17
MEM_MB_ADD7 5,17

MEM_MA_BANK0 5,16
MEM_MA_ADD10 5,16
MEM_MA_ADD3 5,16
MEM_MA_ADD1 5,16

C884

1
2
3
4

SRN47J-4-GP
RN60
8
7
6
5

1
2
3
4

SRN47J-4-GP
RN62
8
7
6
5

C886

DY

MEM_MB_ADD9 5,17
MEM_MB_ADD12 5,17
MEM_MB_BANK2 5,17
MEM_MB_CKE0 5,17

SRN47J-4-GP
RN54
8
7
6
5

C841

1
2
3
4

MEM_MA_ADD12 5,16
MEM_MA_ADD9 5,16
MEM_MA_BANK2 5,16
MEM_MA_CKE0 5,16

C838

SRN47J-4-GP
RN61
8
7
6
5

C480

1
2
3
4

C482

MEM_MB_RAS# 5,17
MEM_MB0_CS#0 5,17
MEM_MB0_ODT0 5,17
MEM_MB_ADD13 5,17

SRN47J-4-GP
RN59
8
7
6
5

1
2
3
4

MEM_MA_ADD4 5,16
MEM_MA_ADD2 5,16
MEM_MA_BANK1 5,16
MEM_MA_ADD0 5,16

1D8V_S3

SCD1U16V2ZY-2GP

SRN47J-4-GP
RN68
8
7
6
5

Place these Caps near DM1

SCD1U16V2ZY-2GP

MEM_MB_ADD6 5,17
MEM_MB_ADD2 5,17
MEM_MB_ADD0 5,17
MEM_MB_BANK1 5,17

SCD1U16V2ZY-2GP

SRN47J-4-GP
RN58
8
7
6
5

SC2D2U6D3V3KX-GP

1
2
3
4

SC2D2U6D3V3KX-GP

MEM_MA_ADD8 5,16
MEM_MA_ADD5 5,16
MEM_MA_CKE1 5,16
MEM_MA_ADD15 5,16

2008/11/05

SC2D2U6D3V3KX-GP

1
2
3
4

8
7
6
5

SC2D2U6D3V3KX-GP

SRN47J-4-GP
RN66
8
7
6
5

1
2
3
4

MEM_MA0_ODT1 5,16
MEM_MA0_CS#1 5,16
MEM_MA_W E# 5,16
MEM_MA_CAS# 5,16

8
7
6
5

1
2
3
4

C470

SCD1U16V2ZY-2GP

1
2
3
4

C452

SCD1U16V2ZY-2GP

0D9V_S3
RN63

C451

SCD1U16V2ZY-2GP

Put decap near power(0.9V) and pull-up resistor

0D9V_S3

Put decap near power(0.9V) and pull-up resistor

SCD1U16V2ZY-2GP

PARALLEL TERMINATION

C450
SCD1U16V2ZY-2GP

0D9V_S3

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR_DAMPING & TERMINATION

Size
A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

18

of

61

LCD/INVERTER/CCD CONN

RN23
54
54
54
54

LVDS_TXACLKLVDS_TXACLK+
LVDS_TXAOUT2LVDS_TXAOUT2+

LVDS_TXACLKLVDS_TXACLK+
LVDS_TXAOUT2LVDS_TXAOUT2+

54
54
54
54

LVDS_TXAOUT0LVDS_TXAOUT0+
LVDS_TXAOUT1LVDS_TXAOUT1+

LVDS_TXAOUT0LVDS_TXAOUT0+
LVDS_TXAOUT1LVDS_TXAOUT1+

1
2
3
4

LCDVDD

RN22

LCD1

C1
SC10U10V5ZY-1GP

1
2
3
4

Inverter Pin

LCD_TXAOUT0LCD_TXAOUT0+
LCD_TXAOUT1LCD_TXAOUT1+

8
7
6
5

Pin

36 DBC_EN
3D3V_S0

LCD_EDID_CLK
LCD_EDID_DAT

BRIGHTNESS_CN
BLON_OUT_1

2008/11/13

DCBATOUT
F1

DCBATOUT_LCD1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

RN25
54
54
54
54

LCD_TXBCLK+
LCD_TXBCLKLCD_TXBOUT2+
LCD_TXBOUT2LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0LCD_TXACLK+
LCD_TXACLKLCD_TXAOUT2+
LCD_TXAOUT2LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

LVDS_TXBCLKLVDS_TXBCLK+
LVDS_TXBOUT2LVDS_TXBOUT2+

LVDS_TXBCLKLVDS_TXBCLK+
LVDS_TXBOUT2LVDS_TXBOUT2+

1
2
3
4

LCD_TXBCLKLCD_TXBCLK+
LCD_TXBOUT2LCD_TXBOUT2+

8
7
6
5

DIS SRN0J-7-GP

Vin

Brightness

BLON

GND

GND

RN24
54
54
54
54

LVDS_TXBOUT0LVDS_TXBOUT0+
LVDS_TXBOUT1LVDS_TXBOUT1+

LVDS_TXBOUT0LVDS_TXBOUT0+
LVDS_TXBOUT1LVDS_TXBOUT1+

1
2
3
4

LCD_TXBOUT0LCD_TXBOUT0+
LCD_TXBOUT1LCD_TXBOUT1+

8
7
6
5

CCD Pin
Pin

SRN0J-7-GP

DIS

2008/11/11
2008/10/29
RN17

C5

ACES-CONN40C-2-GP

SC10U35V0ZY-GP

69.50007.A31
2ND = 69.50007.A41

POLYSW -1D1A24V-GP

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
42

Vin

DIS SRN0J-7-GP
SB 2008/12/11

Symbol

36 LCD_CB_SEL

LCD_TXACLKLCD_TXACLK+
LCD_TXAOUT2LCD_TXAOUT2+

8
7
6
5

DIS SRN0J-7-GP

SB 2008/12/11
2008/11/04
41
40

20.F1230.040

9
9
9
9

2ND = 20.F1096.040

GMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXACLK+
GMCH_TXACLK-

GMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXACLK+
GMCH_TXACLK-

1
2
3
4

LCD_TXAOUT2+
LCD_TXAOUT2LCD_TXACLK+
LCD_TXACLK-

8
7
6
5

Symbol

CCD_PWR

USB-

USB+

GND

GND

UMA SRN0J-7-GP
C

RN16

CCD

USBPN8_R

USBPP8_R

9
9
9
9

DY

2 EC56
SC22P50V2JN-4GP
2 EC57
SC22P50V2JN-4GP
DY

GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT0+
GMCH_TXAOUT0-

GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT0+
GMCH_TXAOUT0-

1
2
3
4

UMA SRN0J-7-GP
RN19

2008/10/29
CCD1

9
9
9
9

GMCH_TXBOUT2+
GMCH_TXBOUT2GMCH_TXBCLK+
GMCH_TXBCLK-

GMCH_TXBOUT2+
GMCH_TXBOUT2GMCH_TXBCLK+
GMCH_TXBCLK-

9
9
9
9

GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT0+
GMCH_TXBOUT0-

GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT0+
GMCH_TXBOUT0-

1
2
3
4

6
1

CCD_PW R

LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

8
7
6
5

LCD_TXBOUT2+
LCD_TXBOUT2LCD_TXBCLK+
LCD_TXBCLK-

8
7
6
5

UMA SRN0J-7-GP
RN18

2
3
4
5
7

20.D0197.105

2ND = 20.F0984.005

UMA SRN0J-7-GP

3D3V_S0

1
2

LCD_EDID_CLK

74.05285.07F

C7
SC4D7U16V5ZY-GP

LCD_EDID_DAT
RN13

9
9

2
1

CLK_DDC_EDID
DAT_DDC_EDID

UMA

G5285T11U-GP

54 LCD_EDID_DAT

54 LCD_EDID_CLK

IN#4

IN#5

1
2

2
2

C2
SC4D7U16V5ZY-GP

DY

C6
SCD1U16V2ZY-2GP

DY
100KR2J-1-GP

R1

EN
GND
OUT

LCDVDD_ON

4
3

DY

U1

1
2
3

3D3V_S0

RN111
RN2
SRN4K7J-8-GP SRN4K7J-8-GP

2008/11/19

2
0R2J-2-GP

Layout 40 mil
54

3D3V_M92

1
2

1
R2

R3
10KR2J-3-GP

LCDVDD

UMA
9 GMCH_LCDVDD_ON

C3

DY

SC100P50V2JN-3GP

3D3V_S0

BRIGHTNESS 36
BLON_OUT 36

SRN33J-5-GP-U

4
3

C4

DY

4
3
1

1
2

RN1
BRIGHTNESS_CN
BLON_OUT_1

C554
SCD1U16V2ZY-2GP

SC100P50V2JN-3GP

2008/11/07

DY

2ND = 69.50007.771

C555
SC4D7U10V5ZY-3GP

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP1
TP2
TP3

69.50007.691
CCD_PW R

1
1
1

LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0-

8
7
6
5

FUSE-1D1A6V-4GP-U

2008/11/10
CCD_PW R
USBPN8_R
USBPP8_R

1
2
3
4

F2

1
ACES-CON5-1GP-U

USBPN8
USBPP8

USBPN8_R
2
0R2J-2-GP
USBPP8_R
2
0R2J-2-GP

12
12

R253 1
R254 1

C856

3
4
SRN0J-10-GP-U

C701

2008/12/17

SC220P50V2KX-3GP

SC220P50V2KX-3GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

LCD CONN

Document Number

Rev

SB

JV50-PU

Friday, December 19, 2008

Sheet
1

19

of

61

RN21
9
9
9

8
7
6
5

GMCH_BLUE
GMCH_GREEN
GMCH_RED

UMA
1
2
3
4

SRN10J-5-GP

2008/12/8

Ferrite bead impedance: 10 ohm@100MHz

L18

CRT_R

1
2

C700
SCD1U16V2ZY-2GP

54,57 CRT_HSYNC
54,57 CRT_VSYNC

For System CRT

2008/12/8

U46A

14
HSYNC_1

3
4
SRN0J-10-GP-U

UMA
9
9

DY

2
1

VSYNC_1

2008/12/17
EC31

RN34

U46B

CRT_HSYNC1_1

RN36
CRT_HSYNC1
4 SRN22-3-GP
CRT_VSYNC1
3

1
2

TSAHCT125PW -GP

DIS

C176

C203

14

C215

73.74125.L13
CRT_VSYNC1_1

RN31

2
1

GMCH_VSYNC
GMCH_HSYNC

3
4
SRN0J-10-GP-U

1
2

2
2

1
1

1
2

CRT_B

2
FCB1608CF-GP

SC6D8P50V2DN-GP

2008/12/10

DY

2008/12/8
SC6D8P50V2DN-GP

150R2F-1-GP

DY

RN37
SRN2K2J-1-GP

SC6D8P50V2DN-GP

SRN0J-7-GP

DY

EC27
SC3P50V2CN-1-GP

DY

R489
R488 R490
150R2F-1-GP
150R2F-1-GP

EC30

SC3P50V2CN-1-GP

1
2
3
4

SC3P50V2CN-1-GP

8
7
6
5

54
CRT_RED
54 CRT_GREEN
54
CRT_BLUE

2ND = 68.00119.081
68.00230.021

EC32

4
3

CRT_G

CRT_B_1

DIS

2008/12/8

2
FCB1608CF-GP
L15

RN114

1
2

2ND = 68.00119.081
68.00230.021

Hsync & Vsync level shift

5V_S0

FCB1608CF-GP
L16
CRT_G_1

3D3V_S0

2008/12/8
2

2ND = 68.00119.081
68.00230.021

CRT_R_1

TSAHCT125PW -GP

73.74125.L13

2008/11/11
CRT_R 1

Layout Note:
Place these resistors
close to the CRT-out
connector

2
C

MLVG04023R0QV05-GP
DY
EC29

CRT_G 1

MLVG04023R0QV05-GP
EC28

CRT_B 1

DY

DDC_CLK & DATA level shift

5V_CRT_S0

2
MLVG04023R0QV05-GP

Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

F3
5V_S0
FUSE-1D1A6V-4GP-U

3D3V_S0

2ND = 69.50007.771
69.50007.691 D25

3D3V_M92

CRT I/F & CONNECTOR

2008/11/11
5V_CRT_DDC

CRT_G

7
12
8
13
9
14
10
15

3
4

CRT_IN#_R

DAT_DDC1_5

5V_CRT_S0

DIS

CRT_HSYNC1
CRT_VSYNC1

9 GMCH_DDCCLK
9 GMCH_DDCDATA

SA

4
3

DAT_DDC1

RN20

2
1

2R49

1DAT_DDC1_5
0R2J-2-GP

2R50

1CLK_DDC1_5
0R2J-2-GP

1
2N7002EDW -GP

3 CLK_DDC1_5_Q
4
SRN0J-10-GP-U

84.27002.F3F
CLK_DDC1

20.20378.015

2008/11/11

2ND = 20.20378.015

R64
CRT_DEC#

<Core Design>

1CRT_IN#_R

470R2J-2-GP
C129
SC100P50V2JN-3GP

EC24

36

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY
2

1
2

DY

SC100P50V2JN-3GP

VIDEO-15-42-GP-U
C161

5
6

UMA

17

CLK_DDC1_5
DAT_DDC1_5
C142
C148
DY SC100P50V2JN-3GP

C722

CRT_HSYNC1

SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

C150

U69
DAT_DDC1_5_Q

3
4
SRN0J-10-GP-U

CLK_DDC1_5
SCD01U16V2KX-3GP

CRT_VSYNC1

CRT_IN#_R

RN33

2
1

54 CRT_DDCDATA
54 CRT_DDCCLK

2008/11/27

1
2

6
11

1
2

Title

MLVG04023R0QV05-GP
Size

CRT Connector

Document Number

Rev

SB

JV50-PU
Date:
5

1
2
3
4

16

3RD = 83.5R003.08F
RN35
SRN10KJ-6-GP

RN112
RN26
SRN2K2J-1-GPSRN2K2J-1-GP

CRT_R

CRT_B

4
3

DY

CRT1

83.R5003.C8F
500mA
2nd = 83.R5003.H8H

8
7
6
5

2008/12/15

CH551H-30PT-GP

3D3V_S0

Friday, December 19, 2008

Sheet
1

20

of

61

5V_S0
5V_S0

SKT-HDMI19P-11GP-U1

62.10078.171

SRN1K5J-GP

DY

EC66

EC64

DY

DY

66.15236.04L
D

EC65

3D3V_M92

2008/12/18
2008/11/19

2008/04/03 SB

2ND = 62.10078.121
3RD = 62.10027.991

3D3V_S0

4
3

MLVG04023R0QV05-GP

TMDS_CLOCK_SHIELD
TMDS_CLOCK+
TMDS_CLOCK-

2
1

4
3

20
21
22
23

TMDS_DATA0_SHIELD
TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD

HDMI_A_HPD_CN

GND
GND
GND
GND

8
5
2

3
4

TP14 TPAD14-GP

RESERVED#14

14

HDMI_A_CEC

13
17
19

TMDS_DATA0+
TMDS_DATA0TMDS_DATA1+
TMDS_DATA1TMDS_DATA2+
TMDS_DATA2-

TDMS_A_CLK
TDMS_A_DAT

SC220P50V2JN-3GP

CEC
DDC/CEC_GROUNG
HOT_PLUG_DETECT

7
9
4
6
1
3

11
10
12

HDMI_TXC+
HDMI_TXC-

15
16

SCL
SDA

+5V_POWER

SC220P50V2JN-3GP

HDMI_TX0+
HDMI_TX0HDMI_TX1+
HDMI_TX1HDMI_TX2+
HDMI_TX2-

RN6

18

2008/12/11 SB

HDMI1

RN113
SRN1K5J-GP

RN79
SRN1K5J-GP

UMA RN32
2
1

9 GMCH_HDMI_CLK
9 GMCH_HDMI_DATA
3D3V_S0

R281 4K7R2J-2-GP
2
R282 2
4K7R2J-2-GP

2
1

2
1

2
1

2008/11/13

TMDS_A_TX0TMDS_A_TX0+
TMDS_A_TX1TMDS_A_TX1+
TMDS_A_TX2TMDS_A_TX2+

1
1

DY DY

HDMI_DATA0HDMI_DATA0+

8
8

HDMI_DATA1HDMI_DATA1+

8
8

HDMI_DATA2HDMI_DATA2+

UMA
UMA

3
4 RN27
SRN0J-10-GP-U
3
4 RN28
SRN0J-10-GP-U
3
4 RN29
SRN0J-10-GP-U
3
4 RN30
SRN0J-10-GP-U

2
1
2
1
2
1

Recommended Equalization: [PC1,PC0]=01, 4dB

R301 2
4K7R2J-2-GP
PC0
1
3D3V_S0
R302 2
4K7R2J-2-GP
PC1
1

From NB

IN_D1IN_D1+

OUT_D1OUT_D1+

23
22

HDMI_TXCHDMI_TXC+

41
42

IN_D2IN_D2+

OUT_D2OUT_D2+

20
19

HDMI_TX0HDMI_TX0+

44
45

IN_D3IN_D3+

OUT_D3OUT_D3+

17
16

HDMI_TX1HDMI_TX1+

47
48

IN_D4IN_D4+

OUT_D4OUT_D4+

14
13

HDMI_TX2HDMI_TX2+

3
4

DY
REXT_HDMI
RT_EN#_8101
OE#_8101
DDC_EN_PS8101

R283

3D3V_S0
3D3V_S0

6
10
25
32

PC0
PC1

SDA
SCL
HPD

REXT
RT_EN#
OE#
DDC_EN

PS8101-GP

R303
499R2F-2-GP

OE#_8101

71.P8101.003

TDMS_A_CLK
TDMS_A_DAT

RN7

DY

3 HDMI_TXC4 HDMI_TXC+
SRN0J-10-GP-U

2
1

DY

5V_S0

2
5

1A
2A

1OE
2OE

1
7

VCC

3
6

1B
2B

GND

TSCBTD3305CPW R-GP

DDC_OE

DY

73.03305.A0B
2ND = 73.53305.A0B

Q19
2N7002-7F-GP

2008/11/14

2008/11/07
<Core Design>

UMA

HDMI_DETECT#
1
2
R305 1KR2J-1-GP
1
2
HDMI_A_HPD

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DIS

84.27002.N31
2ND = 84.27002.Y31

HPD

HDMI_DETECT#

2008/11/07

R304
200KR2F-L-GP

54

Title
R306
200KR2F-L-GP
Size
Date:

HDMI Connector

Document Number

Rev

SB

JV50-PU

DY

3 HDMI_TX24 HDMI_TX2+
SRN0J-10-GP-U

2
1

U72
HDMI_A_CLK
HDMI_A_DAT

RT_EN#_8101

HDMI_A_HPD_CN

DY

HDMI_A_HPD_CN
TDMS_A_DAT
TDMS_A_CLK

DY

R288
20KR2F-L-GP

RN12

HDMI_A_DAT
HDMI_A_CLK
HPD

4K7R2J-2-GP

30
29
28

3 HDMI_TX14 HDMI_TX1+
SRN0J-10-GP-U

2
1

R492
2K2R2F-GP

4K7R2J-2-GP
R295

HPD_SINK
SDA_SINK
SCL_SINK

8
9
7

RN9

DY

3D3V_S0

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

3D3V_S0

35
34

38
39

1
5
12
18
24
27
31
36
37
43
49

8
8

UMA

2
1

3 HDMI_TX04 HDMI_TX0+
SRN0J-10-GP-U

2
1

2008/11/13

UMA
HDMI_CLKHDMI_CLK+

TMDS_A_TXCTMDS_A_TXC+

RN8

DY

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U35

NC#35
NC#34

2
11
15
21
26
33
40
46

From VGA

8
8

HDMI_A_CLK 54
HDMI_A_DAT 54

SCD1U10V2KX-4GP

54 TMDS_A_TX254 TMDS_A_TX2+

C638

SCD1U10V2KX-4GP

54 TMDS_A_TX154 TMDS_A_TX1+

C28

SCD1U10V2KX-4GP

2
1

54 TMDS_A_TX054 TMDS_A_TX0+

C34

SCD1U10V2KX-4GP

C32

66.15236.04L

HDMI_A_CLK
3
HDMI_A_DAT
4
SRN0J-6-GP

3D3V_S0

54 TMDS_A_TXC54 TMDS_A_TXC+

66.15236.04L

1
2

1
2

DIS

Friday, December 19, 2008

Sheet

21
1

of

61

SATA Connector
SATA1

23
NP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SATA_RXP0 13
SATA_RXN0 13

D23
SS24-GP

SCD1U16V2ZY-2GP

16
17
18
19
20
21
22
NP2
24

C685

DY

SC10U10V5ZY-1GP

MP

1
TC22

5V_S0

83.2R004.08G

2ND = 83.2R004.J8M
3RD = 83.2R004.H8M

SATA_TXN0 13
SATA_TXP0 13

SKT-SATA22P-27-GP

62.10065.471
2ND = 62.10065.551
3RD = 62.10065.661

SATA_TXP0

D22
BAV99PT-GP-U

SATA_TXN0

DY

DY

DY

D21
BAV99PT-GP-U

3D3V_S0

83.00099.K11
2ND = 83.00099.M11

D19
BAV99PT-GP-U

D24
BAV99PT-GP-U

DY

MP
B

SATA_RXP0

SATA_RXN0

2008/12/17

3D3V_S0
3D3V_S0

83.00099.K11
83.00099.K11
2ND = 83.00099.M112ND = 83.00099.M11

3D3V_S0

83.00099.K11
2ND = 83.00099.M11

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5

HDD

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

22

of

61

SATA ODD Connector

2008/11/12

ODD1

13 SATA_RXP1
13 SATA_RXN1

S6
S5

B+
B-

13 SATA_TXP1
13 SATA_TXN1

S2
S3

A+
A-

P3
P2

+5V
+5V

9
8
P6
P5
S7
S4
S1

DP
MD

P1
P4

ODD_DP
ODD_MD

TP152 TPAD14-GP

SSM24PT-GP

83.2R004.H8M

SKT-SATA7P+6P-39-GP-U
TC9
SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

C430

D4

SB

62.10065.541

R165
10KR2J-3-GP

DY
2

2008/11/14 DY

5V_S0

GND
GND
GND
GND
GND
GND
GND

2nd: 62.10065.481
3nd: 62.10065.441

BOM change to 62.10065.751

D8
BAV99PT-GP-U

D7
BAV99PT-GP-U

1
3D3V_S0

83.00099.K11
2ND = 83.00099.M11

DY

D6
BAV99PT-GP-U

DY

D5
DY
BAV99PT-GP-U

DY

SATA_TXP1

SATA_TXN1

MP

SATA_RXN1

SATA_RXP1

2008/12/17

3D3V_S0
3D3V_S0

83.00099.K11
83.00099.K11
2ND = 83.00099.M112ND = 83.00099.M11

3D3V_S0
B

83.00099.K11
2ND = 83.00099.M11

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5

ODD

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

23

of

61

BLUETOOTH MODULE
D

1.5A / High Active Voltage 2V

3D3V_S0
3D3V_BT_S0
U68

1
2
3

EC98 DY
SCD1U16V2ZY-2GP

C920
SC4D7U10V5ZY-3GP

OUT
GND
NC#3

IN

EN

DY 2
BLUETOOTH_EN 36

G5240B1T1U-GP

3D3V_BT_S0

74.05240.A7F

2ND = 74.09711.A7F

EC21 put near

BLUE1 / all
USB put one
choke near
connector by
EMI request

R527
0R0402-PAD
2
1

BT1
ACES-CON4-1-GP-U2

4
3
2

USB_5USB_5+

3D3V_BT_S0

USBPN5
USBPP5

12
12

20.D0197.104
5

2ND = 20.F0984.004
2

USB_51
USB_5+ 1
3D3V_BT_S0 1

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP235
TP236
TP237

R528
0R0402-PAD

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BLUETOOTH
Size

Document Number

Rev

JV50-PU
Date:
5

Friday, December 19, 2008

SB
Sheet
1

24

of

61

5V_USB1_S0

USB1

2008/11/06

USB1

5V_USB1_S0
5V_S5

22.10218.T51
2ND = 22.10321.111
3RD = 22.10218.W51

5V_USB1_S0

USB2
USB3

12
12

EC84
SCD1U16V2ZY-2GP

DY

DY

79.22710.6AL
2ND = 77.92271.021
3RD = 79.22710.E0L

79.22710.6AL
2ND = 77.92271.021
3RD = 79.22710.E0L

TC24

EC79

DY
2

12

DY

USB_OC#0

TC29

8
7
6
5

EC83
D

2008/11/06

6
1

R156
0R0402-PAD
2
1
2
1

USBPN2
USBPP2

VOUT
VOUT
VOUT
FLG#

2008/11/03
74.09715.079
2ND = 74.00547.A79
3RD = 74.02065.079

C836
SC4D7U10V3KX-GP

GND
VIN
VIN
EN#

RT9715DGF-GP

1
2
3
4

SC1000P50V3JN-GP

USB_PW R_EN#

SCD1U16V2ZY-2GP

SKT-1394-4P-27-GP-U

100 mil
SE220U6D3VM-7GP

R134
0R0402-PAD

5V_USB1_S0
U54

SE220U6D3VM-7GP

2
3
4
5

USB_0USB_0+

USBPN0
USBPP0

12
12

6
1

R133
0R0402-PAD
2
1
2
1

USB_2USB_2+

2
3
4
5

R157
0R0402-PAD

SKT-1394-4P-27-GP-U

22.10218.T51
2ND = 22.10321.111
3RD = 22.10218.W51
5V_USB1_S0
U14
C

USBPN0

USBPP0

DY AOZ8001J-GP-U1
83.08000.AAE

2008/11/04

2008/11/13
USB_OC#4

TP173 AFTE14P-GP

USBPN1

TP174 AFTE14P-GP

USBPP1

TP176 AFTE14P-GP

USBPN3

TP175 AFTE14P-GP

USBPP3

TP177 AFTE14P-GP

USB_PW R_EN#

TP178 AFTE14P-GP

5V_S5

12

17

USBPN1
USBPP1

12
12

USBPN3
USBPP3

36 USB_PW R_EN#

U17

USBPN2

USBPP2

DY AOZ8001J-GP-U1
83.08000.AAE
B

2nd = 83.5V0U2.0A3
1.U75 as close to the USB2 as possible

C837

DY

SC1U16V3ZY-GP

SCD1U16V2ZY-2GP

5V_S5
EC85

5V_USB1_S0

15
14
13
12
11
10
9
8
7
6
5
4
3
2

USB_OC#4
12
12

TP179 AFTE14P-GP

2nd = 83.5V0U2.0A3

USBCN1

2008/11/07

2008/11/10

2.U76 as close to the USB1 as possible

16

ACES-CON15-8-GP-U

20.F1290.015
2ND = 20.F1035.015
3RD = 21.D0214.115

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

USB
Size

Document Number

Rev

JV50-PU
Date:
5

Friday, December 19, 2008

SB
Sheet

25
1

of

61

GPHY_PLLVDDL

48
42

2
1

FCM1608K-601T03GP

3D3V_LAN_S5

R20
AT45DB011D-SH-T-GP

72.45011.B01

1
FCM1608K-601T03GP

LAN_AVDD
LAN_AVDD

R27

PCIE_PLLVDDL
PCIE_PLLVDDL

2
C

49
50

TRD2_N
TRD2_P

47
46

MDI2MDI2+

27
27

TRD1_N
TRD1_P

43
44

MDI1MDI1+

27
27

TRD0_N
TRD0_P

41
40

LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#

2
1
67
66

MDI3MDI3+

27
27

MDI0MDI0+

Place PLLVDD/AVDDL
CKT as close to chip as
possible

C48

3D3V_AUX_S5
27
27

30
27

TRD3_N
TRD3_P

SCD1U10V2KX-4GP

2LAN_AVDD

68.00217.241
2ND = 68.00121.071

C56
SCD1U10V2KX-4GP
PCIE_PLLVDD

C44
SCD1U10V2KX-4GP

68.00217.241
2ND = 68.00121.071

3D3V_LAN_S0

GPHY_PLLVDD

2BIASVDD_G

FCM1608K-601T03GP C67

3D3V_S0

1 R26
2
0R0603-PAD

C100

SCD1U10V2KX-4GP
68.00217.241
2ND = 68.00121.071

SO
GND
VCC
WP#

C33
SCD1U10V2KX-4GP

C35

DY

XTALVDD_G

SI
SCK
RESET#
CS#

SI

8
7
6
5

35

BIASVDD_G

2XTALVDD_G

1
1
2
3
4

AVDDL
AVDDL
AVDDL

23

R44

U3

SO
SCLK
AT45_RESET#
CS#

SCD1U10V2KX-4GP

39
45
51

36

38
52
68
DC#38
DC#52
DC#68

XTALVDDH

AVDDH
AVDDH
AVDDL_G
AVDDL_G
AVDDL_G

R13
10KR2J-3-GP

2008/10/28

BIASVDDH
VDDC_IO
VDDC_IO
VDDC
VDDC
VDDC
VDDC

3D3V_LAN_S5

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

5
55
13
20
34
60

C114

C54

6
56
61
15
19
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

2D5V_1D2V_LAN

CO-Layout BCM5764 and BCM5784

modify BOM :71.05784.003

1D2V_LAN_S5

U4

3D3V_LAN_S5

SCD1U10V2KX-4GP

1 R46
2
0R0603-PAD

C93
SCD1U10V2KX-4GP

C64
SCD1U10V2KX-4GP

C107

C103
SCD1U10V2KX-4GP

SC4D7U6D3V3MX-2GP

C110

3D3V_LAN_S5

3D3V_S5

LAN_AVDD

1D2V_LAN_S5

R35

33
24

PCIE_VDDL
PCIE_VDDL

2
1D2V_LAN_S5
R18

2 AVDDL_G

FCM1608K-601T03GP

68.00217.241C50
SC4D7U6D3V3MX-2GP

SCLK
SI
SO
CS#

C43

DY 10KR2J-3-GP

1
2

1
2

R40

C115

2ND = 68.00121.071

65
63
64
62

TP61 TPAD14-GP
TP60 TPAD14-GP
TP183TPAD14-GP

C108 C72

SCLK/EECLK
SI
SO/EEDATA
CS#

UART_MODE
GPIO1
GPIO0

9
7
4

UART_MODE
GPIO_1/SERIAL_DI
GPIO_0/SERIAL_DO

C113

2
1

LAN_RST

CLK_PCIE_LAN
CLK_PCIE_LAN#

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
PERST#
PCIE_REFCLK_P
PCIE_REFCLK_N

C98

R23

2GPHY_PLLVDD

FCM1608K-601T03GP

2
1
C81

1 R28
2PCIE_SDSVDD
0R0603-PAD

2008/11/13

REGCTL12

14

Q5
REGCTL12
BCP69-GP

84.00069.B1B1
2ND = 84.DCP69.01B
3RD = 84.00069.A1B

C51
SC4D7U6D3V3MX-2GP
C84
SCD1U10V2KX-4GP

1D2V_LAN_S5

BCM5764MKMLG-GP
SRN1KJ-10-GP-U

71.05764.M01

SUPER_IDDQ

16
2

GND

VMAINPRSNT
VAUX_PRESENT
LAN_CLKREQ#

69

8
7
6
5

2ND = 71.05784.003

C58
SC10U10V5ZY-1GP

RN15

1
2
3
4

CLKREQ#
1

3D3V_LAN_S5

11

LAN_CLKREQ#

3D3V_LAN_S0

Wistron Corporation
C73
SCD1U10V2KX-4GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

BCM5764MKMLG
Size
A3
Date:

R42
1D5R3F-GP

1K24R2F-GP

C109

2008/11/13

C75
SC4D7U6D3V3MX-2GP

RDAC

1 R32
2PCIE_PLLVDD
0R0603-PAD

37

3D3V_LAN_S5

2RDAC

18

1 R22

REGOUT12_IO

SC4D7U6D3V3MX-2GP

82.30020.A31
2ND = 82.30020.851

1
XTALO
XTALI

17

XTAL-25MHZ-120-GP-U C105
SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

22
21

VDDC_IO

SMB_CLK
SMB_DATA

LAN_XI

C92

LAN_XO_R

58
57

X1

2D5V_1D2V_LAN

C116
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12,33,34 SMB_CLK
12,33,34 SMB_DATA

1
0R2J-2-GP
R39 1
2 LAN_SMB_CLK
R34 1 0R2J-2-GP
2 LAN_SMB_DATA
0R2J-2-GP
2
1LAN_X0
R45
200R2J-L1-GP

C112

2 R47
DY

VAUX_PRSNT
VMAIN_PRSNT
LOW_PWR

C45

2ND = 68.00121.071

SCD1U10V2KX-4GP

VAUX_PRESENT54
VMAINPRSNT
53
LOW _PW R
3

LOW _PW R

R340
4K7R2J-2-GP
SCD1U10V2KX-4GP

36

C38
68.00217.241
SC4D7U6D3V3MX-2GP

59

ENERGY_DET

36

ENERGY_DET

2D5V_1D2V_LAN

SCD1U10V2KX-4GP

DY

C117
SC47P50V2JN-3GP

3
3

26
25
31
32
12
10
29
28

TP59 TPAD14-GP

SCD1U10V2KX-4GP

2
0R2J-2-GP

12,34 PCIE_W AKE#

PCIE_RXDP
PCIE_RXDN

GPIO2

SCD1U10V2KX-4GP

R48
1

2 C87
2 C96

SC4D7U6D3V3MX-2GP

9,11,33,36 PLT_RST1#

SCD1U16V2KX-3GP 1
SCD1U16V2KX-3GP 1

GPIO_2

SCD1U10V2KX-4GP

PCIE_RXP1
PCIE_RXN1
PCIE_TXP1
PCIE_TXN1

ENERGY_DET

SCD1U10V2KX-4GP

8
8
8
8

10M/100M/1G_LED# 27
LAN_ACT_LED# 27

C69
SCD1U10V2KX-4GP

DY 10KR2J-3-GP
2

PCIE_SDSVDD

3D3V_LAN_S5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

26

of

61

LAN Connector

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

LAN_ACT_LED#
10M/100M/1G_LED#

DY

DY

C11
C558
SC1KP50V2KX-1GP SC1KP50V2KX-1GP

GIGA Lan Transformer

2D5V_1D2V_LAN

XRF_TDC

2
2008/11/130R2J-2-GP
1
2

1
2

SCD1U16V2ZY-2GP

C39

C31

SCD1U16V2ZY-2GP

2008/12/17

12

26

MDI1+

10

26

MDI1-

11

26

MDI0+

DY

1 R15

A2(+) A1(-)::GREEN

2008/11/11

XF1

26

MDI0-

A2(+) A3(-):ORANGE

RJ45_3
MCT2
RJ45_6
RJ45_1

LAN Connector

MCT1
RJ45_2

2008/11/05
RJ45

XFORM-271-GP

26 10M/100M/1G_LED#

XF2
26

MDI3+

26

MDI3-

26

MDI2+

12

10

11

RJ45_1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
CONN_PW R2

2
3
4
5
6
7
8
B1

CONN_PW R

68.HD081.301
2ND = 68.68161.30A

9
A1
A2
A3
1

RJ45_7
MCT4
RJ45_8

RJ45_4
MCT3

B2
10

26 LAN_ACT_LED#

1
2

C14

26

SCD1U16V2ZY-2GP

C16

SCD1U16V2ZY-2GP

2008/11/17
MDI2-

RJ45_5

RJ45-125-GP-U1

22.10277.021

2ND = 22.10277.231
XFORM-271-GP

B1(+) B2(-):YELLOW
68.HD081.301
2ND = 68.68161.30A

DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
10/20 @ Inner layers
2

RN5

EC11

8
7
6
5

DY

1
2
3
4

RN77
SRN75J-1-GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

MCT1
MCT2
MCT3
MCT4

EC60

DY

SRN470J-3-GP

CONN_PW R2
CONN_PW R

8
7
6
5

1
2
3
4

3D3V_LAN_S5

MCT_R

C570
SC1KP2KV8KX-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN CONN
Size
A3
Date:
A

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
E

27

of

61

3D3V_S0
C898
SC10U10V5ZY-1GP
D

5VA_S0

1
2

AUDIO_BEEP

4
3

AUDIP_PC_BEEP

C900

C897

2
2

C896
SC100P50V2JN-3GP

RESET#

R516 1

BCLK

R514 1

C905
C906
C902
C904

MIC1-L_PORT-B
MIC1-R_PORT-B
IMT_MIC1-L
IMT_MIC1-R
MIC1V_R
MIC1V_L

RN109

8
7
6
5

32
28
30

MIC1_VREFO_R
MIC1_VREFO_L
MIC2_VREFO

C915

34
13

LINEOUT_JD#

30
C

ALC268_SENSE

SC22P50V2JN-4GP

1
2
10KR2F-2-GP

LINEIN_JD#

R518
1
2
20KR2F-L-GP

MIC_JD#

30

30

Sense resistors need close codec

SDATA_OUT
SDATA_IN
SPDIFO1
SPDIFI/EAPD

48
47

SIDESURR_L
SIDESURR_R

45
46

SURR_L
SURR_R

39
41

FRONTL 29
FRONTR 29

FRONT_L
FRONT_R

35
36

SOUNDL 29
SOUNDR 29

AC97_DATIN 1
R517
AUD_SPDIF_OUT
ALC_EAPD

2
39R2J-L-GP

ACZ_SDATAOUT 12
ACZ_SDATAIN0 12

AUD_SPDIF_OUT
ALC_EAPD 29

30

ALC888S-VC2-GR-GP

71.00888.D0G

DMIC_CLK
MXM_SPDIF
MONO-OUT
1

2
39K2R2F-L-GP
R519

C899
1
2DY

SENSE_B
SENSE_A

LFE
CENTER

ALC888S

DMIC_DAT
VREF

1
1

TP225 TPAD14-GP
TP223 TPAD14-GP

TP234 TPAD14-GP

C917
SCD47U16V3ZY-3GP

R521
20KR2F-L-GP

C919
SC10U10V5ZY-1GP

DY

TP224

MIC1_L
MIC1_R
MIC2_L
MIC2_R

SC4D7U10V5ZY-3GP

C916
SC4D7U10V5ZY-3GP

TPAD14-GP

C914
SC4D7U10V5ZY-3GP

SRN2K2J-2-GP

2008/11/11

MIC2-VREFO

1
2
3
4

21
22
16
17

R520

CD_L
CD_R
CD_GND

1
1
2
2

LINE1_VREFO
LINE2_VREFO

ACZ_RST# 12,31
ACZ_SYNC 12,31
ACZ_BITCLK 12

5
8

18
20
19

RN103

2
2
1
1

29
31

GPIO0/DMIC_CLK/SPDIFO2
GPIO1/DMIC_DATA

INT_MIC
AUD_MICIN_L
AUD_MICIN_R

30

5
6
SC4D7U10V3KX-GP
7MIC1-L_PORT-B_1
SC4D7U10V3KX-GP
8 MIC1-R_PORT-B_1
INT_MIC_2
SC1U16V3ZY-GP
SC1U16V3ZY-GP

30
30

4
3
2
1

LINE1_L
LINE1_R
LINE2_L
LINE2_R

VREF

2208/12/18
2208/12/16
SRN75J-1-GP

23
24
14
15

27

ALC861_LINE_IN_L
ALC861_LINE_IN_R

JDREF

1 C907
1 C911

SC4D7U10V3KX-GP 2
SC4D7U10V3KX-GP 2

AVSS1
AVSS2
DVSS
DVSS

LINE_IN_L
LINE_IN_R

26
42
4
7

30
30

BEEP
RESET#
SYNC
BCLK
AGPIO

DVDD
DVDD_IO
AVDD1
AVDD2

U64

44
43

SPKR_SB_1
2
C894

2
3

1
SCD47U16V3ZY-3GP

JDREF
PIN37_VREFO

ACZ_SPKR

2
0R2J-2-GP
2
0R2J-2-GP
1
2
C895
DY
SC22P50V2JN-4GP

2
C893

12
11
10
6
33

12

1
SCD47U16V3ZY-3GP

40
37

KBC_BEEP

1
9
25
38

36

SC33P50V2JN-3GP

SCD1U10V2KX-4GP

R515
1K91R2F-1-GP

2208/12/09

SC1U10V3KX-3GP
SRN47K-2-GP-U

C912
SCD1U10V2KX-4GP

C901
1

RN108
KBC_BEEP_1

C909
SC10U10V5ZY-1GP

3D3V_S0

"VAUX" Pull high to enable standby mode

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Azalia codec ALC888

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

28

of

61

SB 2008/11/15
+5V_SPK_AMP

Close to U53.8

Close to U53.18

1
2

1
2

C929
SC1U6D3V2KX-GP

C928
SC10U6D3V5MX-3GP

1
2

C927
SCD1U10V2KX-4GP

C926
SC1U6D3V2KX-GP

C925
SC1U6D3V2KX-GP

C930
SC1U6D3V2KX-GP

Close to Pin9

AUD_LIN_R 2
AUD_LIN_L 2

R533
6K2R2F-GP
1
1

AMP_REGEN
AMP_C1P
C933 1
AMP_C1N

R535 2
R537 2
R536 2

1 0R2J-2-GP

1 0R2J-2-GP
DY

SOUNDR
SOUNDL

28
28

+5V_SPK_AMP
MAX9789A_SHDN#
AMP_SHUTDOW N# 36

R538

5V_S0

100KR2J-1-GP
C937
SC4D7U10V3KX-GP

1
2

C936
SC1U10V3KX-3GP

5VA_S0

1
MAX9789A-GP

1 100KR2J-1-GP
DY

2 SC1U10V3KX-3GP

AUD_BIAS
AUD_SET

74.09789.013

2 C931 SC1U10V3KX-4GP
2 C932 SC1U10V3KX-4GP

6K2R2F-GP

AUD_SPK_ENABLE#
AMP_MUTE#_R

R540
0R2J-2-GP

23
25
22
4
10
12
29
24
1

AUD_LIN_R_1 1
AUD_LIN_L_1 1

HP_INR
HP_INL

DY

30

17

VDD

18

HPVDD

2
3

PVSS

R539
2K2R2J-2-GP

GAIN1
GAIN2

21
5

C934
SC1U25V3KX-1-GP

26
27

SB

14

SC1U25V3KX-1-GP
2K2R2J-2-GP
C935
R541
1
2 AUD_HP1_OUT_R1 1
2 AUD_HP1_OUT_R2
1
2 AUD_HP1_OUT_L1 1
2 AUD_HP1_OUT_L2

31
32

CPVSS

AUD_AMP_GAIN1
AUD_AMP_GAIN2

SPKR_EN#
MUTE#
2008/11/15 HP_EN
REGEN
C1P
C1N
VOUT
BIAS
SET
CPGND

HPR
HPL

SPKR_INR
SPKR_INL

13

15
16

DY

R534
2008/12/17

11

SPKR_R+1
SPKR_L+1

PVDD

OUTL+
OUTLOUTROUTR+

CPVDD

SPKR_R+1
SPKR_L+1

6
7
19
20

GND
GND

30
30

SPKR_L+
SPKR_LSPKR_RSPKR_R+

PVDD

SPKR_L+
SPKR_LSPKR_RSPKR_R+

PGND
PGND

30
30
30
30

28
33

1
2

DY

U70

FRONTR
FRONTL

+5V_SPK_AMP

+5V_SPK_AMP

C924
SC1U10V3KX-3GP

C923
SCD1U10V2KX-4GP

1
2

60ohm 100MHz
3000mA 0.05ohm DC

28
28

+5V_SPK_AMP

2 R532
1
0R0603-PAD

C922
SC10U6D3V5MX-3GP

5V_S0

Signal inverter for speaker shutdown

+5V_SPK_AMP

C938
2
1AUD_CPVSS

R542
100KR2J-1-GP

SC1U10V3KX-3GP

AUD_SPK_ENABLE#

AMP_SHUTDOW N# 36
U71
ALC_EAPD

2N7002A-7-GP

R544
MAX9789A_SHDN#

R545
100KR2J-1-GP

3D3V_S0

10KR2J-3-GP

83.00056.E11
DY

+5V_SPK_AMP

D32
BAW 56-3-GP

R543
0R0402-PAD

GAIN SETTING

AMP_MUTE#_R

28

R546
100KR2J-1-GP

DY

DY
AUD_AMP_GAIN1
R547
100KR2J-1-GP

AUD_AMP_GAIN2
R548
100KR2J-1-GP

GAIN1

DY

GAIN2

GAIN

6dB

10dB

15.6dB

21.6dB

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AUDIO AMP
Size

Document Number

Rev

SB

JV50-PU
Date:
A

Friday, December 19, 2008

Sheet
E

29

of

61

Internal Speaker
29
29
29
29

LINE IN

SPKR_LSPKR_L+
SPKR_RSPKR_R+

SPKR_LSPKR_L+
SPKR_RSPKR_R+

LIN1

2008/11/13
2008/11/11

28

RN107

2
1

LINE_IN_R
LINE_IN_L

LINEIN_JD#
LINE_IN_R_CONN

3
4

LINE_IN_L_CONN

SPKR_R-

R512
R513

DY

2
4

PHONE-JK329-GP
EC96

22.10133.G21

MLVG04023R0QV05-GP

SPKR_R1

3
1

SPKR_R+

EC97

2
2

DYDY

MLVG04023R0QV05-GP
2

SB 2008/12/11
2008/10/29

10KR2J-3-GP
10KR2J-3-GP

1
1

SRN75J-2-GP-U

D
METAL

28
28

NP2
NP1
5
4
3
6
2
1

DY

PTW O-CON2-3-GP

SPKR_L-

2ND = 20.F0825.002
3RD = 20.F1297.002
2008/12/17
2008/12/16
2008/11/13
2008/11/11

2
4

RN41

20.F1214.002

2ND = 20.F0825.002
3RD = 20.F1297.002

2
1

MIC_JD#

AUD_MICIN_R_2
3
4
SRN0J-10-GP-U
AUD_MICIN_L_2

1
1
1
1
1
1
1
1

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP164
TP158
TP154
TP163
TP155
TP168
TP166
TP165

INT_MIC_1

AFTE14P-GP

TP4

LINEIN_JD#

AFTE14P-GP

TP172

LINE_IN_R_CONN 1

AFTE14P-GP

TP171

LINE_IN_L_CONN 1

AFTE14P-GP

TP170

DYDY

SPKR_LSPKR_L+
SPKR_RSPKR_R+

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

1
1
1
1

R498
R500

EC94

EC95

DY
MLVG04023R0QV05-GP
2

AUD_SPDIF_OUT
5V_SPDIF_S0
LINEOUT_JD#
LOUT_R+1
LOUT_L+1
MIC_JD#
AUD_MICIN_R_2
AUD_MICIN_L_2

10KR2J-3-GP
10KR2J-3-GP

2
2
B

28

28 AUD_MICIN_R
28 AUD_MICIN_L

1
1

PTW O-CON2-3-GP

DY
SC100P50V2JN-3GP

DY
SC100P50V2JN-3GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY

EC68

MICIN1

NP2
NP1
5
4
3
6
2
1

METAL

DY

EC67

EC2

EC1

MIC IN

MLVG04023R0QV05-GP

SPKR_L+

20.F1214.002

3
1

DY
2

SPKR_L1

PHONE-JK330-GP

22.10133.G31

TP5
TP6
TP18
TP19

SB 2008/12/11

INT MIC

AMIC1

3
1

3
2
1

28 AUD_SPDIF_OUT

5V_SPDIF_S0

5V_SPDIF_S0

C
B
A

DY

C853
SCD1U16V2ZY-2GP

DY

28

LINEOUT_JD#
29
29

RN102

2
1

SPKR_L+1
SPKR_R+1

2
1

74.05240.B7F
= 74.09711.07F
R4722ND
2
1
0R2J-2-GP

3
4

LOUT_L+1
LOUT_R+1

SRN47J-7-GP

2008/11/20

DY2008/12/09

SRN1KJ-7-GP
RN101

2008/12/17

1
2

PHONE-JK332-GP

22.10133.G51

Wistron Corporation

3
4

5
4
3
2
1
7
6

METAL

DY

G5240B2T1U-GP-U

C851
SCD1U16V2ZY-2GP

2ND = 20.F0825.002
3RD = 20.F1297.002

DRIVE
IC

NC#3
GND
OUT

28

LED

IN

INT_MIC

20.F1214.002
TX

EN#

EC58
SC47P50V2JN-3GP

PTW O-CON2-3-GP

NP2
NP1

U56

2
0R2J-2-GP

DY

LOUT1

5V_S0

ER1
1

2
4

LINE OUT
LINEOUT_JD#

INT_MIC_1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

AUDIO JACK
Size

Document Number

Rev

SB

JV50-PU
Date:

Friday, December 19, 2008

Sheet

30

of

61

MDC 1.5 CONN

D

12,28
ACZ_SYNC
12 ACZ_SDATAIN1
ACZ_RST#

C536
SC100P50V2JN-3GP

20.F0917.012
2ND = 20.F0604.012

2008/12/09

R244
1
2
0R2J-2-GP

ACZ_BTCLK_MDC 12

1
R243
100KR2J-1-GP

C534
SC22P50V2JN-4GP

C540
SC4D7U10V5ZY-3GP

DY

3D3V_S5
ACZ_BTCLK_MDC_1

TYCO-CONN12A-2-GP-U1

12,28

3D3V_S5

4
6
8
10
12
17
18

C541
DUMMY-C2

13
14
15

3
0R2J-2-GP
5
ACZ_SYNC_A
1
2
7
R245 1 33R2J-2-GP
ACZ_SDATAIN1_A
2
9
R438
11
1
2ACZ_RST#_MDC
NP2
0R2J-2-GP
16
R437

15
14
2

C539
SC4D7U10V5ZY-3GP

13
NP1
1

ACZ_SDATAOUT_MDC

12 ACZ_SDATAOUT_MDC

MDC1

11

12

16
17
18

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

MDC
Size

Document Number

Rev

JV50-PU
Date:
5

Friday, December 19, 2008

SB
Sheet
1

31

of

61

3D3V_S0

3D3V_D_S0

XD_CD#
SD_WP
SD_CD#
SD_DAT1/XD_D4
XD_D5/MS_BS
XD_D3/MS_D1
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
MS_INS#
SD_DAT6/XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
SD_DAT5/XD_D0
SD_DAT4/XD_WP#
XD_R/B#
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE

R487

2
0R3-0-U-GP

CARD_3D3V_S0
C876
SC1U10V3KX-3GP

DY

CARD_3V3

AV_PLL

AV_PLL

0R2J-2-GP

VREG

10

VREG

3V3_IN

R491

MODE_SEL
SD_CMD
GPIO0
RREF
RST#

24
22

NC#30
NC#7
NC#3

30
7
3

GND
GND
GND
GND

6
12
32
46

EEDO
EEDI

71.05159.00G

15
18

EESK
EECS

USBPN10

DY

C858
SC1U10V3KX-3GP

USBPP10

USB_10+
1
0R2J-2-GP
USB_101
0R2J-2-GP

2
R496
2
R495

R485

2008/11/10

DY

12M_XO

12

XDAL_CTR

1
R482
12
0R2J-2-GP

C864
SC47P50V2JN-3GP

2
2

0R3-0-U-GP

1RST#

R474
100KR2J-1-GP
11,33,34,37,53 PLT_RST1#_B

45
36
14
2
44

MODE_SEL

DY
R479

MODE_SEL
SD_CMD
K VBUS_LED
R494
LED-W -23-GP
1
2 RREF
6K19R2F-GP
RST#
1
2
R480
0R3-0-U-GP
LED1
ADY

5
4

3D3V_D_S0

D3V3
D3V3

17
16

33
11
C852
SCD1U16V2ZY-2GP

DP
DM

1 R484
2 VBUS_R
68R2F-GP
DY

DY

MS_D5
MS_D4

DY

3D3V_S0

-1

2
C873
SCD1U16V2ZY-2GP

3D3V_D_S0

C875
SCD1U16V2ZY-2GP

C871
SC4D7U6D3V5KX-3GP

3V_VBUS_S0

1
0R3-0-U-GP
1

3D3V_S0

XTLO
XTLI

XTAL_CTR

47
48

VREG

C874
SCD1U16V2ZY-2GP

R493

13

2
1

C872
SC1U10V3KX-3GP

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43

U58
RTS5159-GR-GP

3D3V_D_S0

1
0R2J-2-GP

R486
3

CLK48_5158E

12M_XO

0R2J-2-GP

5 IN1 CARD-READER (SD/MMC/MS/MS PRO/XD)

CARD_3D3V_S0

C881
SCD1U16V2ZY-2GP

C880
SC4D7U10V5ZY-3GP

CARD1

DY
SD_DAT5/XD_D0

0R2J-2-GP 1

2 R506

XD_D3/MS_D1

0R2J-2-GP 1

2 R502

SD_DAT4/XD_W P# 0R2J-2-GP 1

SD_DAT0/XD_D6/MS_D0_1
SD_DAT1/XD_D4_1
DY
SD_DAT2/XD_RE#_1
DY
SD_DAT3/XD_W E#_1
DY
SD_W P
DY
SD_CD#
DY
SD_CMD_1
DY
SD_CLK/XD_D1/MS_CLK DY

DY
5

EC88
EC90
EC92
EC89
EC93
EC91
EC86
EC87

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

23
14
33

SD_VCC
MS_VCC
XD_VCC

SD_DAT5/XD_D0_1
SD_CLK/XD_D1/MS_CLK
SD_DAT7/XD_D2/MS_D2_1
XD_D3/MS_D1_1
SD_DAT1/XD_D4_1
XD_D5/MS_BS_1
SD_DAT0/XD_D6/MS_D0_1
SD_DAT6/XD_D7/MS_D3_1

8
9
26
27
28
30
31
32

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

XD_R/B#
SD_DAT2/XD_RE#_1
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_W E#_1
SD_DAT4/XD_W P#_1
XD_CD#

1
2
3
4
5
6
7
34

XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW

CARD_3D3V_S0

2 R505

NP1
NP2
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP

SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

25
29
10
11

SD_DAT0/XD_D6/MS_D0_1
SD_DAT1/XD_D4_1
SD_DAT2/XD_RE#_1
SD_DAT3/XD_W E#_1

R471
R475
R476
R473

2
2
2
2

1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D4
SD_DAT2/XD_RE#
SD_DAT3/XD_W E#

SD_CMD
SD_CLK
SD_CD_SW
SD_WP_SW

12
24
36
35

SD_CMD_1
SD_CLK/XD_D1/MS_CLK
SD_CD#
SD_W P

R470 2

1 0R2J-2-GP

SD_CMD

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

19
20
18
16

SD_DAT0/XD_D6/MS_D0_1
XD_D3/MS_D1_1
SD_DAT7/XD_D2/MS_D2_1
SD_DAT6/XD_D7/MS_D3_1

R501 2
R507 2

1 0R2J-2-GP
1 0R2J-2-GP

SD_DAT7/XD_D2/MS_D2
SD_DAT6/XD_D7/MS_D3

MS_BS
MS_INS
MS_SCLK

21
17
15

XD_D5/MS_BS_1
MS_INS#
SD_CLK/XD_D1/MS_CLK

R503 2

1 0R2J-2-GP

XD_D5/MS_BS

4IN1_GND
4IN1_GND
4IN1_GND
4IN1_GND

13
22
38
37

NP1
NP2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

CARD-PUSH-36P-5-GP

Title

20.I0081.011

CARDREADER- RTS5159

2ND = 20.I0079.011

Size

Document Number

Rev

SB

JV50-PU
Date:
4

Friday, December 19, 2008

Sheet
1

32

of

61

Mini Card Connector(WLAN)

Mini Card Connector(Robson2 and 3G)

3D3V_S0

3D3V_S5 3D3V_S0
3D3V_S5

2008/11/12
2008/11/05

R331
4

53
NP1
1

0R2J-2-GP
R336

R297

MINI1
4

DY

0R2J-2-GP
1

0R2J-2-GP
R296

DY

DY

7.3/9.2mm

0R2J-2-GP
1

1D5V_S0

DY
1

2008/11/12
2008/11/05

MINI3_PW R

2
MINI2_PW R

1D5V_S0

MINI2

53
NP1
1

36
36
8
8
3

8
8

E51_RxD
E51_TxD

C550 1
C549 1
2

PCIE_RXN2
PCIE_RXP2

RXN2
SCD1U16V2KX-3GP
RXP2
SCD1U16V2KX-3GP

PCIE_TXN2
PCIE_TXP2
3D3V_MINI

1R241
2
0R2J-2-GP

5V_S5

5V_S5_MIN2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

USBPN7_1
USBPP7_1

1
2

PCIE_RXN3
PCIE_RXP3

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

DY

10KR2J-3-GP
1
DY 2
R252

8 PCIE_TXN3
8 PCIE_TXP3

DY

W IRELESS_EN 36
1 R251
2
3D3V_S0
PLT_RST1#_B 11,32,34,37,53
0R2J-2-GP

PLT_RST1#_MINI1

SMB_CLK_MINI1
SMB_DATA_MINI1

0R2J-2-GP
1
2E51_RxD_1
E51_RxD
R310
1
2E51_TxD_1
E51_TxD
R307 0R2J-2-GP
DY
DY
C631 1
RXN3
2
C628 1
SCD1U16V2KX-3GP
RXP3
2
SCD1U16V2KX-3GP

36
36
8
8

2208/12/09

C552
SC100P50V2JN-3GP

3 CLK_PCIE_MINI1#
3 CLK_PCIE_MINI1

4
6
8
10
12
14
16

RN72 SRN33J-5-GP-U
4
SMB_CLK 12,26,34
3
SMB_DATA 12,26,34

1 R289
23D3V_S0_MIN1_1
0R2J-2-GP
1
2
R290DY
0R2J-2-GP

3D3V_S5

DY

1 R248
2
USBPN7
0R2J-2-GP
1
2
USBPP7
R246 0R2J-2-GP
LED_W W AN#
TP169 TPAD14-GP
1

5V_S5
12
12

1
R280

DY

C639
SC100P50V2JN-3GP

DY

2008/11/07

DY

3
5
7
9
11
13
15

3 CLK_PCIE_MINI2#
3 CLK_PCIE_MINI2

R250
0R3-0-U-GP

4
6
8
10
12
14
16

3
5
7
9
11
13
15

3D3V_MINI 3D3V_MINI

H=6.0/8.0mm

2 5V_S5_MIN1
0R2J-2-GP

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

10KR2J-3-GP
1
DY 2
R312
W IRELESS2_EN 36
R300
2
1
PLT_RST1# 9,11,26,36
0R0402-PAD
RN78

SMB_CLK_MINI2
SMB_DATA_MINI2
USBPN4_1
USBPP4_1

1
2

1
R292 1
R291
LED_W W AN2#
1

DY

4
3

SMB_CLK 12,26,34
SMB_DATA 12,26,34

SRN33J-5-GP-U
DY 2
0R2J-2-GP
2
DY 0R2J-2-GP
TP15 TPAD14-GP

USBPN4
USBPP4

12
12

W LAN2_LED#_MC 41

2008/11/07
3

SKT-MINI52P-20-GP

W LAN_LED#_MC 41

20.F1117.052
2ND = 62.10043.391
DY

SKT-MINI52P-13-GP

2ND = 20.F1049.052
3RD = 62.10043.511

3D3V_S0

R239 0R2J-2-GP
1
2

3D3V_S5

R240 0R2J-2-GP
1
DY 2

3D3V_MINI

Place near MINI2

3D3V_S0

1D5V_S0

C538
SCD1U16V2ZY-2GP

1
2

C530
SCD1U16V2ZY-2GP

1
2

1
2

C553
SC1U10V3ZY-6GP

DY
2008/11/07

TC13
ST100U6D3VBM-8GP

C522
SCD1U16V2ZY-2GP

C519
SC1U10V3ZY-6GP

1
2

SCD1U16V2ZY-2GP

3D3V_MINI
C521

Place near MINI1

3D3V_S0

1D5V_S0

1
2

1
2

DY

C630
SCD1U16V2ZY-2GP

DY

C594
SCD1U16V2ZY-2GP

DY DY

1
2

TC20
ST100U6D3VBM-8GP

C658
SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

2008/11/07
DY

1
2

C618
SC10U10V5KX-2GP

C667

MINI2_PW R
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY
Title

MINI CARD
Size

Document Number

Rev

SB

JV50-PU
Date:
A

Friday, December 19, 2008

Sheet
E

33

of

61

NEWCARD Connector
NEW 2

DY
1

CARDBUS2P-21-GP-U

21.H0182.001

2ND = 21.H0168.011
3RD = 21.H0183.001
3D3V_S5

NEW 1
12,36,48 PM_SLP_S5#

21
20
19
18
17
16

2008/11/10

12,35,36,42,44,49,60

1
2
3
4
5

PM_SLP_S3#
3D3V_S0
3D3V_NEW _S0
3D3V_S0
3D3V_NEW _S0

STBY#
3_3VIN
3_3VOUT
NC#4
NC#5

SYSRST#
GND
PERST#
CPUSB#
CPPE#

GND
SHDN#
OC#
RCLKEN
AUXIN
NC#16

U26

AUXOUT
NC#14
NC#13
1_5VIN
1_5VOUT

15
14
13
12
11

3D3V_NEW _LAN_S5
1D5V_S0
1D5V_NEW _S0
1D5V_S0
1D5V_NEW _S0

DY
C

W 83L351YG-GP

6
7
8
9
10

NP2
26
25
8 PCIE_TXP5
24
8 PCIE_TXN5
23
DY
C532 1
2 SCD1U16V2KX-3GP RXP5
22
8
PCIE_RXP5
C531
SCD1U16V2KX-3GP
RXN5
1
2
21
8
PCIE_RXN5
20
DY
19
3 CLK_PCIE_NEW
3D3V_NEW _S0
18
3 CLK_PCIE_NEW #
CPPE#
17
12
CPPE#
NEW _PIN16
16
TP167
15
14
3D3V_NEW _LAN_S5
TPS2231_PERST#
13
12
PCIE_W AKE#_NEW
1DY
2
11
12,26 PCIE_W AKE#
R226 0R2J-2-GP
10
1D5V_NEW _S0
RN64
9
1
4 SMB_DATA_NEW 8
DY
12,26,33 SMB_DATA
2
3 SMB_CLK_NEW
7
12,26,33 SMB_CLK
SRN33J-5-GP-U
CONN_TP1 6
TP162
CONN_TP2 5
TP161
CPUTSB#
4
DY
R210 1
USBPP9_1
2 0R2J-2-GP
3
12
USBPP9
R207 1
USBPN9_1
2 0R2J-2-GP
2
12
USBPN9
DY
1
NP1

DY R242

PLT_RST1#_NEW CARD

2
1
0R2J-2-GP

11,32,33,37,53 PLT_RST1#_B

3D3V_S5

TPS2231_PERST#

DY

RN71
CPUTSB# 2
CPPE#
1

DY

C533
SC100P50V2JN-3GP

SRN100KJ-6-GP

74.83351.073
2ND = 74.04156.07T
3RD = 74.02231.073

2208/12/09

CARDBUS26P-20GP-U

62.10081.131

DY

3
4

2ND = 62.10081.151
3RD = 20.F1311.026
Place them Near to Connector

DY

DY

C503

3D3V_NEW _LAN_S5

1
2

DY

C510
SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

C518

C520
SC1U10V3ZY-6GP

1D5V_NEW _S0

3D3V_NEW _S0

SCD1U16V2ZY-2GP

DY

C543
SCD1U16V2ZY-2GP

3D3V_S0

Place them Near to Chip

C512
SCD1U16V2ZY-2GP
B

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

NEW CARD
Size

Document Number

Rev

SB

JV50-PU
Date:

Friday, December 19, 2008

Sheet

34

of

61

FAN1_VCC

5V_S0

C670

DY SC2200P50V2KX-2GP

D20
BAS16-1-GP
83.00016.B11

R9

C679
SC4D7U10V5ZY-3GP

DY

*Layout* 15 mil
C669
SCD1U16V2ZY-2GP

FAN1_VCC

AFTE14P-GP

TP57

FAN1_FG1

AFTE14P-GP

TP58

2008/12/8
FAN1_VCC

10KR2J-3-GP
D

AFAN1

2ND = 83.00016.K11

3RD = 83.00016.F11

2008/11/04

5
FAN1_FG1

3
2
1

4
C18
SC1KP50V2KX-1GP

*Layout* 15 mil

ACES-CON3-GP-U1

20.F0714.003

SA
5V_S0

U2

RUNPW ROK

5
17

SGND1
SGND2
SGND3

8
10
12

G792_DXN2
G792_DXN3

G1

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree

12,34,36,42,44,49,60

PM_SLP_S3#

R7
10R2J-2-GP
1
2

C551

SC470P50V3JN-2GP
SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

Q11
MMBT3904-4-GP

C702

84.T3904.C11
2ND = 84.03904.L06

G2

84.T3904.C11
2ND = 84.03904.L06

2.H/W Shutdown

H_THERMDA 6

Place near chip as close

as possible

C20
SC2200P50V2KX-2GP
H_THERMDC 6

G792_32K

1.For CPU Sensor

RTC_CLK

TSLVC08APW -1-GP

11,15

32KHZ

Q23
MMBT3904-4-GP

C8

14

U16B

GAP-CLOSE

G792SFUF-GP
74.00792.A79

3D3V_S5

C
C17

GAP-CLOSE

R10
49K9R2F-L-GP

DGND
DGND

2
1

42

ALERT#
THERM#
THERM_SET
RESET#

3.System Sensor, Put Plamrest.

G792_DXP2
G792_DXP3

SC470P50V3JN-2GP

15
13
3
2

V_DEGREE

SMBD_Therm 36,54
SMBC_Therm 36,54

ALERT#
T8_HW _SHUT#

G792_32K

13

1
4
14
16
18
19

DXP1
DXP2
DXP3

FAN1
FG1
CLK
SDA
SCL
NC#19

7
9
11

SCD1U16V2ZY-2GP

T8=90

VCC
DVCC

1
1
R11
21KR2F-GP

6
20

C10
SCD1U16V2ZY-2GP

C9

DY

C24
SC1U10V3ZY-6GP

C12
SC4D7U6D3V3MX-2GP

5V_G792_S0

*Layout* 30 mil

5V_S0

2
R12
10R2J-2-GP

2ND = 20.F1000.003

73.07408.L16
2ND = 73.07408.L15
= 73.07408.02B
32K 3RD
suspend
clock output

BL3#
5V_AUX_S5

5V_AUX_S5
B

U43

HW thermal shut down tempature

setting 95 degree . Put Near SB.

T8_HW _SHUT#

LOW 3_OFF

G680LT1UF-GP

R321

DY

R338
6K04R2F-GP

3D3V_AUX_S5

VCC

HYST

1
G709_VCC
SB_TH_HYST

G709T1UF-GP

174KR2F-GP

RSMRST# 6,36

R314
0R2J-2-GP

DY
2

OUT#: Hi active / mount R1110

Low active / mount R1108

SET
GND DY
OUT#

DY R337
D18
BAW 56-7-F-GP
3D3V_AUX_S5

U39

C646
SCD1U16V2ZY-2GP

36,52

1
2
3

S5_ENABLE

DY

1
2
3

R309
0R2J-2-GP

DY

1
1

DY

2
3

R322
0R2J-2-GP

D17
BAT54-4-GP

2 SB_THSET
18KR2F-GP
T8_HW _SHUT#

HTH

1
R311
10KR2J-3-GP

DY

DY

C645
SCD01U16V2KX-3GP
U38

LTH

1
2
3

HTH
DY
GND
RESET#/RESET LTH

R308
150R2J-L1-GP-U
5V_AUX_S5

VCC

1MR2F-GP

DY

DY R330

HTH

DY
2

C656
SCD1U16V2ZY-2GP

DCBATOUT

HW Thermal Throttling

A
B
GND

VCC

DY

NC7S08M5X-NL-GP

S5PW R_ENABLE 46

<Core Design>

3RD = 83.00016.F11

Wistron Corporation

2ND = 83.00016.K11
D16

1
R298

2
1KR2J-1-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

BAS16-1-GP
83.00016.B11

Title

2008/11/07
3

G792

KBC_THERMTRIP# 36
Size

A3
Date:

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

35

of

61

4
3

E51_TxD
DBC_EN

TPAD14-GP
SRN4K7J-8-GP

111
113
CCD_ON 112

E51_TxD
E51_RxD
TP110

DC_BATFULL114
LCD_CB_SEL
14
15

41 DC_BATFULL
19 LCD_CB_SEL
35,52
S5_ENABLE

GPIO34 and GPIO46 swap

VCORF

44

KROW 0
KROW 1
KROW 2
KROW 3
KROW 4
KROW 5
KROW 6
KROW 7

GND
GND
GND
GND
GND
GND

UMA_DISCRETE#
LOW _PW R
ENERGY_DET

UMA

1
R384

SPI_W P#

W PC775L-0DG-GP-U

2
12

ECSCI#_1

4
3
2
1

ECRST#
KA20GATE
KBRCIN#

Q7

12

ECSW I#

84.T3906.A11
2ND = 84.03906.F11

3D3V_S5
3D3V_AUX_S5
3D3V_S5
S5_ENABLE

LOW _PW R
1
2KBC_THERMTRIP#
3 ENERGY_DET
4

8
7
6
5

SRN10KJ-6-GP

2ND = 83.R2002.B8E

3RD = 83.R3004.A8E
DY

1
R88

2
0R2J-2-GP

3D3V_S0

R115
10KR2J-3-GP

R114
10KR2J-3-GP

DY

DY

R113
10KR2J-3-GP

PlanarID
(1,0)
SA: 0,0
SB: 0,1
-1: 1,0
-2: 1,1

RN91
SRN10KJ-6-GP

CRT_DEC#

<Core Design>

MODEL_ID0
UMA_DISCRETE#

R380
10KR2J-3-GP

2nd = 84.27002.E3F

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R393
10KR2J-3-GP
Title

DIS

3D3V_S0

Size

A3
Date:
3

MMBT3906-4-GP

ECSW I#_KBC

CH731UPT-GP
83.R0304.A8H

3D3V_S0

SMBC_Therm 35,54
SMBD_Therm 35,54

RSMRST#

2 ECSCI#_KBC
0R2J-2-GP

C731

RN89

GMCH_BL_ON 9

84.27002.D3F

5
6
7
8

D2

37

0R2J-2-GP

PTW O-CON26-1-GP

ECRST#

DY

1
R71

LOW _PW R 26
ENERGY_DET 26
2008/11/13
BT_LED
41
USB_PW R_EN# 25

2N7002DW -1-GP

28

85

SRN10KJ-6-GP

1
1

VCC_POR#

FIU

6,35

R116
10KR2J-3-GP

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP C
AFTE14P-GP

3D3V_S0

2
THER_SDA

TP48
TP35
TP49
TP36
TP50
TP37
TP51
TP52

RN90

TP_LOCK_LED 41
BLON_OUT 19

Q6

20.K0326.026
2ND = 20.K0320.026

1
1
1
1
1
1
1
1

TP86 TPAD14-GP

THER_SCL

KROW 0
KROW 1
KROW 2
KROW 3
KROW 4
KROW 5
KROW 6
KROW 7

3D3V_AUX_S5

PCB_VER1
PCB_VER0

F_SDI
F_SDO
F_CS0#
F_SCK

54
55
56
57
58
59
60
61

1
2

1
2

KBC_XO_R 2

1
2

MODEL_ID1
SPI_W P_R#

Internal KeyBoard Connector

86
87
90
92

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

PS/2

W PC775L-0DG-GP-U

Change to 71.00773.00G

GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

FRONT_PW RLED 41
STDBY_LED 41
CAP_LED
39
AD_OFF
51
RSMRST#_KBC 12
PM_SLP_S5# 12,34,48
CHARGE_LED 41

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

SPIDI
SPIDO
SPICS#
SPICLK

13
12
11
10
71
72

TP109
TPAD14-GP
Volume_up#
39
W IRELESS2_EN 33

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

TPDATA
TPCLK

5
18
45
78
89
116

103

27

37
37
37
37

PM_SLP_S3# 12,34,35,42,44,49,60
KBC_PW RBTN# 40
AC_IN#
50
LID_CLOSE# 40

MODEL_ID0

BLON_IN

KB1

KCOL0

PCB_VER0
PCB_VER1

SB_ID
Volume_up#

BECKUP#

40
BECKUP#
39 POW ER CONSUMPTION_LED#
41
L-line_LED
39 POW ER CONSUMPTION#
KBC_THERMTRIP# 35
38
TPDATA
38
TPCLK
CRT_DEC# 20

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

KBC

1105

TP189 TPAD14-GP
FP_DETECT#
38

SPI_W P_R# 2 R76

1
0R0402-PAD

AGND

2008/11/04

C146
SCD1U16V2ZY-2GP

1
1

VCORF

SER/IR

GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM

19
46
76
88
115
VCC
VCC
VCC
VCC
VCC

102

4
VDD

AVCC

GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
GPIO16
GPIO34
GPIO36/TB3

1105
AD_IA
50
TP_LOCK_BTN# 40
W IRELESS_BTN# 40
BT_BTN#
40

TP39
TP27
TP40
TP28
TP41
TP29
TP42
TP30
TP43
TP31
TP44
TP32
TP45
TP33
TP46
TP25
TP47
TP34

4
3
2
1

1
2

33
33

GPIO

32KX2
GPIO55/CLKOUT

63
117
Volume_down# 31
32
118
62

KBC_CIR

TP63
12,52 PM_PW RBTN#
39
Volume_down#
28
KBC_BEEP
12
EC_TMR
19
BRIGHTNESS

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

5
6
7
8

RN88

SPI

TPAD14-GP

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

41 W LAN_TEST_LED

GPIO77/SPI_DI
GPIO76/SPI_DO/SHBM
GPIO75/SPI_CLK
GPIO81

79
30

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

DY

DBC_EN

64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110

32KX1/32KCLKIN

KBC_XO

1 10KR2J-3-GP

DY

77

29 AMP_SHUTDOW N#

R66

84
83
82
91

SP

GPIO66/G_PWM

DY

GPIO01/TB2
GPIO03/AD6
GPIO06
GPIO07/AD7
GPIO23/SCL3
GPIO24
GPIO30
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47/SCL4
GPIO50/TDO
GPIO51/TA3
GPIO52/RDY#
GPIO53/SDA4
GPIO70
GPIO71
GPIO72
GPO82/TRIS#

R111
24 BLUETOOTH_EN
10KR2J-3-GP 2008/12/11
19
DBC_EN
1
2 E51_TxD
33 W IRELESS_EN

GPIO41
81

SMB

TPAD14-GP
TP113
TPAD14-GP
TP114

U6B

KBC_XI
10MR2J-L-GP

R85

5V_AUX_S5

SC1U10V3KX-3GP

NUM_LED

39

GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1

GPI94/DA0
GPI95/DA1
GPI96/DA2
GPI97/DA3

X-32D768KHZ-38GPU

3D3V_S0 R112
10KR2J-3-GP
1
2 E51_RxD

BAT_SDA
BAT_SCL

68
67
69
70

D/A

50,51
50,51

BATTERY----->

80
THER_SDA
THER_SCL

THERMAL----->

BAT_IN#

1105

101
105
106
107

BLON_IN

LPC

GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05/AD4
GPIO04/AD5

97
98
99
100
108
96

X2

54

R382
100KR2F-L1-GP

104

82.30001.691
2ND = 82.30001.861
1
2

3D3V_AUX_S5

U6A

VREF

LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
INT_SERIRQ
PM_CLKRUN#
KBRCIN#
KA20GATE

A/D

C194

11,37
11,37
11,37
11,37
11,37
C285
11
1 DY2PCLK_KBC_RC 11
12
SC4D7P50V2CN-1GP
12

1
2

PCLK_KBC
R109
0R2J-2-GPDY

8
7
6
5
1
2
3
4

1
2
11,15

GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#

R87

30KR2F-GP

124
7
2
3
126
127
128
1
125
8
122
121
ECSCI#_KBC 29
9
ECSW I#_KBC123

PLT_RST1#_1

C730
SCD1U16V2ZY-2GP

C232
SC100P50V2JN-3GP

DY

C749
SCD1U16V2ZY-2GP

BAT_IN#

C271

C139
SCD1U16V2ZY-2GP

2208/12/09

C259

C725

C733

SCD1U16V2ZY-2GP

9,11,26,33 PLT_RST1#

3D3V_S0

SC10U6D3V3MX-GP

2 R95
1
0R0402-PAD

3D3V_S0

SCD1U16V2ZY-2GP

51

1 R394
2
0R0603-PAD

SC10U6D3V3MX-GP

LPC_LAD[0..3]

11,37 LPC_LAD[0..3]

SCD1U16V2ZY-2GP

DY

C750
SC1U16V3ZY-GP

SMBC_Therm
SMBD_Therm

C754
SCD1U16V2ZY-2GP

BAT_SCL
BAT_SDA

C751

DY DY

C207

SC15P50V2JN-2-GP

C753
RN39
SRN4K7J-10-GP

VBAT

3D3V_AUX_S5

SC15P50V2JN-2-GP

VBAT
SC10U6D3V3MX-GP

SCD1U16V2ZY-2GP

DY

FOR KBC DEBUG

3D3V_AUX_S5

EC36

3D3V_S0

3D3V_AUX_S5

KBC WPC775

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

36

of

61

3D3V_AUX_S5

5
6
7
8

RN94

DY

SRN10KJ-6-GP

R106
0R0603-PAD

4
3
2
1

2008/10/30
U9

EC34
SCD1U16V2ZY-2GP

SPI_HOLD#

1
2
3
4

CS#
SO/SIO1
WP#/ACC
GND

VCC
HOLD#
SCLK
SI/SIO0

BIOS_VCC
SPI_HOLD#
BIOS_CLK
BIOS_DIO

8
7
6
5

ER3 2
ER2 2

1 0R2J-2-GP
1 0R2J-2-GP

SPICLK
SPIDO

36
36

16M Bits
SPI FLASH ROM

EC75

DY

SC4D7P50V2CN-1GP

DY
72.25165.A01
2ND = 72.25X16.A01

EC76

MX25L1605DM2I-12G-GP

SC4D7P50V2CN-1GP

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

DY

EC78

EC77

1
2BIOS_DO
33R2J-2-GP SPI_W P#

ER4

36

SPICS#
SPIDI
SPI_W P#

36
36

3D3V_AUX_S5

GOLDEN FINGER FOR DEBUG BOARD

11,36 LPC_LAD[0..3]

LPC_LAD[0..3]
DB1
3D3V_S0
11,36 LPC_LAD0
11,36 LPC_LAD1
11,36 LPC_LAD2
11,36 LPC_LAD3
11,36 LPC_LFRAME#
11,32,33,34,53 PLT_RST1#_B
11,15

PCLK_FW H

1
2
3
4
5
6
7
8
9
10
11
12

DY
B

MLX-CON10-7-GP

20.D0183.110

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

Document Number

BIOS
JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

37

of

61

TOUCH PAD
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

SA

5V_S0

5V_S0

TP62
TP68
TP67
TP69
TP70

1
1
1
1
1

5V_S0
TP_DATA
TP_CLK
TP_LEFT
TP_RIGHT

2008/11/12

2
4
3

DY

DY

DY

DY

12
11
10
9
8
7
6
5
4
3
2

TP_DATA
TP_CLK

SRN33J-5-GP-U

1
2
4
3

1
2

14

EC23
SC100P50V2JN-3GP

TPDATA
TPCLK

TPDATA
TPCLK

TPCN1

EC22
SC100P50V2JN-3GP

RN85
36
36

2008/11/12
2008/11/05
2008/10/29

EC74
SC100P50V2JN-3GP

DY

EC73
SC100P50V2JN-3GP

EC26
SCD1U10V2KX-4GP

RN83
SRN10KJ-5-GP

TP_RIGHT

2008/11/11
2008/11/13
TP_LEFT

1
13
PTW O-CON12-3-GP-U

20.K0370.012

2ND = 20.K0315.012

Finger printer

3D3V_S0

2008/10/29
R427
0R0603-PAD

FPCN1
13

12
12
36
12
A

USBPP6
USBPN6
FP_DETECT#
FP_ID

R149 1
R150 1

TP_LEFT
TP_RIGHT

08/02/25 SB Swap FP_ID and FP_DETECT#

3D3V_FP_S0
USBPP6_1
2 0R2J-2-GP
USBPN6_1
2 0R2J-2-GP

2
3
4
5
6
7
8
9
10
11
12
14

PTW O-CON12-3-GP-U

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP132
TP131
TP128
TP126
TP127

1
1
1
1
1

<Core Design>

2008/11/07
3D3V_FP_S0
USBPP6_1
USBPN6_1
FP_DETECT#
FP_ID

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

20.K0370.012

2ND = 20.K0315.012

Size

A3
Date:
5

Touch PAD/Finger printer

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

38

of

61

EC72
1

SB 2008/12/11

PSCN1
SC1U16V3ZY-GP

7
1

3D3V_S0

2
3
4
5
6

POW ER CONSUMPTION#

POW ER CONSUMPTION_LED#_R

36

Volume_Up# 36
Volume_Down# 36
D

3D3V_S0
PTW O-CON6-12-GP

20.K0382.006

2ND = 20.K0320.006
4
3
2
1

2008/10/30
2008/11/06
2008/11/11

2008/12/18
2008/11/12

2008/11/06

Q20
36 POW ER CONSUMPTION_LED#

RN93

R1

POW ER CONSUMPTION_LED#_R

Volume_Up#
Volume_Down#
POW ER CONSUMPTION#

R2
DTC143ZUB-GP

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

NUM_LED

NUM_LED#_R

R1

R263
1
2
56R2J-4-GP

2008/11/12

Q17

CAP_LED

CAP_LED#_R

R1

2008/10/30
R265
1
2
56R2J-4-GP

A
LED-B-98-GP

2008/11/12
5V_S0

2008/10/30

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

5V_S0

CAP_LED1
CAP_LED#

2
R2
DTC143ZUB-GP

13

A
LED-B-98-GP

R2
DTC143ZUB-GP

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K
36

5V_S0

NUM_LED1
NUM_LED#

Volume_Up#_1
Volume_Down#_1
POW ER CONSUMPTION#_1

8
7
6
5
SRN470J-3-GP

2008/11/12
2008/10/30
Q16

36

1
2
3
4

5
6
7
8

RN92
SRN10KJ-6-GP

MEDIA_LED1

MEDIA_LED#

R264 2
100R2J-2-GP

A
LED-B-98-GP

DY

Power consumption# 1
EC71
NUM_LED#_R
EC61
CAP_LED#_R
EC63
MEDIA_LED#
EC62

2
SC220P50V2JN-3GP

DY
1

2
SC220P50V2JN-3GP

POW ER CONSUMPTION#

AFTE14P-GP

TP55

Volume_Up#

AFTE14P-GP

TP53

Volume_Down#

AFTE14P-GP

TP38

5V_S0

AFTE14P-GP

TP125

3D3V_S0

AFTE14P-GP

TP56

DY
1

2
SC220P50V2JN-3GP
POW ER CONSUMPTION_LED#_R

DY
1

AFTE14P-GP

TP54

2
SC220P50V2JN-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

LAUNCH BOARD

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

39

of

61

Cover Up Switch

Power Button
PW R_SW 1

KBC_PW RBTN#_1

3D3V_AUX_S5
D

EC3
SC1KP50V2KX-1GP

2008/11/13
LID1

SW -TACT-119-GP

62.40009.671

2nd:62.40012.101
3D3V_AUX_S5
RN80

1
2

Beckup Button

VDD

LID_CLOSE#

EC70
SCD1U16V2ZY-2GP

ME268-002-GP

KBC_PW RBTN#
LID_CLOSE#

4
3

OUT

74.00268.07B

SRN10KJ-5-GP

LID_CLOSE# 36

GND
2

DY
2

DY
1

2008/10/27

EC69
SCD1U16V2ZY-2GP

BK_SW 1

Beckup#_1

3
1

2008/10/27

DY EC4

SC1KP50V2KX-1GP

SW -TACT-119-GP
C

3D3V_S0

62.40009.671

2ND = 62.40012.101

RN4

1
2
3
4

8
7
6
5

W IRELESS_BTN#
BT_BTN#
BECKUP#

SRN10KJ-6-GP

WIRELESS Button
2008/11/11
W LAN_SW 1
3

2008/10/27
4

RN3
Beckup#_1
1
BT_BTN#_1
2
W IRELESS_BTN#_1 3
KBC_PW RBTN#_1 4

DY EC6
2

W IRELESS_BTN#_1

SC1KP50V2KX-1GP

8
7
6
5

Beckup#
BECKUP#
36
BT_BTN#
BT_BTN#
36
W IRELESS_BTN#
W IRELESS_BTN# 36
KBC_PW RBTN#
KBC_PW RBTN# 36

SRN470J-3-GP

SW -TACT-119-GP

62.40009.671

2ND = 62.40012.101

3D3V_S0

T/P lock Button

R233
10KR2J-3-GP

BT_SW 1

5
BT_BTN#_1

2008/10/27

470R2J-2-GP

DY EC5
2

R227
1

2
5

2008/10/27

TP_LOCK_BTN#_1

SW -TACT-119-GP

SC1KP50V2KX-1GP

TP_SW 1

BT/3G Button
2

TP_LOCK_BTN# 36

EC51
SC1KP50V2KX-1GP

DY

62.40009.671

SW -TACT-119-GP

62.40009.671

2ND = 62.40012.101

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

Document Number

SWITCH
JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet

40
1

of

61

Q29
36 FRONT_PW RLED

PW RLED#_DB

R1

2008/11/07

2
R2
DTC143ZUB-GP

5V_S5

PW R_LED1

2008/11/06

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

FRONT_PW RLED#_R

2008/11/04

2008/11/06
RN74

Q30
36

R1

STDBY_LED

STDBY_LED#_BD

SRN300J-1-GP
4
3
2
1

R2

84.00143.G1K DTC143ZUB-GP
2ND = 84.00143.D1K
3RD = 84.00143.E1K
Q31

36

DC_BATFULL

3D3V_S5

PW RLED#_DB
PW RLED#_DB

1
2

4
3

PW R_LED4
FRONT_PW RLED#_1
K
A

5
6
7
8

LED-OB-2-GP

83.01221.I70

SRN100J-3-GP

2008/11/04

83.19223.A70

RN110

PW R_LED3
FRONT_PW RLED#_2
K
A

SA
2008/11/07
2008/11/04

2
R2
DTC143ZUB-GP

5V_S5

LED-B-77-GP-U2

2008/11/06

DC_BATFULL#

R1

STDBY_LED#_R

2008/11/06

5V_S5

LED-B-77-GP-U2

5V_AUX_S5

83.01221.I70

2008/11/06
CHARGER_LED1

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

DC_BATFULL#_R

CHARGE_LED#_R

Q32

R1

36 CHARGE_LED

CHARGE_LED#
3D3V_AUX_S5

LED-OB-2-GP

83.19223.A70

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

2008/11/06

2
R2
DTC143ZUB-GP

2008/11/04
R258

2008/11/06
Q14
36

L-line_LED#

1
2

2
R2
DTC143ZUB-GP

PW RLED#_DB

PW R_LED5

RN73

R1

L-line_LED

2008/11/06

2008/12/16

4
3

L-line_LED#_1

5V_S5

FRONT_PW RLED#_3K

PW R_LED2
A

5V_S5

100R2J-2-GP

LED-B-77-GP-U2

2008/11/06

83.01221.I70

LED-B-98-GP
SRN100J-3-GP

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

2008/12/16
PW R_LED6
L-line_LED#

L-line_LED#_2

2008/12/03
5V_S5
L-line_LED#

LED-B-98-GP

R530
1
2
56R2J-4-GP

PW R_LED7

5V_S5

LED-B-98-GP
3D3V_S0

2208/12/09
Q10
36 TP_LOCK_LED

TP_LOCK_LED#

R1

L-line_LED#

R219

2
R2
DTC143ZUB-GP

TP_LOCK_LED#_1 2

TP_LED1
1

R531
1
2
56R2J-4-GP

PW R_LED8

2008/12/03

5V_S5

LED-B-98-GP
B

LED-Y-29-GP

100R2J-2-GP

83.00190.S70

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K
D1

R1

1
2

33R2J-2-GP
Q4

BAW 56-5-GP

R2
R1

DTA143ZUB-GP

LED-Y-29-GP

83.00190.S70

.
.
. .

W LAN2_LED#_1

W LAN_LED#_2

83.00056.Q11
2ND = 83.00056.K11
3RD = 83.00056.G11

Q2

W LAN_LED1
1

W LAN_LED#
75R2J-1-GP

84.00143.F1K
3RD = 84.00143.C1K

R5

DTA143ZUB-GP

33 W LAN2_LED#_MC

R4

W LAN_LED#_1

R2

33 W LAN_LED#_MC

3D3V_S0

2008/11/06

Q1

36 W LAN_TEST_LED

84.00143.F1K
3RD = 84.00143.C1K

2N7002E-1-GP

84.2N702.D31
2ND = 84.2N702.I31

2008/11/06
A

5V_S0
Q3
36

BT_LED

R1

BT_LED#

R6
1
2 BLT_LED#_1
390R2J-1-GP

Wistron Corporation

BT_LED1
A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

LED-B-98-GP

2
R2
DTC143ZUB-GP

Title

83.00193.A70

Blue-tooth LED

84.00143.G1K
2ND = 84.00143.D1K
3RD = 84.00143.E1K

Size

A3
Date:

Document Number

LED
JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet

41
1

of

61

3D3V_S0

4
3

2D5V_S0

RN99
SRN100KJ-6-GP
D

1
2

C825

D27
2D5V_S0_PG

SC1U10V3ZY-6GP
12,34,35,36,44,49,60

VCORE_EN 45,47

PM_SLP_S3#

BAW 56-5-GP

83.00056.Q11
2ND = 83.00056.K11
3RDR457
= 83.00056.G11

46

3V/5V_POK

DY

0R2J-2-GP
R456
1 DY
2

48 1D8V_S3_PW RGD

0R2J-2-GP

P/H @ 1D8V_S3 PAGE

R120
45

DY

VRM_PW RGD

1D1V_PW RGD 47

0R2J-2-GP

1D8V_S3

.
.
. .

Q9

3D3V_S5

S
U16C

14
12,34,35,36,44,49,60

8
10

47

1D1V_PW RGD

RUNPW ROK

3
35

RUNPW ROK_D

NB_PW RGD 9,12

2ND = 84.2N702.I31

SB_PW RGD 12
B

TSLVC08APW -1-GP

D3

2N7002E-1-GP

84.2N702.D31

PM_SLP_S3#

73.07408.L16
2ND = 73.07408.L15
RUNPW ROK_D 3
3RD = 73.07408.02B

PH in page 3
BAW 56-5-GP

83.00056.Q11
2ND = 83.00056.K11
3RD = 83.00056.G11

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

POWER ON LOGIC
Size

A3
Date:
5

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

42

of

61

Adapter
Input Signal
AD_OFF

Input Signal

AD_IN#

(O)

Input Power
AD_JK

Output Signal

Input Signal
VCORE_EN

ENTRIP1

Output Power

VCC(I)

DCDC 1D2V(RT8202)

EN0
S5_ENABLE

DCDC 5V/3D3V(TPS51125)

Output Signal

(I)

ENTRIP2

PGOOD

Input Power
DCBATOUT

Output Power
VCLK

VIN

CPU_CORE
ISL6265HRTZ

VREG3
VREG5

Input Signal

Output Signal

SVD

VOUT
VRM_PWRGD

PGOOD

CPU_SVC

PGOOD

3V/5V OK

Input Power

VOUT

V5FILT

+15V_ALW
3D3V_AUX_S5

Output Power

V5DRV
DCBATOUT

VTT

1D2V_S0

V(I)

5V_AUX_S5
3D3V_S5
5V_S5

SVC

DCDC 1D1V(RT8202)

VCORE_EN

ENABLE

DCDC 1D8V(RT8202)

CPU_PWRGD_SVID_REG

PWROK
Input Power

+5V_RUN

Input Signal
PM_SLP_S5#

Output Power

VCC

DCBATOUT

VCC_CORE(O)

VIN

VCC_CORE(O)
VCC_CORE(O)

Input Signal

EN_PSV

PGOOD

1D2V_PWRGD

Input Power

5V_S5
VCC_CORE1

Output Power

V5IN
DCBATOUT

VDDNB

VTT

G9161
PM_SLP_S5#

+5V_SUS
1D8V_S3

EN_PSV

PGOOD

Input Signal

1D1V_PWRGD

Output Power

V5FILT
V5DRV

V(I)

DCBATOUT

RT9026

VTT

1D2V_S0

V(I)

CHARGER MAX8731

Output Signal

LDO_SHDN#

Output Signal

1D8V_S3_PWRGD
Input Power

VCC_VORE0

Output Signal

Input Signal

Output Signal

0D9V LDO
1D2V LDO

1D2V_PWRGD
EN_PSV

AD+

VCC(O)

5V_S5

CPU_SVD

Output Signal

Input Signal

LDO_POK

MAX8731A ACIN

Output Signal

ACIN
MAX8731A ACOK

5V_S5
Input Power
3D3V_S5

IN

OUT

Input Power

Output Power

VIN

Output Power
1D2V_S5

1D8V_S3

PBAT_SMBDAT

LDO_OUT

VLDOIN

0D9V_S3

PBAT_SMBCLK

LDO_OUT

ACOK

SDA
SCL
Input Power

1D5V LDO
2D5V LDO
Input Signal

R9161

G9571

Input Signal

Output Signal

Input Power
Input Power
IN

3D3V_AUX_S5

Output Signal

3D3V_S0

AD+

Output Power
OUT

3D3V_S0
2D5V_S0

Output Power

IN

OUT

DCIN
VDDSMB

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

A3
Date:
3

1D5V_S0

Size

+VCHGR

V(O)

Title

Output Power

Power Block Diagram

Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

43

of

61

Aux Power
I min = 150 mA

3D3V_AUX_S5

5V_S0

1
2
3
4

DCBATOUT
RUN_POW ER_ON

84.04800.D37
2ND = 84.04468.037

3D3V_S0

3D3V_S5

U25
D31
PDZ9D1B-GP

1
2
3
4

83.9R103.C3F

SI4800BDY-T1 2008/12/18
84.04800.D37
2ND = 84.04468.037

1
2

1
1

R529
100KR2J-1-GP

2ND = 83.9R103.F3F

1D8V_S0
U49

1
2
3
4

Q33
2N7002-11-GP

PM_SLP_S3# 12,34,35,36,42,49,60
R431

2N7002EDW -GP
Z_12V_D3

84.27002.W31
2ND = 84.27002.Y31

1MR2F-GP

84.27002.F3F

2008/10/30

2ND = 84.27002.G3F

SI4800BDY-T1 2008/12/18
84.04800.D37
= 84.04468.037
2008/10/29

C795
SC22P50V2JN-4GP

DY

8
7
6
5

1D8V_S0_ON
2ND

Z_12V_D3

U67
3D3V_runpwr

8
7
6
5

1D8V_S3

Z_12V_D4

DY R524
100R5J-3-GP

R526
330KR2J-L1-GP

10KR2J-3-GP

2ND = 84.00610.C31
2 R523
1 Z_12V_G3
330KR2J-L1-GP
3D3V_S0

C921 1

R525

8
7
6
5

SI4800BDY-T1

D
SCD22U25V3KX-GP

2 Z_12V
S
10KR2J-3-GP
Q28
NDS0610-NL-GP
84.S0610.B31

1
R522

DY

2nd source:74.09198.G7F

BC1

1
2

G909-330T1U-GP
74.00909.03F

GAP-CLOSE-PW R

C546
SCD1U25V3KX-GP
1 DY2

G
S
S
S

Run Power

D
D
D
D

NC#4

3D3V_AUX_S5_G 1

G
S
S
S

D
D
D
D

VOUT

SC1U16V3ZY-GP

SC1U16V3ZY-GP

DY

5V_S5

U28
G
S
S
S

BC2

2008/12/18

G9

VINDY
GND
SHDN#

3D3V_AUX_S5

U11

1
2
3

D
D
D
D

5V_AUX_S5
D

DIS

3D3V_M92

R342

U44
APM2300AAC-TRLGP
84.02300.B31

2ND = 84.03400.A37

3D3V_M92_ON

DIS
2MR2F-GP

C675
SC22P50V2JN-4GP

3D3V_S5

DIS

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

RUN AND AUX POWER

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

44

of

61

DCBATOUT

DCBATOUT_6265_1

G4

1
2
54K9R2F-L-GP

2 R395
1
910KR2J-GP

DY

2 R396
1
0R2J-2-GP

DY

6265_FB0_R
1
C742
5

2
SC1KP50V2KX-1GP

1
2

R102
1KR2F-3-GP
1
2
3D3V_S0

R90

DY

2 R91
1
0R2J-2-GP

DY

R379
1 DY
2
10R2F-L-GP NTC-10K-9-GP
ISP1_R

DY 2

ISN1
2
G7

2
SC1KP50V2KX-1GP
C241

C218
1
2

6265_FB1_R
1
C217

1
2

1
2

1
1

54K9R2F-L-GP SC1KP50V2KX-1GP

2 R92
1
316KR2F-GP

1
2

G
S
S
S

R100

1
ISP1

C261 SC180P50V2JN-1GP
1
2DY

C236
1
2

1
2
249R2F-GP
SC4700P50V2KX-1GP SC180P50V2JN-1GP

R392

1
2
6K81R2F-1-GP
SC180P50V2JN-1GP

4
3
2
1

4
3
2
1

TC6
TC23 3RD =
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP

R93
1
2
C240 SCD1U16V2KX-3GP

S
S
S
G

3D3V_S0

C738
1
2

C237
1
2

2
4K02R2F-GP

4
3
2
1

1
S
S
S
G

1
2
1
2
249R2F-GP
C740 SC1KP50V2KX-1GP
SC4700P50V2KX-1GP SC180P50V2JN-1GP

R98

79.33719.L01
2ND = 77.C3371.051
77.23371.13L

TC5

Close to
CPU socket
84.01712.037
84.01712.037
2ND = 84.57N03.A372ND = 84.57N03.A37

R391

to
PWM IC

LGATE1

ESR=15mohm

Parts

U7
AOL1712-GP

2
L-D36UH-1-GP

R107
16K2R2F-GPclose

D
D
D
D

Parallel

D
D
D
D

BOOT1 1
2
C288
SCD22U10V3KX-2GP
U8
AOL1712-GP

6265_FB1_C

79.22719.20L
2ND = 80.2271V.A9L
3RD = 77.22271.20L

VCC_CORE_S0_1
Design Current: 12.6A
Peak current: 18A
OCP_min:24A

68.R3610.20A
2ND = 68.R3610.20C
VCC_CORE_S0_1

2008/12/18L47

5
6
7
8

6 CPU_VDD1_RUN_FB_L
6 CPU_VDD1_RUN_FB_H

C741 SC180P50V2JN-1GP
1
2 DY

68.4R710.20D
TC28
2ND = 68.4R71C.10A

LGATE_NB

UGATE1
PHASE1

1
2

5
6
7
8
4
3
2
1

1
2

1
2

84.01426.037
2ND = 84.12003.A37

C178
SCD1U25V3KX-GP

DY

C179
SC10U25V6KX-1GP

C180
SC10U25V6KX-1GP

C181
SC10U25V6KX-1GP

U5
AOL1426-GP

R96

R97
10R2F-L-GP

L53
PHASE_NB 1
2
IND-4D7UH-88-GP

84.04800.D37
2ND = 84.08884.037

DY 0R2J-2-GP

R388
10R2J-2-GP

C822

VDDNB: Design Current: 2.1A

Peak current: 3A OCP_min:5A

DCBATOUT_6265_2
ISN1
ISP1

6 CPU_VDD0_RUN_FB_H
6 CPU_VDD0_RUN_FB_L

1KR2F-3-GP
1 R397
2

UGATE_NB
BOOT_NB 1
2
C364
SCD22U10V3KX-2GP

S
S
S
G

R103
10R2J-2-GP

C406

VDDNB
C320
SC2D2U10V3KX-1GP

D
D
D
D

R387
10R2J-2-GP

Close to
CPU socket

C746
1
2

ISP0

5
6
7
8
LGATE1
PHASE1
UGATE1
BOOT1

U53
SI4800BDY-T1

6265_VDIFF1
6265_FB1
6265_COMP1
6265_VW1

ISP0
ISN0

1D8V_S3
VCC_CORE_S0_0
VCC_CORE_S0_1

C744
1
2

84.04800.D37
2ND = 84.08884.037

74.06265.A73

change to 74.06265.A73

R398

5V_S0
LGATE0

ISP0
ISN0
VSEN0
RTN0
RTN1
VSEN1
VDIFF1
FB1
COMP1
VW1
ISP1
ISN1

U10

U50
SI4800BDY-T1

BOOT_NB
BOOT0
UGATE0
PHASE0

36
35
34
33
32
31
30
29
28
27
26
25

G
S
S
S

BOOT_NB
BOOT0
UGATE0
PHASE0
PGND0
LGATE0
PVCC
LGATE1
PGND1
PHASE1
UGATE1
BOOT1

13
14
15
16
17
18
19
20
21
22
23
24

ISL6265HRTZ-T-1-GP

GNDA_VCORE

6265_FB0_C

4
3
2
1

4
3
2
1

C393

DY

SE220U2VDM-8GP

GAP-CLOSE-PW R-3-GP

2008/12/18

GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB

OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0
FB0
COMP0
VW0

G10

close
to L75

SCD1U25V3KX-GP

GNDA_VCORE

GAP-CLOSE-PW R-3-GP
R862

SC10U25V6KX-1GP

1
2
3
4
5
6
7
8
9
10
11
12

CPU_PW RGD_SVID_REG
R119 1 0R0402-PAD
6265_SVD
2
R117 1 0R0402-PAD
6265_SVC
2
R118 1 0R0402-PAD
6265_ENABLE
2
6265_RBIAS
1
2
R400 93K1R2F-L-GP
6265_OCSET
6265_VDIFF0
6265_FB0
6265_COMP0
6265_VW 0

1
2
R399 23K7R2F-GP

CPU_VDDNB_RUN_FB_L

ISP0_R
ISN0
2
G8

79.33719.L01
2ND = 77.C3371.051
3RD = 77.23371.13L
79.33719.L01
2ND = 77.C3371.051
3RD = 77.23371.13L

SC10U25V6KX-1GP

GNDA_VCORE

42
VRM_PW RGD
6 CPU_PW RGD_SVID_REG
6
CPU_SVD
6
CPU_SVC
42,47 VCORE_EN

R129 2
1
0R0402-PAD

84.01712.037
84.01712.037
2ND = 84.57N03.A372ND = 84.57N03.A37

79.33719.L01
2ND = 77.C3371.051
3RD = 77.23371.13L

1
2
C735 SCD1U16V2KX-3GP
R390
R402
1
2
DY 2 1 DY
10R2F-L-GP
NTC-10K-9-GP

4
3
2
1

GNDA_VCORE

R121DY
0R2J-2-GP

R403
10KR2F-2-GP

2008/11/12
2008/12/08
2008/12/18

UGATE_NB

CPU_VDDNB_RUN_FB_L_R

LGATE0

TC4
TC3
TC25
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP

DCBATOUT_6265_3

1
2

GNDA_VCORE

CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L

5
6
7
8

6265_OFS/VFIXEN

3D3V_S0

1 R385
2
4K02R2F-GP

5
6
7
8

DY

R122
0R2J-2-GP

4
3

SRN10J-7-GP

DY

10KR2F-2-GP

6265_VIN
6265_VCC
6265_FB_NB
6265_COMP_NB
6265_FSET_NB
6265_VSEN_NB

R123
0R0603-PAD

RN45

1
2

PHASE_NB

49
48
47
46
45
44
43
42
41
40
39
38
37

R124

C767
SCD1U25V3KX-GP

PHASE_NB
1 R125
2
11K3R2F-2-GP
LGATE_NB

L49
2
L-D36UH-1-GP

to
PWM IC

S
S
S
G

GAP-CLOSE-PW R

3D3V_S0

Parts

VDDNB

1 R414
2R3J-GP

S
S
S
G

5V_S0

U13
AOL1712-GP

VCC_CORE_S0_0
Design Current: 12.6A
Peak current: 18A
OCP_min:24A
68.R3610.20A
2ND = 68.R3610.20C
VCC_CORE_S0_0

R389
16K2R2F-GPclose

D
D
D
D

DCBATOUT_6265_3

GAP-CLOSE-PW R
G14
1
2

CPU_VDDNB_RUN_FB_H

BOOT0 1
2
C346
SCD22U10V3KX-2GP
U12
AOL1712-GP

GNDA_VCORE
R1301 0R0402-PAD
2

2008/12/18

D
D
D
D

GAP-CLOSE-PW R
TC7
G13
ST15U25VDM-1-GP
1
2

UGATE0
PHASE0

5
6
7
8

C768
SC1U10V3KX-3GP

GNDA_VCORE

2008/11/10

2
SCD1U10V2KX-4GP

1 R132
2
22KR2F-GP

GAP-CLOSE-PW R
G12
1
2

2R3J-GP

1
C380

C384

DCBATOUT_6265_1
G11

6265_OCSET_NB

DCBATOUT

4
3
2
1

2
SC1KP50V2KX-1GP

R415
GAP-CLOSE-PW R

5
6
7
8
1 R131
26265_FB_NB_R
1
44K2R2F-1-GP
C376

5V_S0

84.01426.037
2ND = 84.12003.A37

U15
AOL1426-GP

C377 SC180P50V2JN-1GP
1
2

5
6
7
8

1
2

GAP-CLOSE-PW R
G6
1
2

2008/11/04

2
SC33P50V2JN-3GP

C382
SC10U25V6KX-1GP

1
C374

C387

DY

SCD1U25V3KX-GP

C383
SC10U25V6KX-1GP

TC8
ST15U25VDM-1-GP
GAP-CLOSE-PW R
G5
1
2

SC10U25V6KX-1GP
D
S
D
S
D
S
D
G

GAP-CLOSE-PW R

GAP-CLOSE-PW R
G3
1
2

1
2

GAP-CLOSE-PW R
G16
1
2

D
D
D
D

DCBATOUT_6265_3
G15

D
D
D
D

DCBATOUT

DCBATOUT_6265_2

R858 close
to 79.33719.L01
L77

79.33719.L01
2ND = 77.C3371.051
3RD = 77.23371.13L

2ND = 77.C3371.051
<Core Design>
3RD = 77.23371.13L
A

Wistron Corporation

GAP-CLOSE-PW R-3-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

1 R94

CPU Vcore(ISL6265HR)
Size

6K81R2F-1-GP

A3

2
SC180P50V2JN-1GP

Date:
3

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

45

of

61

DCBATOUT_62392

DCBATOUT

GAP-CLOSE-PW R
G35
1
2
D

GAP-CLOSE-PW R
G38
1
2

GAP-CLOSE-PW R
G21
TC11
1
2
ST15U25VDM-1-GP
GAP-CLOSE-PW R
G19
1
2

GAP-CLOSE-PW R
G41
1
2

R183

2
1

35 S5PW R_ENABLE

GAP-CLOSE-PW R
TC10
G22
ST15U25VDM-1-GP1
2

2008/11/07

3D3V_PW R

3V/5V_EN

2KR2F-3-GP

G29
R186
200KR2F-L-GP

GAP-CLOSE-PW R
G18
1
2

GAP-CLOSE-PW R
G23
1
2

GAP-CLOSE-PW R
G17
1
2

GAP-CLOSE-PW R
G31
1
2

GAP-CLOSE-PW R

GAP-CLOSE-PW R

GAP-CLOSE-PW R
G27
1
2

DCBATOUT_62392

DCBATOUT_62392

1
2

SCD1U25V3KX-GP

TC12

ST220U6D3VDM-20GP
2

C517

2008/11/05
2008/10/21
77.22271.27L
2ND = 77.C2271.00L

G
S
S
S

4
3
2
1
5
6
7
8

C448
SC1200P50V2KX-1GP

20081127
1

42

6239_VCC

R168
0R2J-2-GP

62392_FB1_R

R175
3K3R2F-2-GP

2008/12/17

20081120
6239_FSET1

DY

R180
68K1R2F-1-GP

C438
SC1U25V3KX-1-GP

1
2

D
D
D
D

5
6
7
8

6239_FCCM

DY

C529
1

2008/12/18

4
3
2
1

G
S
S
S

84.04812.A3730KR2F-GP
2ND = 84.08878.037

3D3V_AUX_S5
3V/5V_POK

1 R174
2
0R2J-2-GP

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

1 R173
2
100KR2F-L1-GP

R178

2008/12/19

9K09R2F-GP

1
R170
24K3R2F-1-GP

Polymer
220uF,6.3V,25mohm,Iripple=2.236A
OS-CON
220uF,6.3V,10mohm,Iripple=3.9A

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

Polymer
220uF,6.3V,25mohm,Iripple=2.236A
OS-CON
220uF,6.3V,10mohm,Iripple=3.9A

R172
C439
19K6R2F-GP

C445

2008/12/19

1 R169
2
0R0402-PAD

2008/12/18

1 R237

2008/12/18

29

6239_VCC

2
IND-3D3UH-57GP

PGND

2008/12/18

19

EN1
EN2
LDO3EN
FCCM
FSET1
FSET2

R184 0R2J-2-GP
3V/5V_EN
1
2
1
2
R185 0R2J-2-GP

2008/12/19

5V_PW R

PVCC
VCC

11
24
5
3
6
2

6239_FB2

Iomax=6A
OCP>9A

18
4

D
D
D
D

VIN

17

28

FB2
PGOOD

2008/11/04

1R202
2
0R0402-PAD-1-GP

C466

2
1

5V_AUX_S5

R177
10KR2F-2-GP

LDO3

6239_OCSET2
6239_ISEN2

GAP-CLOSE-PW R

68.3R310.20A
2ND = 68.3R31A.10E

ISL62392HRTZ-T-GP

1
2
0R0402-PAD-1-GP

SC4D7U10V3KX-GP

2008/12/17

SC4D7U10V3KX-GP

R176
3K3R2F-2-GP

C465

25
26
27

R182
1

R181
1
30KR2F-GP
2

6239_PVCC

OCSET2
ISEN2
VOUT2

FB1

16

R201

20081127
62392_FB2_R

OCSET1
ISEN1
VOUT1

6239_LDO3

1
R179
45K3R2F-L-GP

10
9
8

6239_FB1

2008/12/18
3D3V_AUX_S5

6239_LGATE2

30KR2F-GP
2

6239_OCSET1
6239_ISEN1

2008/10/21
2008/11/05

C447
SC1200P50V2KX-1GP

6239_PHASE2

U23

Id=7.7A
2ND = 84.08878.037
Qg=8.5~13nC
Rdson=16.5~21mohm

77.22271.27L
2ND = 77.C2271.00L

20

GAP-CLOSE-PW R
G28
1
2

Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
L30

6239_FSET2

84.04812.A37

23

LGATE2

GND

1
2
3
4
8
7
6
5

2008/12/18 Roc=Ioc*DCR/10uA

2
8
7
6
5

30KR2F-GP

1
2
3
4

1
2

SCD1U25V3KX-GP

PHASE2

LGATE1

C457
SCD22U25V3KX-GP
1
2

C493

SCD1U10V2KX-4GP

PHASE1

15

R196
2D2R2F-GP
1
2
6239_UGATE2

C485

SCD01U50V2KX-1GP

R236

12

6239_LGATE1

U24
Id=7A
SI4800BDY-T1
Qg=8.7~13nC
Rdson=23~30mohm

SI4812BDY-T1-E3-GP

SI4812BDY-T1-E3-GP

SCD1U10V2KX-4GP

U22

G
S
S
S

C528

D
D
D
D

C537

6239_PHASE1

C473

SC10U25V6KX-1GP

68.3R310.20A
L/DCR=RC
2ND = 68.3R31A.10E

21
22

84.04800.D37
2ND = 84.08884.037

SC10U25V6KX-1GP

2
IND-3D3UH-57GP

BOOT2
UGATE2

C463
SCD01U50V2KX-1GP

G
S
S
S

C455
R195
U19
SCD22U25V3KX-GP
2D2R2F-GP
2
16239_BOOT_1
1
26239_BOOT1
14 BOOT1
6239_UGATE1
13 UGATE1

L29

SC10U25V6KX-1GP

D
D
D
D

Rdson=23~30mohm

84.04800.D37

Cyntec 7*7*3 2ND = 84.08884.037

DCR=30mohm, Irating=6A
Isat=13.5A

2008/12/19

Id=7A

U21
Qg=8.7~13nC
SI4800BDY-T1

DY C471

C486
SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD01U50V2KX-1GP

Iomax=7A
OCP>10.5A

C474

C494

GAP-CLOSE-PW R

ST220U6D3VDM-20GP
2

DCBATOUT_62392
GAP-CLOSE-PW R
G25
1
2

GAP-CLOSE-PW R
G36
1
2

TC14

GAP-CLOSE-PW R
G26
1
2

GAP-CLOSE-PW R
G39
1
2

3D3V_PW R

GAP-CLOSE-PW R
G30
1
2

GAP-CLOSE-PW R
G37
1
2

3D3V_S5

G20

G40

DCBATOUT_62392

G24

5V_S5

DCBATOUT
5V_PW R

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Vout=0.6*(1+R1/R2)
Title
Size
A3
Date:
5

ISL62392 5V/3D3V

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

46

of

61

DCBATOUT

DCBATOUT_51124
1D1V_PW R

G63

G55

3RD = 79.10112.3JL
DCBATOUT

S
S
S
G

84.04800.D37
2ND = 84.08884.037

1
2

GAP-CLOSE-PW R
G57
1
2

GAP-CLOSE-PW R
G59
1
2

Iomax=8A

DCBATOUT_51124_1
G49

GAP-CLOSE-PW R
TC17
G51
SE390U2D5VM-2GP
1
2

1
2

2
1
2

D
D
D
D

5
6
7
8
2

R318
39K2R2F-L-GP

84.04812.A37
2ND = 84.08878.037

DY

TC16

DY

GAP-CLOSE-PW R
G52

1
2
79.3971V.6AL
2ND = 77.93971.02L

79.22719.20L
2ND = 80.2271V.A9L

GAP-CLOSE-PW R
G54
1
2

2008/10/21

GAP-CLOSE-PW R

C623

1D1V_PW RGD

Close to VFB Pin (pin5)

42

TP182TPAD14-GP

24
7

U41

1D2V_PW RGD

1
6

C654
SC1U10V2KX-1GP

1D1V_PW RGD

2
5

1D2V_PW R
1D1V_PW R
51124_VFB2
51124_VFB1

1D2V_PW R

1
2

SCD1U16V2KX-3GP
51124_V5FILT

TC19

DY
2

C682
SCD1U10V2KX-4GP

2
1

DY

R328
30KR2F-GP

GAP-CLOSE-PW R
G69
1
2
GAP-CLOSE-PW R
G70
1
2
TC18
GAP-CLOSE-PW R
SE390U2D5VM-2GP
G73
1
2

GAP-CLOSE-PW R
79.3971V.6AL
G71
2ND = 77.93971.02L

79.22719.20L
2ND = 80.2271V.A9L

84.04812.A37
2ND = 84.08878.037

DY

51124_VFB2

C657
SC18P50V2JN-1-GP

5
6
7
8

R329
17K8R2F-GP

D
D
D
D

U42

G
S
S
S

10KR2J-3-GP

51124_VBST2

R326
0R2J-2-GP

GAP-CLOSE-PW R
G68
1
2

1D2V Iomax=5A
OCP>10A

4
3
2
1

C661
1

DY

SI4812BDY-T1-E3-GP

DY R323

51124_VBST1

SCD1U16V2KX-3GP
51124_LL2

C641
1

GAP-CLOSE-PW R
G67
1
2

SE220U2VDM-8GP

68.1R510.10K
2ND = 68.1R510.10Y

2008/12/18
51124_LL1

1
5
6
7
8

L37
1
2
IND-1D5UH-23-GP

1D2V_S0
G66

1D2V_PW R

R332
9K1R2F-1-GP

C666

R317
5K6R2F-2-GP

C665

51124_TRIP1
51124_TRIP2

U45
SI4800BDY-T1

84.04800.D37
2ND = 84.08884.037

C664

S
S
S
G

TPS51124RGER-GPU1

74.51124.073
51124_TONSEL

DY

DRVH2
LL2
DRVL2

51124_DRVH2
51124_LL2
51124_DRVL2

10
11
12

4
3
2
1

BC4
SCD47U6D3V2KX-GP

DCBATOUT_51124

17
14

1
2

20080307_Modify by
Brian

D
D
D
D

1
2
R335 0R2J-2-GP

PGOOD1
PGOOD2

GND
GND
PGND2
PGND1

TONSEL

3
25
13
18

51124_DRVH1
51124_LL1
51124_DRVL1

21
20
19

ACOUSTIC NIOSE

EN1
EN2

VBST1
VBST2

23
8

VO1
VO2

VFB1
VFB2
51124_EN1
51124_EN2

DRVH1
LL1
DRVL1

SCD1U25V3KX-GP

V5FILT
V5IN

SC10U25V6KX-1GP

15
16

SC10U25V6KX-1GP

51124_V5FILT

22
9

DY

TRIP1
TRIP2

BC3
SC1U10V2KX-1GP

2008/11/13
VCORE_EN

DY

2
1

SC180P50V2JN-1GP

C636 1

R299 DY
2
1
10KR2J-3-GP

R327
2R3J-GP

SC4D7U6D3V3KX-GP

3RD = 79.10112.3JL

C650

51124_VFB1

G
S
S
S

10KR2J-3-GP

10KR2J-3-GP

42,45 VCORE_EN

R319
18KR2F-GP

4
3
2
1

R313

R334

GAP-CLOSE-PW R
G53
1
2
SE220U2VDM-8GP

5V_S5

U40

SCD1U10V2KX-4GP

3D3V_S0
GAP-CLOSE-PW R

79.10712.L02
2ND = 79.10712.6JL

42,45

3D3V_S0

1D1V_PW R

C647

68.1R01A.20B
2ND = 68.1R10A.10S

1
2
R333 0R2J-2-GP

SI4812BDY-T1-E3-GP

GAP-CLOSE-PW R
G48
1
2

Vo(cal)=1.1060V

L32
1
2
COIL-1UH-34-GP-U

TC21
SE100U25VM-L1-GP

Vtrip(mV)=Rtrip(Kohm)*10(uA)
Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))

SC18P50V2JN-1-GP

GAP-CLOSE-PW R
G47
1
2

GAP-CLOSE-PW R
G58
1
2

4
3
2
1

GAP-CLOSE-PW R

1
2

SI4800BDY-T1

GAP-CLOSE-PW R
G56
1
2

C635
SCD1U25V3KX-GP

U37

C634

D
D
D
D

GAP-CLOSE-PW R
G65
1
2

C633

SC10U25V6KX-1GP

SC10U25V6KX-1GP

GAP-CLOSE-PW R
G64
1
2

5
6
7
8

TC15

79.10712.L02
2ND = 79.10712.6JL

1D1V_S0

DCBATOUT_51124_1

1
SE100U25VM-L1-GP

2008/10/21

GAP-CLOSE-PW R
G72
1
2
GAP-CLOSE-PW R

TONSEL

GND

OPEN

V5FILT

240k/CH1
300k/CH2

300k/CH1
360k/CH2

360k/CH1
420k/CH2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Vout=0.758V*(R1+R2)/R2 --> PWM mode

Vout=0.764V*(R1+R2)/R2 --> Skip Mode

Title

TPS51124_1D1V_1D2V
Size

Document Number

A3
Date:
5

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

47

of

61

DCBATOUT_51117

DCBATOUT_51117

U61

79.10712.L02
2ND = 79.10712.6JL

GAP-CLOSE-PW R

GAP-CLOSE-PW R

5
14

VFB
VBST

0R2J-2-GP
1 R467
251117A_EN
1
1 R466
2 51117A_TON 2
51117A_TRIP 11
249KR2F-GP

EN_PSV
TON
TRIP

13
9

51117A_DRVH
51117A_DRVL

LL

12

51117A_LL

VOUT
PGOOD
GND
PGND
GND

3
6
7
8
15

TC33

DY

TC32
SE390U2D5VM-2GP

79.3971V.6AL
2ND = 77.93971.02L

1
1
2
2

DY

SE390U2D5VM-2GP

79.3971V.6AL
2ND = 77.93971.02L

R464
21KR2F-GP

4
3
2
1

DRVH
DRVL

C903

Vo(cal)=1.8214V
1D8V Iomax=10A
OCP>15A

51117A_VFB

V5FILT
V5DRV

C849

DY

51117A_VFB

84.04812.A37
2ND = 84.08878.037

U57

4
10

12,34,36 PM_SLP_S5#

R465
30KR2F-GP

2008/10/21
1D8V_PW R

1D8V_PW R
R468
200KR2J-L1-GP

TPS51117RGYR-GP
R481
15K8R2F-GP

Vout=0.75*(R1+R2)/R2

3D3V_S5

3RD = 83.5R003.08F

5
6
7
8

2008/10/29

51117A_VBST
C

68.1R510.10J

U60
SI4812BDY-T1-E3-GP

C850

SC1U10V2KX-1GP
2
1

SCD1U25V3KX-GP

SCD1U10V2KX-4GP

51117A_V5FILT

SC18P50V2JN-1-GP

C861
2
1

4
3
2
1
1
1

L54
1
2
IND-1D5UH-34-GP

R469
300R3F-GP

2ND = 83.R5003.H8H

1D8V_PW R

2ND = 68.1R51A.10G

S
S
S
G

D29
CH551H-30PT-GP
83.R5003.C8F

Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A

D
D
D
D

5V_S5

84.04800.D37
2ND = 84.08884.037

S
S
S
G

C862
SC1U10V2KX-1GP

C868

SI4800BDY-T1

3RD = 79.10112.3JL

5V_S5

C867

C863

GAP-CLOSE-PW R
G96
1
2

GAP-CLOSE-PW R
G95
1
2

SCD1U25V3KX-GP

GAP-CLOSE-PW R
G93
1
2

D
D
D
D

GAP-CLOSE-PW R
G94
1
2

5
6
7
8

SC10U25V6KX-1GP

DCBATOUT

G91

SC10U25V6KX-1GP

TC31

SE100U25VM-L1-GP

G92

DCBATOUT

1D8V_S3

1D8V_PW R

G99

1D8V_S3_PW RGD 42

2008/12/17

G103

GAP-CLOSE-PW R
G100
1
2

GAP-CLOSE-PW R
G104
1
2

GAP-CLOSE-PW R
G109
1
2

GAP-CLOSE-PW R
G107
1
2

GAP-CLOSE-PW R
G101
1
2

GAP-CLOSE-PW R
G105
1
2

GAP-CLOSE-PW R
G102
1
2

GAP-CLOSE-PW R
G108
1
2

GAP-CLOSE-PW R

GAP-CLOSE-PW R

DDR_0.9V
B

C548
SC10U10V5KX-2GP

DDR_VREF_PW R
C545
G32
SCD1U10V2KX-4GP
1
2

C547
SC1U16V3KX-2GP

Iomax=1.5A
OCP>3A

1D8V_S3

5V_S5

GAP-CLOSE-PW R
G33
1
2

U27

RT9026PFP-GP

1
C535
SC10U10V5KX-2GP

GAP-CLOSE-PW R

C542
SCD1U10V2KX-4GP

GAP-CLOSE-PW R
G34
1
2

1
2
3
4
5

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
GND

10
9
8
7
6

DDR_VREF_S3

9026_S5
2 R249
1
0R0402-PAD
9026_S3
2 R247
1
0R0402-PAD

11

12,34,36 PM_SLP_S5#

0D9V_S3

C544
SC10U10V5KX-2GP

<Core Design>

74.09026.079
2ND = 74.02997.A79

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

DCDC_1D8V_TPS51117/LDO 0D9V
Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

48

of

61

1D5V_S0
Iomax=1A

G957

1D5V_S0_LDO

1D5V_S0
G111

2008/12/12 SB

C918

GAP-CLOSE-PW R-3-GP
G110
1
2

DY

SC10U6D3V5KX-1GP

U66

GAP-CLOSE-PW R-3-GP

DY

3D3V_S0

3
2
1

VOUT
GND
VIN
G957T65UF-GP

DY

74.95765.03C

C913
SC1U10V3KX-3GP

DY

1D2V_S5
Iomax=400mA

For MINI Card.NEW Card power SW

3D3V_S5

1D2V_S5

3D3V_S0

2D5V_LDO

U47
G74

3
2
1

1
1

VOUT
VIN
GND

Place near to SB700

74.09161.E3C

DY

1
2

IN
GND
OUT

1
2
3

1
2

G9161-120U65U-GP

2D5V
Iomax=0.2A

C411
SC10U6D3V5KX-1GP

C412

U18

SC10U6D3V5KX-1GP

DY

SC10U10V5KX-2GP

SC1U10V3KX-3GP

C413
C410

2D5V_S0

GAP-CLOSE-PW R-3-GP
C761

1D8V_S3

C803
SC1U16V3ZY-GP

Iomax=0.8A

1
C819
SC10U10V5ZY-1GP

C820
SC10U10V5ZY-1GP

Place near to CPU

5V_S5

DY

SC22U6D3V5MX-2GP

SC1U10V3ZY-6GP

C782
RT9161-A-25PG-GP

DIS
DIS
1D1V_M92_PW R

RT9025-25PSP-GP
R446
2K2R2J-2-GP

74.09025.03D
2ND = 74.0G966.03D

DIS

DIS

R420
20KR2F-L-GP

DIS

DY

C771

GAP-CLOSE-PW R
G86
1
2
GAP-CLOSE-PW R

<Core Design>

Wistron Corporation

9025_FB

C776

1
2

DIS

DIS

C775
R421
8K25R2F-1-GP

5
6
7
8

SC10U10V5ZY-1GP

NC#5
VOUT
ADJ
GND

SC10U10V5ZY-1GP

3D3V_S0

VDD
VIN
EN
PGOOD

G85

SC100P50V2JN-3GP

4
3
2
1

DIS
1

PM_SLP_S3#

GND

12,34,35,36,42,44,60

U48

1D1V_M92
PM_SLP_S3#

R447
2
19025_EN
0R0402-PAD

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

9025_POK

Vo=0.8*(1+(R1/R2))

Title
Size
A3
Date:

LDO 2D5V/1D5V/1D2V_S5

Document Number

JV50-PU

Friday, December 19, 2008

Rev

SB
Sheet
1

49

of

61

2008/12/18

2
AD+

36,51

BAT_SDA

PHASE

23

ISL88731_LX

L31

ISL88731_LX

PGND

19

CSOP

18

CSON

17

IND-10UH-119-GP

ISL88731_DLO

1
8

ICM
ISL88731_CSIN

2008/12/18

VCOMP
NC#5
ICOMP
VREF
NC#7
GND

NC#16

16

VFB

15

C567
SCD22U50V3ZY-1GP

84.04800.D37
2ND = 84.08884.037

2008/11/04
1

D
D
D
D

U33
SI4800BDY-T1

10R2F-L-GP

D01R2512F-4-GP

R275

GND

6
5
4
3
7
12

PBATT_SENSE_R

BATT_SENSE

51

100R2J-2-GP
ISL88731AHRZ-T-GP

74.88731.B73

29

C562
SCD1U25V2ZY-1GP

DY

DY
2

1
2

C569
SC1U10V3KX-3GP

SCD015U25V2KX-GP

C566
2
1

C565
SCD01U50V2ZY-1GP

DY
2

1ISL88731_CCV1
2

ISL88731_CCV

2
10KR2F-2-GP

ISL88731_CCS
C564
SCD01U50V2KX-1GP

DY
2

10KR2J-3-GP

R267

SCD01U16V2KX-3GP
2
1
C560

1KR2F-3-GP
R274
1

ISL88731_CSIP

AD_IA

ISL88731_IINP

G
S
S
S

36

CHG_AGND

R272

R276
ISL88731_CSIP_R

2008/11/17

NC#14

4
3
2
1

14

R278

5
6
7
8

20

C619

BT+

2008/11/04

68.1001B.10S

LGATE

2008/11/13

SC1U10V3KX-4GP

1
2
C575
SCD1U50V3KX-GP

1
2

G50
GAP-CLOSE-PWR-2U

D
D
D
D

5
6
7
8

G
S
S
S

ISL88731_DHI

SDA

24

UGATE

C563
SC10U25V6KX-1GP

10

C595

C15
SC10U25V6KX-1GP
2
1

BAT_SCL

BAT54PT-GP

C13
SC10U25V6KX-1GP
2
1

SCL

36,51

C568
SC10U25V6KX-1GP
2
1

ACOK

84.04800.D37
2ND = 84.08884.037

DY

13

25
21

U36
CHG_AGND
SI4800BDY-T1

CHG_AGND

BOOT
VDDP

D15

ISL88731_ACOK

CHG_AGND

R285
4D7R3F-L-GP
2

ISL88731_CSSN_R
ISL88731_VCC
R284
0R3-0-U-GP
ISL88731_BST 1
2ISL88731_BST1
ISL88731_LDO

CHRG_IN
C576
SC1U10V3KX-3GP

VDDSMB

27
26

C561
SCD1U10V2KX-4GP

CSSN
VCC

CHG_AGND

4
3
2
1

11

5V_S5

1
2

C571
SCD01U50V2KX-1GP

ACIN

28

G61
GAP-CLOSE-PWR-2U
2
1

2
1
2

CSSP

C23

SCD1U25V3KX-GP

DCIN

2008/11/04

SC10U25V6KX-1GP

ISL88731_ACIN

22

84.04433.A37
2ND = 84.04407.F37

R293
470KR2J-2-GP

SC10U25V6KX-1GP

U32

2
SCD047U25V3KX-GP C577

ISL88731_CSSP

CHG_AGND

R277
215KR3F-1-GP

R279
49K9R2F-L-GP

SC1U25V5KX-1GP

NC#1

2008/10/20

C573

1
SCD1U25V3KX-GP

C572

CH521S-30PT-GP-U

C574
ISL88731_ACOK

83.R2003.C8F
2ND = 83.R2003.F8F D14
A
3RD = 83.R2003.J8F

SCD1U25V3KX-GP

R261 1
10KR2F-2-GP

R286
10R2J-2-GP

G60
GAP-CLOSE-PWR-2U
2
1

1
R287
10R2J-2-GP

2ND = 84.27002.G3F

Q15
84.27002.F3F
2N7002EDW -GP

8
7
6
5

AO4433-GP

G62
GAP-CLOSE-PWR-2U
2
1

100KR2J-1-GP

10KR2J-3-GP

G43
GAP-CLOSE-PWR-2U

R259

1ISL88731_CSSN
1
2

D
D
D
D

SCD1U25V3KX-GP

84.04433.A37
2ND = 84.04407.F37

AD+_G_1

G42
GAP-CLOSE-PWR-2U

D01R2512F-4-GP
R260

AO4433-GP

BT+

U34
S
S
S
G

1
2
3
4

DCBATOUT
R262
1

AD+_TO_SYS

1
2
3
4

U30
S
S
S
G

D
D
D
D

GAP-CLOSE-PWR-2U
G45
1
2

2008/12/18
8
7
6
5

C620

AD+

C626

G46
GAP-CLOSE-PWR-2U

20081008
1
2
G44
GAP-CLOSE-PW R-2U

2008/11/04

CHG_AGND

3D3V_AUX_S5

R270
10KR2F-2-GP ISL88731_LDO

AC_IN#

AC_IN#

R268
10KR2F-2-GP

36

Q18
2N7002-11-GP

R269

ISL88731_ACOK

<Core Design>

0R2J-2-GP
R266
15KR2J-1-GP

84.27002.W31
2ND = 84.27002.Y31

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2008/11/17
Title

ISL88731A Charger
Size
A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

50

of

61

2008/11/06
2008/10/29
4

AD_JK

Adaptor in to generate DCBATOUT

GND

2008/12/18

AD_JK

22.10037.G11

K
C556
SCD1U50V3ZY-GP

D9

AD+_2

P6SBMJ24APT-GP

83.P6SBM.AAG

1
2
3
4

R256
200KR2F-L-GP

U29
S
S
S
G

D
D
D
D

8
7
6
5

AO4433-GP

DC-JACK150-GP

DY

AD+

EC59
SCD1U50V3KX-GP

6
5
4
1
2
3
NP1

DCIN1

84.04433.A37
2ND = 84.04407.F37

C557
SC1U50V5ZY-1-GP

R2
R1

2
3
1

Q13
AD_OFF#_JK

DTA124EUB-GP

Q12
AFTE14P-GP
AFTE14P-GP

1
1

36

2
R2
DTC124EUB-GP

AD_OFF

R255
100KR2J-1-GP

84.00124.T1K
2ND = 84.00124.N1K
3RD = 84.00124.K1K

R1

84.00124.S1K
2ND = 84.00124.M1K
3RD = 84.00124.H1K

TP8
TP7

AD_JK
AD_JK

R257
1KR2F-3-GP

BATTERY CONNECTOR

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
BT+
BT+

D12
BAV99PT-GP-U

DY

D11
DY
BAV99PT-GP-U

83.00099.K11 83.00099.K11
83.00099.K11
2ND = 83.00099.M11
2ND = 83.00099.M11
2ND = 83.00099.M11

DY

RN76

1
2
3
4

36,50
36,50

BAT_SDA
BAT_SCL

8
7
6
5

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1

SRN33J-7-GP

50

EC14

BATT_SENSE

DY
2

1
2

1
2

1
2

K
A

DY EC19

DY EC13
SC10P50V2JN-4GP

DY EC16

SC10P50V2JN-4GP

EC18
SCD1U50V3ZY-GP

SC1000P50V3JN-GP

83.5R603.E3F
3RD = 83.5R603.D3F

DY

SC1000P50V3JN-GP

EC17
SCD1U50V3ZY-GP
D13
MM3Z5V6T1G-GP

BT+

BAT_IN#

36

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

1
1
1
1
1

TP9
TP10
TP11
TP13
TP12

BAT1

9
8
7
6
5
4
3
2
1

D10
BAV99PT-GP-U

3D3V_AUX_S5

GND
GND
GND
GND
DAT
CLK
BAT_IN
BT+2
BT+1

ALP-CON7-9-GP

20.81094.007

2008/11/10
2008/11/15

R8
1
2
0R0402-PAD

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

AD/BATT CONN

Document Number

Rev

SB

JV50-PU
Date:
A

Friday, December 19, 2008

Sheet
E

51

of

61

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

EC103

DY

EC102

DY

1
2

1
2

1
2

1
2

1
2

1
2

1
2

EC101

DY

SCD1U25V2ZY-1GP

EC55

DY

2008/12/18

SCD1U25V2ZY-1GP

14
7
1

EC100

DY

SCD1U25V2ZY-1GP

EC736

DY

SC1KP50V2KX-1GP

EC99

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

EC735

DY

SC1KP50V2KX-1GP

EC734

DY

SC1KP50V2KX-1GP

EC54

DY

SCD1U25V2ZY-1GP

DY

1D1V_S0

2008/11/12

SCD1U25V2ZY-1GP

EC733

DY

SC1KP50V2KX-1GP

EC732

DY

SC1KP50V2KX-1GP

EC53
SCD1U25V2ZY-1GP

EC731

DY

SC1KP50V2KX-1GP

EC52
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

EC730

DY

SC1KP50V2KX-1GP

EC15

SC1KP50V2KX-1GP

2008/11/12

DY

EC729

DY

SC1KP50V2KX-1GP

EC21

DY

EC728

DY

SC1KP50V2KX-1GP

EC37
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

EC727

DY

SC1KP50V2KX-1GP

EC25

DY

EC726

DY

SC1KP50V2KX-1GP

EC46
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

EC725

DY

SC1KP50V2KX-1GP

EC20

DY

EC724

DY

5V_S5

3D3V_S0

BT+

EC12

DY

EC723

DY

SC1KP50V2KX-1GP

EC10

DY

EC722

DY

SC1KP50V2KX-1GP

EC9

DY

EC721

DY

SC1KP50V2KX-1GP

EC8

DY

EC720

DY

SC1KP50V2KX-1GP

EC7

DY

EC719

DY

SC1KP50V2KX-1GP

TSLVC08APW -1-GP

73.07408.L16
2ND = 73.07408.L15
3RD = 73.07408.02B

EC718

DY

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

11
13

EC717

DY

SC1KP50V2KX-1GP

DY

U16D

12

DCBATOUT

2008/12/17
EC716

1D8V_S0

3D3V_S5

1D8V_S3
VCC_CORE_S0_0

2008/12/17

2008/11/13
1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

DY

2008/11/10

2008/11/10

34.49U26.001

34.41Y19.001

34.41Y19.001

34.41Y19.001

34.41Y19.001

34.41Y19.001

DY

DY

DY

DY

DY

DY

SPRING_GND21
SPRING-7

SPRING_GND22
SPRING-7

ASPRING_GND20
SPRING-12-GP-U

ASPRING_GND19
SPRING-12-GP-U

ASPRING_GND18
SPRING-12-GP-U

SPRING_GND17
SPRING-12-GP-U

DY

2008/11/10

ASPRING_GND16
SPRING-12-GP-U

34.43G01.002

GND11
SPRING-48-GP

34.43G01.002

GND10
SPRING-48-GP

34.43G01.002

GND6
GND7
GND12
GND9
HOLE355X355R111-S1-GPHOLE355X355R111-S1-GPHOLE355X355R111-S1-GPHOLE355X355R111-S1-GP
GND5
SPRING-48-GP

2008/11/10

EC715

DY

SC1KP50V2KX-1GP

EC714

DY

SC1KP50V2KX-1GP

EC713

DY

SC1KP50V2KX-1GP

DY

SC1KP50V2KX-1GP

EC711 EC712

DY

SC1KP50V2KX-1GP

DY

EC710

DY

SC1KP50V2KX-1GP

34.49U26.001

EC709

DY

SC1KP50V2KX-1GP

SPRING_GND15
SPRING-7

EC708

DY

DY

SPRING_GND14
SPRING-7

EC707

DY

SC1KP50V2KX-1GP

EC706

DY

SC1KP50V2KX-1GP

EC705

DY

SC1KP50V2KX-1GP

EC704

DY

SC1KP50V2KX-1GP

EC703

DY

SC1KP50V2KX-1GP

DY

SC1KP50V2KX-1GP

DY

EC702
SC1KP50V2KX-1GP

GND4
HOLE355X355R111-S1-GP

DY

DY

EC38
SCD1U25V2ZY-1GP

GND1
GND2
GND3
HOLE355X355R111-S1-GPHOLE355X355R111-S1-GPHOLE355X355R111-S1-GP

EC35
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

H9
HOLE

EC33

SC1KP50V2KX-1GP

EC701

DY

DY

2008/10/27

2008/12/18

2008/12/18

ASPRING_GND22
SPRING-58-GP

ASPRING_GND21
SPRING-62-GP

SB

-1

SA
DY

2008/11/12

TOP

TOP

Check test point

BOT

3D3V_S0

CPU

VGA

NB

AH1
HOLE

AH2
HOLE

AH3
HOLE

AH4
HOLE

AH5
HOLE

AH6
HOLE

TP233

TPAD14-GP

TP232

TPAD14-GP

3D3V_S5

TP231

TPAD14-GP

5V_S5

TP230

TPAD14-GP

12,36 PM_PW RBTN#

TP229

TPAD14-GP

6,11

CPU_PW RGD

TP228

TPAD14-GP

S5_ENABLE

TP227

TPAD14-GP

6,11 CPU_LDT_RST#

TP226

TPAD14-GP

MINI1

MDC
H7
HOLE

H10
HOLE

3D3V_AUX_S5

H8
HOLE

2008/10/27

DY

34.4P901.001

34.42Y01.011

34.4Z003.001

34.4Z003.001

34.4Z003.001

34.4Z003.001

34.4Z003.001

34.4Z003.001

35,36

Test Point
Dimm Door

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:

EMI/Spring/Boss
Document Number

Rev

JV50-PU

Friday, December 19, 2008

SB
Sheet
1

52

of

61

1 OF 8

AVGA1A

PEG_TXP0
PEG_TXN0

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

PEG_RXP0_1
PEG_RXN0_1

Y33
Y32

C222

1
2
SCD1U16V2KX-3GP
1
C231 SCD1U16V2KX-3GP

DIS

PEG_TXP1
PEG_TXN1

Y35
W36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33
W32

PEG_RXP1_1
PEG_RXN1_1

C226

PEG_TXP2
PEG_TXN2

W38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PEG_RXP2_1
PEG_RXN2_1

C257

PEG_TXP3
PEG_TXN3

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30
U29

PEG_RXP3_1
PEG_RXN3_1

C268
1
2
SCD1U16V2KX-3GP
1
C248 SCD1U16V2KX-3GP

1
2
SCD1U16V2KX-3GP
1
C233 SCD1U16V2KX-3GP

DIS

1
2
SCD1U16V2KX-3GP
1
C238 SCD1U16V2KX-3GP

DIS

DIS

U38
T37

PEG_TXP5
PEG_TXN5

T35
R36

PEG_TXP6
PEG_TXN6

R38
P37

PEG_TXP7
PEG_TXN7

P35
N36

PEG_TXP8
PEG_TXN8

N38
M37

PEG_TXP9
PEG_TXN9

M35
L36

PEG_TXP10
PEG_TXN10

L38
K37

PEG_TXP11
PEG_TXN11

K35
J36

PEG_TXP12
PEG_TXN12

J38
H37

PEG_TXP13
PEG_TXN13

H35
G36

PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N

PCI EXPRESS INTERFACE

PEG_TXP4
PEG_TXN4

PCIE_TX4P
PCIE_TX4N

PEG_RXP4_1
PEG_RXN4_1

T33
T32

C278
1
2
SCD1U16V2KX-3GP
1
C273 SCD1U16V2KX-3GP

DIS

PCIE_TX5P
PCIE_TX5N

PEG_RXP5_1
PEG_RXN5_1

T30
T29

C287
1
2
SCD1U16V2KX-3GP
1
C279 SCD1U16V2KX-3GP

DIS

PCIE_TX6P
PCIE_TX6N

PEG_RXP6_1
PEG_RXN6_1

P33
P32

C289
1
2
SCD1U16V2KX-3GP
1
C294 SCD1U16V2KX-3GP

DIS

PCIE_TX7P
PCIE_TX7N

PEG_RXP7_1
PEG_RXN7_1

P30
P29

C307
1
2
SCD1U16V2KX-3GP
1
C299 SCD1U16V2KX-3GP

DIS

PCIE_TX8P
PCIE_TX8N

PEG_RXP8_1
PEG_RXN8_1

N33
N32

C301
1
2
SCD1U16V2KX-3GP
1
C309 SCD1U16V2KX-3GP

DIS

PCIE_TX9P
PCIE_TX9N

PEG_RXP9_1
PEG_RXN9_1

N30
N29

C319

1
2
SCD1U16V2KX-3GP
1
C328 SCD1U16V2KX-3GP

DIS

PCIE_TX10P
PCIE_TX10N

L33
L32

PEG_RXP10_1
PEG_RXN10_1

C303

1
2
SCD1U16V2KX-3GP
1
C292 SCD1U16V2KX-3GP

DIS

PCIE_TX11P
PCIE_TX11N

L30
L29

PEG_RXP11_1
PEG_RXN11_1

C333
1
2
SCD1U16V2KX-3GP
1
C344 SCD1U16V2KX-3GP

DIS

PCIE_TX12P
PCIE_TX12N

K33
K32

PEG_RXP12_1
PEG_RXN12_1

C314
1
2
SCD1U16V2KX-3GP
1
C322 SCD1U16V2KX-3GP

DIS

PCIE_TX13P
PCIE_TX13N

J33
J32

PEG_RXP13_1
PEG_RXN13_1

C343
1
2
SCD1U16V2KX-3GP
1
C332 SCD1U16V2KX-3GP

DIS

PEG_TXP14
PEG_TXN14

PEG_RXN[15..0]

8 PEG_RXN[15..0]

PEG_TXN[15..0]

8 PEG_TXN[15..0]

PEG_RXP[15..0]

8 PEG_RXP[15..0]

PEG_TXP[15..0]

8 PEG_TXP[15..0]
D

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

PEG_RXP14_1
PEG_RXN14_1

C353
1
2
SCD1U16V2KX-3GP
1
C360 SCD1U16V2KX-3GP

DIS

PEG_TXP15
PEG_TXN15

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

PEG_RXP15_1
PEG_RXN15_1

C352
1
2
SCD1U16V2KX-3GP
1
C359 SCD1U16V2KX-3GP

DIS

PEG_RXP0
PEG_RXN0

DIS

PEG_RXP1
PEG_RXN1

DIS

PEG_RXP2
PEG_RXN2

DIS

PEG_RXP3
PEG_RXN3

DIS

PEG_RXP4
PEG_RXN4

DIS

PEG_RXP5
PEG_RXN5

DIS

PEG_RXP6
PEG_RXN6

DIS

PEG_RXP7
PEG_RXN7

DIS

DIS

PEG_RXP9
PEG_RXN9

DIS
2

DIS
2

DIS
2

DIS
2

DIS
2

PEG_RXP8
PEG_RXN8

DIS

PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14

PEG_RXP15
PEG_RXN15

DIS

CLOCK

AB35
AA36

3 CLK_PCIE_PEG
3 CLK_PCIE_PEG#

PCIE_REFCLKP
PCIE_REFCLKN

1D1V_M92
CALIBRATION

AJ21
AK21
AH16

NC#AJ21
NC#AK21
NC_PWRGOOD

R89

PCIE_CALRP

Y30

PCIE_CALRN

Y29

1
R99

11,32,33,34,37 PLT_RST1#_B

PLT_RST1#_M92_1

1
2
R423 0R2J-2-GP
1

DIS

1K27R2F-L-GP

2
2

2KR3F-L-GP

DIS

PERST#
M92-M2-GP

DIS

DY

C780
SC47P50V2JN-3GP

AA30

DIS

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

M92 PCIE
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

53

of

61

TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC

TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N

DPD

1D8V_S0

HPD1

4
3
LVDS_TXAOUT0+ 19
LVDS_TXAOUT0- 19

AR37
AU39

LVDS_TXAOUT1+ 19
LVDS_TXAOUT1- 19

AP35
AR35

LVDS_TXAOUT2+ 19
LVDS_TXAOUT2- 19

8
7
6
5

M92-M2-GP
CRT_RED

AT23
AR22

DIS

CRT_GREEN

CRT_RED 20

AE36
AD35

CRT_GREEN

AF37
AE38

CRT_BLUE 20

AC36
AC38

CRT_HSYNC
CRT_VSYNC

C
Y
COMP
H2SYNC
V2SYNC

1
2
3
4

AVSSQ

20,57
20,57

499R2F-2-GP
DAC2_VDD2DI

AD30
AD31

DIS

DIS

DIS

DAC2_A2VDD

AF30
AF31

3D3V_M92
R70
1

AC32
AD32
AF32

DIS

AD29
AC29

DIS

DIS

100mA
AG31
AG32

DIS

DIS

AVSSQ

DIS

1D8V_S0
L17

DIS

DIS

DIS

C204

1
2
BLM15BD121SN1D-GP

DIS

DAC2_VDD2DI
DAC2_A2VDDQ

1D8V_S0

130mA
AG33

2mA

A2VDDQ
VREFG
A2VSSQ

C152
SCD1U16V2KX-3GP

DAC2_A2VDDQ

DIS

AF33

DIS

AA29

R418
1
2
715R2F-GP

DIS

3D3V_M92

1
2
BLM15BD121SN1D-GP

DIS

DIS
2

R2SET

AD33

L19

DAC2_A2VDD

A2VDD

1
2
BLM15BD121SN1D-GP

DAC1_VDD1DI

0R2J-2-GP
2

DIS

C156

DIS

DIS

C187

DIS

1D8V_S0
L14

AVSSQ

AC30
AC31

DAC1_AVDD

0R2J-2-GP
2

DIS

C184
SC1U6D3V2KX-GP

DAC1_VDD1DI

1D8V_S0
R52
1

AVSSQ

100mA

2
DAC1_AVDD

DIS

C183
SCD1U16V2KX-3GP

65mA

B2
B2#

0R2J-2-GP

DIS

G2
G2#

R80

AC33
AC34

R2
R2#

DIS

2008/12/17
2008/12/18

AD34
AE34

RN86
SRN150F-1-GP

20

VDD1DI
VSS1DI

AB34

8
7
6
5

AD39
AD37

R82
RSET
AVDD
AVSSQ

HPD1

AH13

1
2

AN36
AP37

LVDS_TXACLK+ 19
LVDS_TXACLK- 19

AW37
AU35

C182
SCD1U16V2KX-3GP

HSYNC
VSYNC

DIS

AP34
AR34

2008/11/12

AU22
AV21

B
B#

= 0.6V)
VGA_VREFG

R69
249R2F-GP
DIS

TXOUT_L3P
TXOUT_L3N

G
G#

VREFG VOLTAGE DIVIDER IS

(VREFG = VDDR4,5(1.8V) / 3

84.2N702.D31
2ND = 84.2N702.I31

DIS

DIS

R324
100KR2F-L1-GP

AT21
AR20

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

R
R#

VDD2DI
VSS2DI

R73
499R2F-2-GP

LVDS_TXBOUT2+ 19
LVDS_TXBOUT2- 19

R212 1

CLK_27M_M92

0R0402-PAD
2

DPLL_PVDD
DPLL_PVSS

AN31

AUX1P
AUX1N

XTALIN
XTALOUT

DPLL_VDDC

AV33
AU34

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

2008/12/17
2008/12/17

AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N

2008/12/17

For Thermal sensor

THERMAL

DDCCLK_AUX5P
DDCDATA_AUX5N

AK32
AJ32
AJ33

TS_FDO
TSVDD
TSVSS

DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

R360
1MR2J-1-GP

DIS

SMBC_Therm
SMBD_Therm

DIS
DIS

2 0R2J-2-GP
2 0R2J-2-GP

SMBC_G781
8
SMBD_G781
7
ALERT#_G781 6
5

21
21

1
2
3
4

SMBCLK
VCC
SMBDATA
DXP
ALERT#
DXN
GND
THERM#

GPU_DPLUS
GPU_DMINUS

DIS G781P8F-GP

AN20
AM20
AL30
AM30

DIS

AN21
AM21

DIS

AJ30
AJ31

Q21
MMBT3904-4-GP

AK30
AK29

HPD1

HDMI_A_HPD

21

3D3V_M92

2008/11/07

84.T3904.C11
2ND = 84.03904.L06

M92-M2-GP

DIS

M92

R325
10KR2J-3-GP

Wistron Corporation

DIS

2008/12/17 SB

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

DIS
82.30034.421

DIS

XTAL-27MHZ-54-GP
2

C678
SC22P50V2JN-4GP

Title

M92 IO

C689
SC22P50V2JN-4GP
Size
A2

DIS

Date:
5

RN75
SRN2K2J-1-GP

3D3V_M92

AL29
AM29

X6
3

R2711
R2731

DIS
2

DIS
2

BLM15BD121SN1D-GP

FAN_PWM
TSVDD

DPLUS
DMINUS

DDCCLK_AUX4P
DDCDATA_AUX4N

HDMI_A_CLK
HDMI_A_DAT

AF29
AG29

35,36
35,36

AM27
AL27
AM19
AL19

C559
SCD1U16V2KX-3GP

U31

20
20

TP77

DIS 220mA
C125
SC1U10V3KX-3GP

C153
SCD1U16V2KX-3GP

L10
1D8V_S0

GPU_DPLUS
GPU_DMINUS

CRT_DDCCLK
CRT_DDCDATA

AM32
AN32

300mA

AM26
AN26

4
3

PLL/CLOCK

120mA
DPLL_VDDC

DDC1CLK
DDC1DATA

1
2

DDC/AUX

DPLL_PVDD

Depending on OSC used select voltage divider resist

values R25 R70 to ensure XTALIN voltage level of
1.8V

RN38
SRN10KJ-11-GP-U

DIS

CRT_BLUE

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG

AK24

BLON_IN 36
LCDVDD_ON 19

AF35
AG36

C221
SCD1U16V2KX-3GP

LVDS_TXBOUT1+ 19
LVDS_TXBOUT1- 19

AG38
AH37

R53
1KR2J-1-GP
2
1

DIS

LVDS_TXBOUT0+ 19
LVDS_TXBOUT0- 19

AH35
AJ36

SC10U6D3V3MX-GP

1
1
1
1
1
1
1
1
1
1
1

TP65
TP73
TP72
TP71
TP85
TP76
TP81
TP74
TP78
TP75
TP82

2N7002E-1-GP
Q22

SC10U6D3V3MX-GP

Back Bias (body bias) which minimizes

power consumption in battery modes.
PD = Disable
PU = Enable

JTAG_TRSTB

LVDS_TXBCLK+ 19
LVDS_TXBCLK- 19

AJ38
AK37

TP184

AK35
AL36

C220
SCD1U16V2KX-3GP

R355 1
DIS 2
10KR2J-3-GP

GPIO_VGA_22

AU20
AT19

57

2008/11/03

AT17
AR16

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

PWRCNTL_1

DIS

60

5V_S0

AU16
AV15

Thermal_int
1
TP66

2008/11/03

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

C201
SC1U6D3V2KX-GP

THERMTRIP_VGA

TP79

2008/11/04

LVTMDP

C118
SCD1U16V2KX-3GP

1
TP64

PWRCNTL_0
DY 1
0R2J-2-GP

TXOUT_U3P
TXOUT_U3N

AT15
AR14

CLK_27M_SSIN

GPIO_VGA_11
GPIO_VGA_12
GPIO_VGA_13

BLON_IN

AK27
AJ27

SC10U6D3V3MX-GP

60
R354 2

GPIO_VGA_08
GPIO_VGA_09

57
57
57

2008/11/10

AU14
AV13

2008/11/03

57
57

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AT33
AU32

Thermal_int

DIS

C202
SCD1U16V2KX-3GP

2008/11/03

DIS

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

RN81
SRN499F-GP

1
TP84

RN82
SRN499F-GP

AV31
AU30
AR32
AT31

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

2008/11/03

C160
SCD1U16V2KX-3GP

TP83
TP80
GPIO_VGA_05

DIS

AR30
AT29

VARY_BL
DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TMDS_A_TX2+ 21
TMDS_A_TX2- 21

57

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

GPIO_VGA_03
GPIO_VGA_04

1
1

C691
SCD1U16V2KX-3GP

TMDS_A_TX1+ 21
TMDS_A_TX1- 21

DIS

GPIO_VGA_00
GPIO_VGA_01
GPIO_VGA_02

DIS

57
57
57

SCL
SDA
GENERAL PURPOSE I/O

R75
10KR2J-3-GP

DIS

C119
SC1U6D3V2KX-GP

AK26
AJ26

19 LCD_EDID_CLK
19 LCD_EDID_DAT

3D3V_M92

TX5P_DPD0P
TX5M_DPD0N

DIS

C693
SCD1U16V2KX-3GP
C690
SCD1U16V2KX-3GP 1
2

I2C

TX2P_DPAP0
TX2P_DPAN0

C159
SC1U6D3V2KX-GP

It's strap for GDDR3-136ball

Need to Clarify

TX4P_DPD1P
TX4M_DPD1N

TX2P_DPAP1
TX2P_DPAN1

AT27
AR26

1
2
3
4

TXCBP_DPB3P
TXCBM_DPB3N

AU26
AV25

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

DVPDATA [3:0]
0100
512MB Hynix-H5PS1G63EFR-20L
(500MHz)
1000
512MB Samsung-K4N1G164QE-HC20
(500MHz)
1100
512MB QIMONDA HYB18T1G161C2F-20 (500MHz)

DIS

DIS

DY

DIS

R374

TX2P_DPA0P
TX2M_DPA0N

DIS

C158
SCD1U16V2KX-3GP

R363 R368 R369

10KR2J-3-GP

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

C695
SCD1U16V2KX-3GP
C692
SCD1U16V2KX-3GP 1
2

LVDS CONTROL

TMDS_A_TX0+ 21
TMDS_A_TX0- 21

C173
SCD1U16V2KX-3GP

2008/10/27

R371 AR8
AU8
AP8
DY
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

DIS

DY

2008/11/04

DVPDATA [3:2:1:0] for VRAM type

selection H/W strap
Should provide VRAM Table for VBios
request

TX1P_DPA1P
TX1M_DPA1N

10KR2J-3-GP
1

MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3

DIS

R370

10KR2J-3-GP
1

DY

R367

10KR2J-3-GP
1

DIS

10KR2J-3-GP
1

DIS

R365

DIS

SCD1U16V2KX-3GP
C126

1
2

SC10U6D3V3MX-GP

DIS

C122

SCD1U16V2KX-3GP
C130
2
1

2
SC1U10V3KX-3GP
C120

8
7
6
5

DPA

DIS

C697
SCD1U16V2KX-3GP
C694
SCD1U16V2KX-3GP 1
2

TMDS_A_TXC+ 21
TMDS_A_TXC- 21

1
2
3
4

1D8V_S0 1D8V_S0

1D8V_S0 1D8V_S0

TX2P_DPAP2
TX2P_DPAN2

DIS

DPLL_VDDC

AT25
AR24

C696
SCD1U16V2KX-3GP 1

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

TX2P_DPAP3
TX2P_DPAN3

2008/11/05

AU24
AV23

TXCAP_DPA3P
TXCAM_DPA3N

2008/11/07

BLM15BD121SN1D-GP

7 OF 8

AVGA1G

2 OF 8

AVGA1B

DIS

DIS

DIS

SCD1U16V2KX-3GP
C147

DIS
2

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DIS

SCD1U16V2KX-3GP
C138

C123

C121

1D1V_M92

Layout notice:
It should be pleace near HDMI connector

DIS 2

BLM15BD121SN1D-GP

L6

DPLL_PVDD

L7
1

1D8V_S0

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

54

of

61

1D8V_S0

C137
SCD1U16V2KX-3GP

DIS

DIS

C133

DIS

SC1U6D3V2KX-GP
C134
2
1

SC10U6D3V3MX-GP

DIS

DIS

1
2

1
2

C246
SC1U6D3V2KX-GP

1
2

C247
SC1U6D3V2KX-GP

1
2

1
2

1
2

C276
SC1U6D3V2KX-GP

1
2

C329
SC1U6D3V2KX-GP

1
2

C283
SC1U6D3V2KX-GP

1
2

C298
SC1U6D3V2KX-GP

1
2

C337
SC1U6D3V2KX-GP

1
2

C321
SC1U6D3V2KX-GP

1
2

1
2

C313
SC1U6D3V2KX-GP

C306
SC1U6D3V2KX-GP

DIS

C234
SC1U6D3V2KX-GP

1
2

DIS

C157
SC1U6D3V2KX-GP
2
1

1
2

DIS

C228
SC1U6D3V2KX-GP

DIS

C223
SC1U6D3V2KX-GP

C270
SCD1U16V2KX-3GP
2
1

1
2

C265
SC1U6D3V2KX-GP

1
2

C210
SC1U6D3V2KX-GP

1
2

C162
SC1U6D3V2KX-GP

C266
SC1U6D3V2KX-GP

C277
SC1U6D3V2KX-GP
2
1

1
2

C267
SC1U6D3V2KX-GP

1
2

C297
SC1U6D3V2KX-GP

C290
SC1U6D3V2KX-GP

DIS

DIS

C185

DIS

C172

DIS

C235

DIS

C208

1
2

1
2

1
2

1
2

1
2

DIS

C209

VCC_GFX_CORE

C300

DIS

C225

DIS

C284

DIS

C355

DIS

DIS

DIS

M92-M2-GP

DIS

DIS

C357

DIS
2

DIS

VCC_GFX_CORE

M15
N13
R12
T12

C190

C304
SC1U6D3V2KX-GP

DIS

SC1U6D3V2KX-GP
C211
2
1

SC1U6D3V2KX-GP
C229
2
1

SPV10

L11

1
2
BLM15BD121SN1D-GP

VDDCI
VDDCI
VDDCI
VDDCI

DIS

SC10U6D3V3MX-GP

VCC_GFX_CORE

ISOLATED
CORE I/O

DIS

BBP
BBP

C189

AA13
Y13

DIS

BACK BIAS

VCC_GFX_CORE

C165

C274
SC1U6D3V2KX-GP

SPVSS

DIS

SPV10

C200

C727
SCD1U16V2KX-3GP

1
2

SC1U6D3V2KX-GP
C726
2
1

DIS

DIS

SC10U6D3V3MX-GP

C729

DIS

NC_SPV18

DIS

C282
SC1U6D3V2KX-GP

AN9
AN10

C296

AM10
SPV10

DIS

SC10U6D3V3MX-GP

PCIE_PVDD

DIS

1
2
BLM15BD121SN1D-GP

DIS

SC10U6D3V3MX-GP

L46

NC_MPV18#1
NC_MPV18#2

DIS

SC10U6D3V3MX-GP

1D8V_S0

PCIE_PVDD

DIS

VCC_GFX_CORE

SC10U6D3V3MX-GP

H7
H8

DIS

PLL
AB37

PCIE_PVDD

DIS

C230
SCD1U16V2KX-3GP

DIS

DIS

C311
DIS
SC1U6D3V2KX-GP

VDDRHB
VSSRHB

DIS

V12
U12

DIS

VDDRHA
VSSRHA

C310
SC1U6D3V2KX-GP

M20
M21

+VDDRHA

C243
SC1U6D3V2KX-GP

C242
SC1U6D3V2KX-GP

1
2

1
DIS 2
BLM15BD121SN1D-GP

DIS

+VDDRHA

L21

DIS

DIS

MEM CLK

N96?
1D8V_S0

DIS

VCC_GFX_CORE

C275
SCD1U16V2KX-3GP

1
2

C168
SCD1U16V2KX-3GP

C167
SC1U6D3V2KX-GP

1
2

C197
SC1U6D3V2KX-GP

2
1

C175
SC1U6D3V2KX-GP
1
2

C149
SC1U6D3V2KX-GP

C191
SC1U6D3V2KX-GP

1
2

C166
SC1U6D3V2KX-GP
1

C272
SC1U6D3V2KX-GP

1
2

C260
SC1U6D3V2KX-GP

1
2

C326
SC1U6D3V2KX-GP

DIS

C350

SC2D2U6D3V2MX-GP

L20
1
2
BLM15BD121SN1D-GP

DIS

SC2D2U6D3V2MX-GP

1D8V_S0

C224

DIS

SC2D2U6D3V2MX-GP

VDDR4
VDDR4
VDDR4
VDDR4

DIS

SC2D2U6D3V2MX-GP

AD12
AF11
AF12
AG11

VDDR5
VDDR5
VDDR5
VDDR5

DIS

SC2D2U6D3V2MX-GP

AF13
AF15
AG13
AG15

DIS

VDDR3
VDDR3
VDDR3
VDDR3

DIS

SC2D2U6D3V2MX-GP

DIS

I/O
AF23
AF24
AG23
AG24

DIS

SC2D2U6D3V2MX-GP

DIS

DIS

DIS

SC2D2U6D3V2MX-GP

DIS

DIS

DIS

DIS

SC2D2U6D3V2MX-GP

DIS

DIS

DIS

VDD_CT
VDD_CT
VDD_CT
VDD_CT

DIS

SC2D2U6D3V2MX-GP

SC10U6D3V3MX-GP

1D8V_S0

C668

DIS

DIS

LEVEL
TRANSLATION
AF26
AF27
AG26
AG27

POWER

SC10U6D3V3MX-GP

3D3V_M92

DIS

C198
SC1U6D3V2KX-GP

VDD_CT

C327

AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28

DIS

L22
1
DIS 2
BLM15BD121SN1D-GP

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

DIS

1D1V_M92

CORE

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

C269
SC1U6D3V2KX-GP

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

DIS

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C216
SC1U6D3V2KX-GP
2
1

1
2

C195
SC1U6D3V2KX-GP
C171
SCD1U16V2KX-3GP

1
1

DIS

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C164
SC1U6D3V2KX-GP

C342
SC1U6D3V2KX-GP
1

DIS

DIS

C188
SCD1U16V2KX-3GP

2
1

DIS

DIS

C325
SC1U6D3V2KX-GP

1
2

C323
SC1U6D3V2KX-GP
1

C336
SCD1U16V2KX-3GP

DIS
2

C318
SCD1U16V2KX-3GP

2
1

DIS

DIS

DIS

C302
SC1U6D3V2KX-GP

C335
SC1U6D3V2KX-GP
1
2

2
1

DIS

DIS

C291
SC1U6D3V2KX-GP

C341
SC1U6D3V2KX-GP
1

C199
SC1U6D3V2KX-GP

DIS

2
2

DIS

C169
SC1U6D3V2KX-GP

C345
SC1U6D3V2KX-GP

C219
SC1U6D3V2KX-GP

1
1

DIS

SC10U6D3V3MX-GP

DIS

1D8V_S0

2
1

C330

DIS

DIS

DIS

SC10U6D3V3MX-GP

DIS

DIS

C334
SC1U6D3V2KX-GP

DIS

C317
SC1U6D3V2KX-GP

C339
SC1U6D3V2KX-GP

PCIE

SC10U6D3V3MX-GP

DIS

MEM I/O

C305
SC1U6D3V2KX-GP

5 OF 8

AVGA1E

1D8V_S0

C245
SCD1U16V2KX-3GP

DIS

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

M92 POWER
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

55

of

61

6 OF 8

AVGA1F

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

AN24
AP24

DPA_VDD10
DPA_VDD10

DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

AP31
AP32

DPA_VDD10

DIS

AP22
AP23

NC_DPD_VDD18#1
NC_DPD_VDD18#2

NC_DPB_VDD18#1
NC_DPB_VDD18#2

AN27
AP27
AP28
AW24
AW26

DIS

AN17
AP16
AP17
AW14
AW16

1D1V_M92

DIS

L8
1
2
BLM18PG300SN-GP
C124

DIS

SC10U6D3V3MX-GP

2008/10/27

DPC_VDD10
DPC_VDD10

AP13
AT13

1 R349
2
0R0603-PAD

NC_DPA_VDD18#1
NC_DPA_VDD18#2

NC_DPC_VDD18#1
NC_DPC_VDD18#2

1D1V_M92

AP20
AP21

8 OF 8
DP A/B POWER

C128
SC1U6D3V2KX-GP

DP C/D POWER

C131
SCD1U16V2KX-3GP

AVGA1H

AP25
AP26

1D1V_M92

1D1V_M92
1 R348
2
0R0603-PAD

AP14
AP15

2008/10/27

1 R65
2
0R0603-PAD

DPE_VDD10
1

AL33
AM33

DPE_VDD10
DPE_VDD10

DPB_PVDD
DPB_PVSS

DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR

DPC_PVDD
DPC_PVSS

AU28
AV27

DPA_PVDD

AV29
AR28

DPB_PVDD

AU18
AV17

DPC_PVDD

DIS

DIS

DIS
2

DP PLL POWER
DPA_PVDD
DPA_PVSS

DP E/F POWER
DPE_VDD18
DPE_VDD18

150R2F-1-GP
AH34
AJ34

DIS

150R2F-1-GP
DPE_VDD18

C132
SC1U6D3V2KX-GP

AW28 1 R358

DPAB_CALR

C136
SCD1U16V2KX-3GP

1
2

DPCD_CALR

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

1D8V_S0

1
2
BLM15BD121SN1D-GP
C127
DIS

1D8V_S0
1 R51
2
0R0603-PAD

2008/10/27

1D8V_S0

DIS

DPE_PVDD

DPE_PVDD

DIS

DPEF_CALR

150R2F-1-GP
M92-M2-GP

DIS

DIS

L42

DIS

DIS

1 AM39

DIS

1 R350
2
0R0603-PAD

1
2
BLM15BD121SN1D-GP
C719
DIS

R68

DIS

DPF_PVDD

2008/10/27

C715
SC1U6D3V2KX-GP

AL38
AM35

1D8V_S0

1D8V_S0

1D8V_S0

1
2
BLM15BD121SN1D-GP
C713
DIS
SC10U6D3V3MX-GP

DIS

DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR

AF39
AH39
AK39
AL34
AM34

NC_DPF_PVDD
NC_DPF_PVSS

DIS

DPD_PVDD

L44

DPF_VDD10
DPF_VDD10

AK33
AK34

DPF_VDD10

AM37
AN38

DPE_PVDD
DPE_PVSS

C714
SCD1U16V2KX-3GP

DPF_VDD18
DPF_VDD18

AF34
AG34

C718
SC1U6D3V2KX-GP

DPF_VDD18

2008/10/27

AV19
AR18

DIS

1 R351
2
0R0603-PAD

DPD_PVDD
DPD_PVDD
DPD_PVSS

C717
SCD1U16V2KX-3GP

AN34
AP39
AR39
AU37
AW35

GND

2008/10/27
AN29
AP29
AP30
AW30
AW32

SCD1U16V2KX-3GP
C155

1 AW18

SCD1U16V2KX-3GP
C140

DIS

SCD1U16V2KX-3GP
C186

DIS

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

DPB_VDD10

L9
2 R359
DIS

1
2
1
2

DIS

DIS

DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR

AN33
AP33

SC10U6D3V3MX-GP

C143
SC10U6D3V3MX-GP

DIS

DIS

DPB_VDD10
DPB_VDD10

2
1
BLM18PG300SN-GP

DIS

SCD1U16V2KX-3GP
C151

L12

DIS

SC1U6D3V2KX-GP
C708
2
1

1D1V_M92

C712
SC10U6D3V3MX-GP

DIS

L43
1
2
BLM15BD121SN1D-GP

DIS

1D8V_S0

C135
SC10U6D3V3MX-GP

DIS

L13
2
1
BLM18PG300SN-GP

1D1V_M92

DIS

DPD_VDD10
DPD_VDD10

SC10U6D3V3MX-GP

C709
SC10U6D3V3MX-GP

DIS

SC1U6D3V2KX-GP
C141
2
1

L41
1
2
BLM15BD121SN1D-GP

SC1U6D3V2KX-GP
C145
2
1

1D8V_S0

SC1U6D3V2KX-GP
C711
2
1

AN19
AP18
AP19
AW20
AW22
C

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VSS_MECH
VSS_MECH
VSS_MECH

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AH29
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

A39
AW1
AW39

M92-M2-GP

DIS

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

DP POWER_GND
Document Number

Rev

SB

JV50-PU
Sheet

Friday, December 19, 2008

1

56

of

61

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

M92-M2 uses memory group B only

H2SYNC,

4 OF 8

AVGA1D
58,59 MDB[0..63]
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

( 0.5 * VDDR1 ) ( for SSTL-1.8/SSTL-2/DDR2 )

( 0.7 * VDDR1 ) ( for GDDR3/GDDR4 )

DIVIDER RESISTORS
MVREF TO 1.8V

DDR2
100R

MVREF TO GND

100R

DDR3
40.2R
100R

1D8V_S0

MVREFDB
MVREFSB

Y12
AA12

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
QSB_0B/WDQSB_0
QSB_1B/WDQSB_1
QSB_2B/WDQSB_2
QSB_3B/WDQSB_3
QSB_4B/WDQSB_4
QSB_5B/WDQSB_5
QSB_6B/WDQSB_6
QSB_7B/WDQSB_7
ODTB0
ODTB1
CLKB0
CLKB0#
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0_0#
CSB0_1#
CSB1_0#
CSB1_1#
CKEB0
CKEB1

MVREFDB
MVREFSB

AD28

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12

54 GPIO_VGA_00

54 GPIO_VGA_01
54 GPIO_VGA_02
54 GPIO_VGA_05
BA2
BA0
BA1

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

RDQSB0
RDQSB1
RDQSB2
RDQSB3
RDQSB4
RDQSB5
RDQSB6
RDQSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

WDQSB0
WDQSB1
WDQSB2
WDQSB3
WDQSB4
WDQSB5
WDQSB6
WDQSB7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

R62

R58

R61

58,59
58,59
58,59

54 GPIO_VGA_08

R54

2008/11/27
54 GPIO_VGA_09
54 GPIO_VGA_11

R56

R57

DIS
DIS
DIS
DY
DY

R55

2 10KR2J-3-GP
2 10KR2J-3-GP

AK10
AL10

2 10KR2J-3-GP

128MB
256MB
64MB
32MB
512MB
1GB
2GB
4GB

2 10KR2J-3-GP

x000
x001
x010
x
x
x
x
x

DIS

DQMB#[0..7]

Chingis
(formerly PMC)

M25P05A
M25P10A
M25P20
M25P40
M25P80

0100
0101
0101
0101
0101

Pm25LV512A
Pm25LV010A

0100
0101

58,59

2008/11/04
20,54 CRT_HSYNC
20,54 CRT_VSYNC
RDQSB[0..7]

R377

R378

R60

2 10KR2J-3-GP

DIS

54 GPIO_VGA_13

R59

CLKB0
CLKB0#

58
58

CLKB1
CLKB1#

59
59

RASB0#
RASB1#

58
59

CASB0#
CASB1#

58
59

CSB0#_0

58

CSB1#_0

59

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

DESCRIPTION
PCIE FULL TX OUTPUT SWING

2 10KR2J-3-GP

DIS

TX_PWRS_ENB

GPIO0

Tansmitter Power Savings Enable

0= 50% Tx output swing
1= Full Tx output swing

GPIO1

Transmitter De-emphasis Enable

0= Tx de-emphasis disabled
1= Tx de-emphasis enabled

(Internal PD)

2 10KR2J-3-GP

DIS
WDQSB[0..7]
58
59

PIN

DIS

58,59
54 GPIO_VGA_12

ODTB0
ODTB1

STRAPS

2 10KR2J-3-GP

58,59

TX_DEEMPH_EN
(Internal PD)

PCIE GNE2 ENABLED

HDMI must only be enabled on systems that are

legally entitled. It is the responsibility of the system
designer to ensure that the system is entitled to
support this feature.

0 = Advertises the PCI-E device

as 2.5GT/s
1 = Advertises the PCI-E device
as 5GT/s

BIF_GEN2_EN_A

GPIO2

AC_BATT

GPIO5

AC (Performance mode) = 3.3 V

Battery saving mode = 0.0 V

ROMSO

GPIO8

Serial ROM Output from ROM

BIF_CLK_PM_EN
0

VGA ENABLED
U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

CKEB0
CKEB1

58
59

WEB0#
WEB1#

58
59

ROMSI

GPIO9

Serial ROM Input to ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

ROMIDCFG[3:0]

if BIOS_ROM_EN=1,then Config[3:0]
defines the ROM type
if BIOS_ROM_EN=0,then Config[3:0]
defines the primary memory apeture size

X X X

AH11

PWRCNTL_[1,0]

M92-M2-GP

BB_EN

STRAPS

PIN

GPIO[15,20]

GPIO21

DESCRIPTION

DIS

GPIO

DVPDATA(23:20)

(Internal PD)
B

ST
Microelectronics

DY

(Internal PD)
DRAM_RST

Part Number GPIO[13,12,11]

2 10KR2J-3-GP

TESTEN
CLKTESTA
CLKTESTB

If BIOS_ROM_EN (GPIO22) = 1

Size of the primary

GPIO[13,12,11] Manufacturer
memory apertures

2 10KR2J-3-GP

GPIO21_BB_EN

2 10KR2J-3-GP

DIS

2008/11/27
54 GPIO_VGA_22

GPIO_28_TDO ,

2 10KR2J-3-GP

DIS

GENERICC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

If BIOS_ROM_EN (GPIO22) = 0
2008/11/27

BA2
BA0
BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

R63

DIS

R356
4K7R2F-GP

4K7R2F-GP

1KR2J-1-GP

DIS

R357

CLKTESTA
CLKTESTB
R417

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

3D3V_M92

58,59

GPIO[13,12,11]

TESTEN

DIS
2

DIS
2

R433
100R2F-L1-GP-U

C793
SCD1U16V2KX-3GP

DIS

WEB0#
WEB1#
C790
SCD01U16V2KX-3GP

DIS

DIS

DIS

C792
SCD1U16V2KX-3GP

R436
100R2F-L1-GP-U

R432
100R2F-L1-GP-U

DIS
2

1D8V_S0

C789
SCD01U16V2KX-3GP

DIS

R435
100R2F-L1-GP-U

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

MEMORY INTERFACE B

MAB[0..12]

Initialization Behavior: This signal is input during

reset (no reference clock is required). After reset,
the default state is output low (0 V).
The signals above can be left unconnected if not
used.

AUD[1]
AUD[0]

VGA_HSYNC
VGA_VSYNC

(Internal PD)

CCBYPASS

Power control signals to control the core

voltage regulator

Back Bias (body bias) which minimizes

power consumption in battery modes.
0V = Disable
3D3V = Enable

AUD[1:0]
00:No audio function
01:Audio for DisplayPort and HDMI
( if adapter is detected)
10:Audio for DisplayPort only
11:Audio for both DisplayPort and HDMI

GENERICC

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

Memory / Straps
Document Number

Rev

SB

JV50-PU
Sheet

Friday, December 19, 2008

1

57

of

61

AFBRAM3

57

W EB0#

57

RASB0#
CASB0#

57
57

DQMB#2
DQMB#3

57

ODTB0

1D8V_S0 57
57

CSB0#_0

L8

W EB0#

K3

WE#

RASB0#

K7

RAS#

CASB0#

L7

DQMB#2
DQMB#3

CS#

RDQSB2
W DQSB2

RDQSB2
W DQSB2

F3
B3

LDM
UDM

K9

ODT

VDDL
VSSDL

F7
E8

LDQS
LDQS#

RDQSB3
W DQSB3

RDQSB3
W DQSB3

B7
A8

UDQS
UDQS#

1
2

BA2

BA2

DIS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1/BA2
NC#R3/A14
NC#R7/A15
NC#R8/A13

VSS
VSS
VSS
VSS
VSS

A3
E3
J3
N1
P9

C760
SC1U6D3V2KX-GP

1D8V_S0

R425
4K99R2F-L-GP

R424

H5PS1G63EFR-20L-GP

DIS

CSB0#_0

57

W EB0#

57

RASB0#

57

CASB0#

K2

CKE

CSB0#_0

L8

CS#

W EB0#

K3

WE#

RASB0#

K7

RAS#

CASB0#

L7

CAS#

57
57

DQMB#1
DQMB#0

57

ODTB0

57
57

RDQSB1
W DQSB1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD

A1
E1
J9
M9
R1

F3
B3

LDM
UDM

K9

ODT

2008/10/30
ODTB0

57
57

RDQSB1
W DQSB1

RDQSB0
W DQSB0

RDQSB0
W DQSB0

DIS

DIS

72.51G63.A0U

C788
57,59

BA2

BA2

57,59

MDB[63..0]

MDB[63..0]

CLKB0#
CLKB0
R409

DIS
1D8V_S0

LDQS
LDQS#

B7
A8

UDQS
UDQS#

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1/BA2
NC#R3/A14
NC#R7/A15
NC#R8/A13

DIS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS
VSS
VSS
VSS
VSS

A3
E3
J3
N1
P9

C763
SCD47U6D3V2KX-GP

DIS

1
2
BLM15BD121SN1D-GP

C797
SCD1U16V2KX-3GP

F7
E8

R408

DIS

DIS

L51

J1
J7

VDDL
VSSDL

2008/10/30

DIS

2008/10/30

CK#
CK

MAB[12..0]

MAB[12..0]

CKEB0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

57,59

1
K8
J8

DQMB#1
DQMB#0

DIS

SCD1U16V2KX-3GP

57,59

1
2
DIS
BLM15BD121SN1D-GP

4K99R2F-L-GP

DIS

C762
SCD1U16V2KX-3GP

4K99R2F-L-GP

DIS
2

R404

2008/10/30

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

57

L48

J1
J7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CKEB0

CLKB0#
CLKB0

1D8V_S0

C759
SCD1U16V2KX-3GP

2008/10/30
57
57

57

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

MDB1
MDB0
MDB3
MDB7
MDB4
MDB5
MDB2
MDB6
MDB9
MDB12
MDB11
MDB15
MDB13
MDB10
MDB14
MDB8

A1
E1
J9
M9
R1

CAS#

2008/10/30
ODTB0

VDD
VDD
VDD
VDD
VDD

CLKB0#
CLKB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

CSB0#_0

57
57

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

C798
SC1U6D3V2KX-GP

DIS

DIS

CKE

BA0
BA1

K2

L2
L3

CKEB0

CKEB0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

BA0
BA1

57

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CK#
CK

2008/10/30

K8
J8

BA0
BA1

CLKB0#
CLKB0

AFBRAM4
57,59
57,59

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

MDB26
MDB31
MDB25
MDB30
MDB28
MDB24
MDB29
MDB27
MDB19
MDB22
MDB18
MDB16
MDB23
MDB17
MDB21
MDB20

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

56R2F-1-GP

CLKB0#
CLKB0

57

DIS

BA0
BA1

56R2F-1-GP

57
57

57

R405
4K99R2F-L-GP

L2
L3

BA0
BA1

BA0
BA1

57,59
57,59

H5PS1G63EFR-20L-GP

72.51G63.A0U

2008/11/11

2008/11/11
B

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

DIS

C818
SC10U6D3V3MX-GP

DIS

C821
SC10U6D3V3MX-GP

DIS

C743
SC10U6D3V3MX-GP

DIS

C765
SC10U6D3V3MX-GP

DIS

C764
SC1U6D3V2KX-GP

DIS

C757
SC1U6D3V2KX-GP

DIS

C747
SC1U6D3V2KX-GP

DIS

C755
SC1U6D3V2KX-GP

DIS

C756
SC1U6D3V2KX-GP

DIS

C758
SC1U6D3V2KX-GP

DIS

C748
SC1U6D3V2KX-GP

DIS

C804
SC1U6D3V2KX-GP

C813
SC1U6D3V2KX-GP

DIS

C399
SC1U6D3V2KX-GP

DIS

C390
SCD1U16V2KX-3GP

DIS

C783
SCD1U16V2KX-3GP

DIS

C796
SCD1U16V2KX-3GP

C812
SCD1U16V2KX-3GP

DIS

1D8V_S0

DIS

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

DDR2 B0
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

58

of

61

AFBRAM2

57

CASB1#

57
57

DQMB#5
DQMB#4

57

K3

WE#

RASB1#

K7

RAS#

CASB1#

L7

DQMB#5
DQMB#4

F3
B3

LDM
UDM

K9

ODT

2008/10/30
ODTB1

ODTB1

RDQSB5
W DQSB5

RDQSB5
W DQSB5

A1
E1
J9
M9
R1

CAS#

VDDL
VSSDL

F7
E8

R373
4K99R2F-L-GP

57

2008/10/30
RDQSB4
W DQSB4

RDQSB4
W DQSB4

B7
A8

2008/10/30

UDQS
UDQS#

1
2

BA2

VREF
NC#A2
NC#E2
NC#L1/BA2
NC#R3/A14
NC#R7/A15
NC#R8/A13

VSS
VSS
VSS
VSS
VSS

A3
E3
J3
N1
P9

57

CSB1#_0

57

W EB1#

57

RASB1#

57

CASB1#

57
57

DQMB#7
DQMB#6

57

1D8V_S0

R346
4K99R2F-L-GP

R345

H5PS1G63EFR-20L-GP

DIS

DIS

DIS

CKE

CSB1#_0

L8

CS#

W EB1#

K3

WE#

RASB1#

K7

RAS#

CASB1#

L7

CAS#

DQMB#7
DQMB#6

F3
B3

LDM
UDM

K9

ODT

2008/10/30
ODTB1

ODTB1

57
57

RDQSB7
W DQSB7

VDD
VDD
VDD
VDD
VDD

A1
E1
J9
M9
R1

VDDL
VSSDL

CLKB1#

57
57

RDQSB6
W DQSB6

F7
E8

LDQS
LDQS#

RDQSB6
W DQSB6

B7
A8

UDQS
UDQS#

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1/BA2
NC#R3/A14
NC#R7/A15
NC#R8/A13

2008/10/30

DIS

DIS

72.51G63.A0U

57,58

BA2

BA2

DIS

CLKB1

1D8V_S0

R362

DIS
L39

J1
J7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS
VSS
VSS
VSS
VSS

A3
E3
J3
N1
P9

R361

DIS

1
DIS 2
BLM15BD121SN1D-GP

C681
SCD1U16V2KX-3GP

RDQSB7
W DQSB7

C684
SCD1U16V2KX-3GP

57,58

BA2

J2
A2
E2
L1
R3
R7
R8

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

C720
SC1U6D3V2KX-GP

DIS

4K99R2F-L-GP

DIS

C716
SCD1U16V2KX-3GP

4K99R2F-L-GP

DIS
2

R372

DIS 57

J1
J7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

K2

L45

1
2
DIS
BLM15BD121SN1D-GP

C721
SCD1U16V2KX-3GP

LDQS
LDQS#

CKEB1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD
VDD
VDD
VDD
VDD

1D8V_S0 57
57

W EB1#

57
1D8V_S0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MDB[63..0]

MDB[63..0]

RASB1#

CK#
CK

57,58

56R2F-1-GP

W EB1#

57

CS#

K8
J8

CKEB1

2008/10/30

56R2F-1-GP

57

L8

CLKB1#
CLKB1

MAB[12..0]

MAB[12..0]

CSB1#_0

CSB1#_0

CLKB1#
CLKB1

57,58

57

57
57

MDB49
MDB51
MDB52
MDB48
MDB53
MDB54
MDB55
MDB50
MDB63
MDB56
MDB58
MDB57
MDB61
MDB62
MDB59
MDB60

CKE

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CKEB1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

57

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

C680
SC1U6D3V2KX-GP

DIS

DIS

DIS

CK#
CK

K2

BA0
BA1

K8
J8

CKEB1

L2
L3

CLKB1#
CLKB1

BA0
BA1

BA0
BA1

2008/10/30

CLKB1#
CLKB1

AFBRAM1
57,58
57,58

57
57

MDB33
MDB32
MDB38
MDB35
MDB39
MDB37
MDB34
MDB36
MDB40
MDB42
MDB46
MDB43
MDB47
MDB44
MDB41
MDB45

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

L2
L3

BA0
BA1

BA0
BA1

57,58
57,58

C699
SCD47U6D3V2KX-GP

H5PS1G63EFR-20L-GP

72.51G63.A0U

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

DIS

C728
SC10U6D3V3MX-GP

DIS

C710
SC10U6D3V3MX-GP

DIS

C662
SC10U6D3V3MX-GP

DIS

C698
SC10U6D3V3MX-GP

DIS

C688
SC1U6D3V2KX-GP

DIS

C683
SC1U6D3V2KX-GP

DIS

C676
SC1U6D3V2KX-GP

C672
SC1U6D3V2KX-GP

DIS

C671
SC1U6D3V2KX-GP

DIS

C724
SC1U6D3V2KX-GP

DIS

C214
SC1U6D3V2KX-GP

DIS

C163
SC1U6D3V2KX-GP

DIS

C212
SC1U6D3V2KX-GP

DIS

C144
SC1U6D3V2KX-GP

DIS

C660
SCD1U16V2KX-3GP

DIS

C663
SCD1U16V2KX-3GP

DIS

C170
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DIS

C192

1D8V_S0

DIS

M92

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

M92 DDR2 B1
Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

59

of

61

DIS

GAP-CLOSE-PW R
G90
1
2

RT8202_VDD_VGA

DIS

RT8202APQW -GP

OC
FB
VOUT

PGND

NC#5
NC#14

8K2R2F-1-GP

1
2

1
2

84.04812.A37
2ND = 84.08878.037

GAP-CLOSE-PW R
G80
1
2

C843

U52
SI4812BDY-T1-E3-GP

2008/12/18

GAP-CLOSE-PW R
G78
1
2

GAP-CLOSE-PW R
G81
1
2

68.1R510.10J

5
6
7
8
2

VCC_GFX_CORE
G77

VGA_CORE_PW R

DIS

DIS

DIS

VGA_CORE_PW R

VGA_CORE_PW R

DIS

Iomax=8A, OCP>12A

L50

IND-1D5UH-34-GP

RT8202_LX_VGA

C826

10
3

RT8202_OC_VGA_L 1
RT8202_FB_VGA

DIS

TC26
TC27
SE390U2D5VM-2GP
SE330U2VDM-L-GP

GAP-CLOSE-PW R
G82
1
2

5
14

DIS1

C828

DIS

DY

SCD1U25V3ZY-1GP

2ND = 68.1R51A.10G

RT8202_LX_VGA

4
3
2
1

C846

2
EN/DEM

VDDP

15

BOOT
UGATE
PHASE
LGATE

RT8202_DH_VGA
SCD1U25V3KX-GP

R460
RT8202_BST_VGA_L
1
2
RT8202_DH_VGA 1R2F-GP
RT8202_LX_VGA
RT8202_DL_VGA
R455

GND
GND

RT8202_EN_VGA

DIS

13
12
11
8

S
S
S
G

DIS

TON
PGOOD

DIS

C835
1
2RT8202_LX_VGA

SCD1U10V2KX-4GP

R462
1
2
0R2J-2-GP

PM_SLP_S3#

RT8202_PGOOD_VGA

16
4

DIS

D
D
D
D

12,34,35,36,42,44,49

VDD

0R0402-PAD-1-GP

84.04800.D37
2ND = 84.08884.037

C823

DIS

DY

GAP-CLOSE-PW R
G84
1
2

79.3971V.6AL
2ND = 77.93971.02L

17
6

U55

DIS

C827
SC100P50V2JN-3GP

2
2

C830
SC1U10V3ZY-6GP

C824

DIS

DIS

U51
SI4800BDY-T1

4
3
2
1

DIS

R450

5
6
7
8

2
1
2

C842
SC1KP50V2KX-1GP

83.00521.01F
2ND = 83.R2003.F8F
3RD = 83.R2003.J8F

SCD1U50V3KX-GP

5V_S5

SC10U25V6KX-1GP

RT8202_TON_VGA

SC10U25V6KX-1GP

C831
SC1U10V3ZY-6GP

D28
CH521S-30-GP-U1

S
S
S
G

R449
10KR2F-2-GP

DIS

DIS

SC10U25V6KX-1GP

DIS

DIS

DCBATOUT_8202_VGA

5V_S5

D
D
D
D

79.10712.L02
2ND = 79.10112.3JL
3RD = 79.10712.6JL

R454
10R2F-L-GP

RT8202_BST_VGA

GAP-CLOSE-PW R
DCBATOUT_8202_VGA
3D3V_S0
1 R461
2
1MR2F-GP

DIS

SE100U25VM-L1-GP

5V_S5

GAP-CLOSE-PW R
G89
1
2

GAP-CLOSE-PW R
G88
1
2

TC30

DCBATOUT_8202_VGA
G87
2

DCBATOUT

GAP-CLOSE-PW R
G79
1
2

79.33719.L01
2ND = 77.C3371.051

RT8202_DL_VGA

GAP-CLOSE-PW R
G75
1
2
RT8202_FB_VGA
GAP-CLOSE-PW R
G83
1
2

Vout=0.75*(1+Rh/Rl)
1

GAP-CLOSE-PW R
G76
1
2
GAP-CLOSE-PW R

R459

DIS

DIS 12KR2F-L-GP

R458
110KR2F-L-GP

Q26
2N7002-7F-GP

DY

DIS

R463
NV_VID1

DY

DIS 2

PW RCNTL_0 54

10KR2J-3-GP

DY

84.27002.N31
2ND = 84.27002.Y31

10KR2J-3-GP

R453
NV_VID0

PW RCNTL_1 54

2008/11/14

Q25
2N7002-7F-GP

C848
SCD1U10V2KX-4GP

DIS
84.27002.N31
2ND = 84.27002.Y31

2008/11/07
R451
30KR2F-GP

DIS

DY

DIS

R452
59KR2F-GP

RT8202_FB_VGA

C833
SC47P50V2JN-3GP

C829
SCD1U10V2KX-4GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

RT8202A_VGA CORE

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

60

of

61

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HISTORY
Size

A3
Date:
5

Document Number

Rev

SB

JV50-PU
Friday, December 19, 2008

Sheet
1

61

of

61