KLS GOGTE INSTITUTE OF TECHNOLOGY, BELAGAVI

Department of Electronics & Communication Engineering

7th Semester
DSP Algorithms & Architecture (10EC751)
Assignment 1
1. Explain decimation and interpolation process. [L2, a] (CLO1) Jun./Jul. 2015(08
Marks)
2. Draw the structure of a 8 x 8 Braun multiplier using 4 x 4 Braun multiplier
modules and show the implementation steps. [L3, a, b] (CLO2)
Dec.2014/Jan.2015 (08 Marks)
3. What is the role of a shifter in DSPr? Explain the implementation of shift left
barrel shifter with neat diagram. Tabulate the outputs for different bit shifts.
[L1, L3, a, b] (CLO2) Jun./Jul. 2014 (08 Marks)
4. Explain the circular and bit-reversed addressing mode with the help of algorithm
and diagram. [L2, a] (CLO2) Dec.2013/Jan.2014 (08 Marks)
5. Explain the different techniques used to prevent overflow and underflow
conditions occurring in MAC unit. [L2, a, b] (CLO2) Jun./Jul.2013 (08 Marks)
6. Explain 4 x 4 Baugh Wolley Signed multiplier with example. [L3, a, b] (CLO2)
Jun.2012 (08 Marks)
7. Describe the implementation of 8-tap FIR filter with single MAC unit and two
MAC units. [L3, a, c] (CLO2) Dec.2008/Jan.2009
8. The sequence
is interpolated using interpolation sequence
and the interpolation factor is 2. Find the interpolated sequence
y(m). [L3, a, b, c] (CLO1) May/Jun2010 (08 Marks) {Answer:[1 2 3 4 5 6 7 8 9]}
9. What are the memory addresses of the operands in each of the following cases of
indirect addressing modes? In each case, what will be the content of the addreg
after the memory access? Assume that the initial contents of the addreg and the
offsetreg are 03f0h and 0012h, respectively.
a. ADD *addreg{Answer: addreg=03efh}
b. ADD +*addreg
{Answer: addreg=03f1h}
c. ADD offsetreg+,*addreg {Answer: addreg=0402h}
d. ADD *addreg, offsetreg- {Answer: addreg=03deh}
[L1, L3, a ] (CLO2) (08 Marks)
10. Decimate the signal x(n)=[1, 0, 2, 4.1, 5, 6, 7, 3, 5.2] by a factor 3. The anti aliasing
filter used in decimator is [0.2, 1.2, -0.3, 0.4]. [L3, a, b, c] (CLO1) (08 Marks)
{Answer:[0.1, 6.77, 4.94, 2.08]}

Dr. Prashant P. Patavardhan

Page 1 DSPAA-Assignment1