FPGA

0-32/34/1/1

1392/11/1 :

 :
0-32/34/1/1 :
:

:
-

2
97

66944117

Barnamehdarci @ yahoo.com :

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 :
F0

FPGA
:
FPGA

FPGA ) Xilinx FIFO DCM IP Core (DDR

:
:
0B

330

121

209

) (
%25 : %65 : - %10 :

:
1B

- 3

. Job

 ) ( :
FPGA
FPGA CPU
FPGA . FPGA .

) ( :
Digital Filters With FPGA
Digital Signal Processing With FPGA
Circuit Design With FPGA

:
AVR
PIC
ARM
PCB Altium Designer

:
:

......................................

......................................

........................................

F1

F2

FPGA

1
2B

2
3B

FPGA VHDL

FPGA Verilog

FPGA ISE

FPGA

FPGA

FPGA

EMC

FPGA

10
11
12
13
14
15
16
17
18

2.

Occupational Standard
. task

:
FPGA

4B

10

5B

:
-

Flash EEPROM PROM ROM

SRAM

- EPROM

- PLA PAL

- CPLD PAL

FPGA
PROM
7805

LF33CV
LM317
LT1083-3
LT1083-adj
1N4007
1n5407

SRAM

- FPGA

1n4148

DC

MUX LC LE LUT CLB IO Block

- Xilinx DCM

ULN2803

- FPGA Xilinx

FIR Multiplier FIFO DSP

- Virtex Zynq

- FPGA

- I/O )

HSTL SSTL LVDS (

LVCMOS

- Real Time RTOS

- FLASH FPGA

Configure

- FPGA

LM35
LED Oval


AD7715

FPGA

6B

7B

ADC0808

- I/O

- Package FPGA

- FPGA

FPGA Flash

Flash

FPGA JTAG - FPGA Chain

- FPGA

FPGA
:
:
:
-

LD1117
LD1117s25
1

- FPGA

Dip Switch

clock FPGA

:
-

LD1086DT33

:
FPGA VHDL

8B

30

60

90

9B

30

- ) (Entity ) (Architecture

- IEEE

boolean integer) VHDL

bit std_logic_vector std_logic signed unsigned

(bit_vector

- inout out in) I/O (buffer

- VHDL

- ) (Identifier

FPGA
PROM
7805

LF33CV
LM317
LT1083-3
LT1083-adj
1N4007
1n5407
1n4148

DC

- ) );( ) (, |(

- ) abs

ULN2803

- xnor xor or and not

mod (rem

- )= > <= < /= =>(

- ) ror sla sra sll srl (rol

- )&(

alias subtype type - ) (Constant Generic

- VHDL

- ) CSA( withselect) VHDL

(whenelse CSA

LM35
LED Oval


AD7715

FPGA VHDL

10B

1B

ADC0808

FPGA

- ) (Sequential VHDL

Process ) (wait - ifthen

- caseis

- ) (Variables

- ) (Function

- Component Port

Map

- Package

to_integer

IEEE conv_integer) numeric

conv_std_logic_vector

to_std_logic_vector (

- whileloop forloop loop

exit

- VHDL

FPGA

- Generate VHDL

Dip Switch

LD1117
LD1117s25
LD1086DT33

FPGA VHDL
12B

13B

60

- ) X 1 0

U L H W Z (-

- VHDL

VHDL

Component

D JK

ALU State Machine - FIFO RAM VHDL

7408 74573 74245 uln2803

:
:
:
-

TTL CMOS

:
FPGA Verilog
14B

15

15B

- ) (Module

Integer Reg Wire) Verilog

(Time

- output input) I/O (inout

FPGA
PROM
7805

LF33CV
LM317
LT1083-3
LT1083-adj

- Verilog

- ) (Identifier

- ) ) ;(

) (, |(

- xnor xor or and (! ^ | &) not

1N4007
1n5407
1n4148

DC

- ) abs

- )= > <= < /= =>(

ULN2803

(%
- )(

- ) (Constant Generic

Verilog );((bet)?value:(bet) ? value

- ) (Sequential VHDL

always -

- if

- case

- )}{(

- ) CSA(

Verilog

LM35
LED Oval


AD7715

FPGA Verilog
16B

17B

ADC0808

- for while

Dip Switch

- Verilog

LD1117

- ) X 1 0

U L H W Z (-

- Verilog

- Verilog Instantiate

- ALU State Machine

:
-

:
-

LD1117s25
LD1086DT33

FPGA ISE

18B

15

20

19B

)
space(

IP VHDL Module Test Bench

User Constraint Embeded Processor

(

Synthesis

- Floor Plan Ahead) ISE

Chip Scope Xpower Analyser Plan

Timing

FPGA Editor Conastraint (System Generator

- ISE

Isim Model Sim

Slack Time -

iMPACT

FPGA mcs bit file

LF33CV
LT1083-3
LT1083-adj
1N4007
1n5407
1n4148

DC

Place Implementation (Route

Critical Path -

7805

- Report ISE

- )

PROM

Constraint -

FPGA

LM317

ULN2803

LM35
LED Oval


AD7715

FPGA ISE

20B

21B

- IP Core )

15

RAM DCM

Multiplier FIFO (Counter

- ) (Test Bench

- ISIM Modelsim

- Floor Plan

- Plan Ahead

Region

Constraint VHDL

- Timing Constraint

Slack Time

- Xpower Analyzer

FPGA

- Chip Scope

FPGA

- iMPACT FPGA

ISE :
:
:
-

ADC0808

Dip Switch

LD1117
LD1117s25
LD1086DT33

:
FPGA

2B

15

35

50

23B

FPGA

15

PROM

- DC

7805

- pwm

LF33CV

LM317
LT1083-3

Dotmatrix

ADC DAC

FPGA

FPGA
Scan

LT1083-adj
1N4007
1n5407
1n4148

- LCD

:
LED -

- 7Segment

- pwm

- DC

- 7Segment

7Segment

- ADC LM35

- ) (

35

DC

ULN2803

LM35
LED Oval


AD7715

FPGA
24B

Pattern

DAC

(Micro Blaze

SDK EDK xps

GPIO

Core -

:
:
:
-

Dip Switch

LD1117

(Recognization

- )

25B

ADC0808

- )

LD1117s25
LD1086DT33

:
FPGA

26B

20

40

50

27B

:
-

(parity

PS2

20

RGB

stop data start idle) UART

ENC28j60
FPGA

- ) PS2 (

PROM

- (RGB) VGA

7805

LF33CV
LM317

- SPI I2C Master

LT1083-3

Slave

- ENC28J60

LT1083-adj
1N4007

1n5407

- RAM

1n4148

- ) (Rapid I/O

SERIO SERDES Gigabit

DC

DSP
:

40

ULN2803

- UART

- FPGA

FIFO

LCD

- I2C SPI

- ) (Bridge

I2C SPI

UART

LM35
LED Oval

:
FPGA
28B

:
- USB FT232

ENC28j60

- VGA )

Core -

- Core USB

PCI-E

- SRAM DRAM

- MMC

UART

:
:
:
-

29B

AD7715
ADC0808

Dip Switch

LD1117
LD1117s25
LD1086DT33

:
FPGA

30B

20

30

50

31B

20

- Pipeline

Latency

AD8572

FPGA

PS2
RGB

ENC28j60

- )(

FPGA

PROM
7805

LF33CV

- FIR IIR

LM317

) MATLAB

LT1083-3

WinTool FvTool Sp Tool FDA Tool

LT1083-adj

(WvTool

1N4007

- textio

1n5407

1n4148

- ISE Simulink MATLAB

System Generator

DC

:
Pipeline

UART

ULN2803
30

FPGA
32B

:
-

LCD

- FIR IIR

Modelsim ISIM textio

- FPGA

3B

LM35
LED Oval


AD7715
ADC0808

Dip Switch

LD1117

:
-

LD1117s25
LD1086DT33

:
EMC
34B

35B

EMI

Polygon

Via

:
:

10

15

10

AD8572
PS2
RGB
ENC28j60
FPGA
PROM
7805
LF33CV
LM317
LT1083-3
LT1083-adj
1N4007
1n5407
1n4148


DC



ULN2803

:
FPGA

36B

10

10

20

37B

10

- Altium Designer

FPGA

- Core

Altium Designer FPGA

- FPGA

Altium Designer JTAG

)(Nexus

- Altium

ISE

- Altium Designer

FPGA Pin Swaping

- Altera Xilinx

Altera

Xilinx

Quartus

FPGA

- C VHDL

FPGA Advantage HDL (

Active ) FPGA

- Synplify

FPGA
Altium Designer
Quartus
FPGA
Advantage
Active HDL
Synplify

:
FPGA
38B

39B

10
Altium

Designer

Altium

Designer

- JTAG Altium Designer

- FPGA

Altium Designer

- Quartus

Altera

- FPGA Advantage Active

HDL FPGA

- Synplify

:
-

:
:
-

16

RAM 1GB CPU 3GHz

12

:
- 2 4 .

FPGA

XC3S400-4PQ208

12

PROM

XCF02S

12

LCD

2 16

12

Keypad 4*4

12

2.5 5

96

RGB LED

SMD

96

50MHz 20MHz

12

DC

12

12

DS1307

DIP

12

10

CR2032

12

11

uSD

1GB uSD

12

PCB MMC
12

FT232

BL RL DIL

12

13

LM386

DIP

12

14

12

15

LM35

Cz

12

16

ADC0804

DIP

12

17

LED

96

18

PS2

PCB

12

:
- 2 4 .

19

Dip Switch

4 3 2 1 8

12

20

1.5A

12

21

BC107-BC337-TIP3055-BC557

24

22

96

23

E12

12

24

1 40

12

25

1 40

12

26

AD8572

DIP

12

27

ADC0808

DIP

12

28

AD7715

DIP

12

29

MCP3001

DIP

12

30

MCP3550

DIP

12

31

1N4007-1N4148-1N5407

96

32

ULN2803

DIP

12

33

ds1820

12

34

12

35

12V/10A

12

36

)(

24

37

7805

12

38

LF33CV

12

39

LM317

12

40

LT1083-3

24

41

LT1083-adj

24

42

LD1117- LD1117s25-

12

43

LD1086DT33- LT1085
8 0.5

:
- 2 4 .

12

44

12

45

12

46

8 8

48

47

25

12

48

HS0038

12

49

12

50

7905

12

51

7909

12

52

Rj45

12

53

50 25 10 5

96

54

192

55

ADC

12

56

DAC

12

57

74HC573

DIP

192

58

50K 10K 5K 1K 100K

96

59

50K 10K 5K 1K 100K

96

60

12

61

1.5

12

62

MAX232

DIP

12

63

) 40KHz (

12

64

Sony

12

65

SG5010

12

66

7 6 5 4 3 2 8

96

67

2 3

96

68

12

12

69

128 64 ks108

12

:
- 2 4 .

70

100nF

24

71

LDR

12

72

Flat

2 3 5 10

73

IDC

2 5 2 20

12

74

12

75

12

76

MQ2 CO

12

77

12

78

USB

30

USB B A
79

RFID

12

80

HMT HMR

915 433

12

81

ENC28j60

DIP

12

82

PCB

12

83

84

24

85

12

86

EMI

12

87

12

88

40

12

:
- 2 4 .

FPGA

Parallel

12

JTAG FPGA

USB

12

12

12

12

40

12

12

12

12

10

12

11

12

12

1 7

12

:
- .

 ) (

FPGA

ISE

Xilinx

Modelsim

Proteus

Altium Designer

Quartus

FPGA Advantage

Active HDL

Nano board 1 technical

Altium

Mentor
Graphics
Labcenter
Electronics
Altium
Altera
Mentor
Graphics
Aldec
Altium

reference manual
10

Synplify

synopsys

) (

FPGA

1386

VHDL

)(

1390

FPGA

)(

FPGA

1390

VHDL

)(

Xilinx

1391

ISE

)(

1391

2
3
4
5

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