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【加速度传感器】Adxl345【Spi、Iic】【英文】
【加速度传感器】Adxl345【Spi、Iic】【英文】
【加速度传感器】Adxl345【Spi、Iic】【英文】
Digital Accelerometer
ADXL345
GENERAL DESCRIPTION
Activity/Inactivity monitoring
Free-Fall detection
Supply and I/O voltage range: 1.8 V to 3.6 V
SPI (3 and 4 wire) and I2C digital interfaces
Flexible interrupt modes Any interrupt mappable to either
interrupt pin
Measurement ranges selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (-40 to +85C)
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 3 5 1 mm LGA package
APPLICATIONS
Handsets
Gaming and pointing devices
Personal navigation devices
HDD protection
Fitness equipment
Digital cameras
VDD I/O
POWER
MANAGEMENT
A/D
CONVERTER
3 AXIS
SENSOR
SENSE
ELECTRONICS
DIGITAL
FILTER
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
SDA/SDI/SDIO
SERIAL I/O
ADXL345
SDO/ALT
ADDRESS
SCL/SCLK
COM
CS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADXL345
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C................................................................................................. 10
Applications....................................................................................... 1
Interrupts..................................................................................... 11
FIFO ............................................................................................. 11
Specifications..................................................................................... 3
Application ...................................................................................... 18
ESD Caution.................................................................................. 4
Tap Detection.............................................................................. 18
Threshold .................................................................................... 19
SPI................................................................................................... 9
REVISION HISTORY
11/08Rev. PrA - Initial Version
ADXL345
SPECIFICATIONS
TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V, Acceleration = 0 g, unless otherwise noted.
Table 1. Specifications1
Parameter
SENSOR INPUT
Measurement Range
Nonlinearity
Inter-Axis Alignment Error
Cross-Axis Sensitivity2
OUTPUT RESOLUTION
All g-ranges
2 g range
4 g range
8 g range
16 g range
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity Change due to Temperature
0 g BIAS LEVEL
0 g Output (XOUT, YOUT, ZOUT)
0 g Offset vs. Temperature
NOISE PERFORMANCE
Noise (x-, y-axes)
Noise (z-axis)
OUTPUT DATA RATE / BANDWIDTH
Measurement Rate3
SELF TEST
Output Change X
Output Change Y
Output Change Z
POWER SUPPLY
Operating Voltage Range (VS)
Interface Voltage Range (VDD I/O)
Supply Current
Supply Current
Standby Mode Leakage Current
Turn-On Time4
TEMPERATURE
Operating Temperature Range
WEIGHT
Device Weight
Conditions
Each axis
User Selectable
Percentage of full scale
Min
Typ
Max
Unit
2, 4, 8, 16
0.5
0.1
1
g
%
Degrees
%
10
10
11
12
13
Bits
Bits
Bits
Bits
Bits
Each axis
10-bit mode
Full-Resolution
Full-Resolution
Full-Resolution
Full-Resolution
Each axis
VS = 2.5 V, 2 g 10-bit or Full-Resolution
VS = 2.5 V, 2 g 10-bit or Full-Resolution
VS = 2.5 V, 4 g 10-bit mode
VS = 2.5 V, 4 g 10-bit mode
VS = 2.5 V, 8 g 10-bit mode
VS = 2.5 V, 8 g 10-bit mode
VS = 2.5 V, 16 g 10-bit mode
VS = 2.5 V, 16 g 10-bit mode
232
3.5
116
7.0
58
14.0
29
28.1
256
3.9
128
7.8
64
15.6
32
31.2
0.02
286
4.3
143
8.6
71
17.2
36
34.3
LSB/g
mg/LSB
LSB/g
mg/LSB
LSB/g
mg/LSB
LSB/g
mg/LSB
%/C
Each axis
VS = 2.5 V, TA = 25C
-150
0
<1
+150
mg
mg/C
<1
<1.5
0.1
3200
Hz
+0.31
-0.31
+0.46
+1.02
-1.02
+1.64
g
g
g
3.6
VS
150
V
V
A
A
A
ms
2.0
1.7
Data Rate > 100 Hz
Data Rate < 10 Hz
Data Rate = 3200 Hz
2.5
1.8
130
25
0.1
1.4
40
85
20
LSB RMS
LSB RMS
C
mgrams
All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Cross-axis sensitivity is defined as coupling between any two axes.
3
Bandwidth is half the output data rate.
4
Turn-on and wake-up times are determined by the user defined bandwidth. At 100 Hz data rate the turn-on/wake-up time is approximately 11.1 ms. For additional
data rates the turn-on/wake-up time is approximately + 1.1 in milliseconds, where is 1/(Data Rate).
2
ADXL345
Rating
10,000 g
10,000 g
0.3 V to 3.6 V
0.3 V to 3.6
0.3 V to 3.6
Indefinite
40C to +105C
40C to +105C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADXL345
SDO/ALT ADDRESS
Mnemonic
VDD I/O
GND
Reserved
GND
GND
VS
CS
INT1
INT2
GND
Reserved
SDO/ALT ADDRESS
SDA/SDI/SDIO
SCL/SCLK
Description
Digital Interface Supply Voltage
Must be connected to ground
Reserved, must be connected to VS or left open
Must be connected to ground
Must be connected to ground
Supply Voltage
Chip Select
Interrupt 1 Output
Interrupt 2 Output
Must be connected to ground
Reserved, must be connected to GND or left open
Serial Data Out, Alternate I2C Address Select
Serial Data (I2C), Serial Data In (SPI 4-Wire), Serial Data In/Out (SPI 3-Wire)
Serial Communications Clock
ADXL345
ADXL345
FUNCTIONAL DESCRIPTION
DEVICE OPERATION
The ADXL345 is a complete three-axis acceleration
measurement system with a selectable measurement range of
either 2 g, 4 g, 8 g, or 16 g. It measures both dynamic
acceleration resulting from motion or shock and static
acceleration, such as gravity, which allows it to be used as a tilt
sensor. The sensor is a polysilicon surface-micromachined
structure built on top of a silicon wafer. Polysilicon springs
suspend the structure over the surface of the wafer and provide
a resistance against acceleration forces. Deflection of the
structure is measured using differential capacitors that consist
of independent fixed plates and plates attached to the moving
mass. Acceleration deflects the beam and unbalances the
differential capacitor, resulting in a sensor output whose
amplitude is proportional to acceleration. Phase-sensitive
demodulation is used to determine the magnitude and polarity
of the acceleration.
POWER SEQUENCING
Power may be applied to VS or VDD I/O in any sequence without
damaging the ADXL345. All possible power on states are
summarized in Table 4. The interface voltage level is set with
the interface supply voltage VDD I/O, which must be present to
ensure that the ADXL345 does not create a conflict on the
communications bus. For single-supply operation, VDD I/O can be
the same as the main supply, VS. Conversely, in a dual-supply
application, VDD I/O can differ from VS to accommodate the
desired interface voltage. Once VS is applied, the device enters
standby state, where power consumption is minimized and the
device waits for VDD I/O to be applied and a command to enter
measurement state (setting the MEASURE bit in the
POWER_CTL register). Clearing the MEASURE bit returns the
device to standby state.
Table 4. Power Sequencing
Condition
Power Off
Bus Enabled
Standby or
On
Measurement
On
POWER SAVING
Power Modes
IDD (A)
130
80
130
130
130
130
80
55
37
25
25
25
25
25
25
25
IDD (A)
130
80
130
80
55
37
30
25
25
25
25
25
25
25
25
25
ADXL345
ADXL345
SERIAL COMMUNICATIONS
ADXL345
SCL/SCLK
D OUT
D IN/OUT
SDO
D IN
SCL/SCLK
D OUT
D OUT
PROCESSOR
SDA/SDI/SDIO
D IN/OUT
SDO
CS
D OUT
SDA/SDI/SDIO
SPI
ADXL345
PROCESSOR
CS
tSCLK
tS
tM
tQUIET
CS
SCLK
SDI
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[7] D[6]
D[1] D[0]
SDO
tSETUP
tHOLD
tSDO
tSCLK
tS
tM
tQUIET
CS
SCLK
SDI
R/W
MB
A[5]
A[4]
SDO
A[3]
A[2]
A[1]
A[0]
D[7] D[6]
D[5] D[4]
tSETUP
tHOLD
tSDO
D[3] D[2]
D[1] D[0]
ADXL345
tSCLK
tS
tM
tQUIET
CS
SCLK
SDI
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[7] D[6]
D[5] D[4]
D[3] D[2]
D[1] D[0]
SDO
tSETUP
tHOLD
tSDO
Parameter Limit
fSCLK
tSCLK
tDELAY
tQUIET
tS
tM
tSDO
tSETUP
tHOLD
Unit
Description
5 MHz max SPI clock frequency
1/(SPI clock frequency) Mark/space
200 ns min
ratio for the SCLK input is 40/60 to
60/40
200 ns min
falling edge to SCLK falling edge
200 ns min
SCLK rising edge to rising edge
0.4 tSCLK ns min
SCLK low pulse width (space)
0.4 tSCLK ns min
SCLK high pulse width (mark)
8 ns max
SCLK falling edge to SDO transition
10 ns min
SDI valid before SCLK rising edge
10 ns min
SDI valid after SCLK rising edge
VDD I/O
ADXL345
RP
RP
PROCESSOR
CS
SDA/SDI/SDIO
D IN/OUT
SDO
SCL/SCLK
D OUT
06238- 007
I2C
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed
VDD I/O by more than 0.3 V. Pull-up resistors, RP, should be in the
range of 1k to 20k.
Data
Register Address
Ack
Stop
Ack
Data
Register Address
Ack
Start1
Register Address
Data
Start1
Ack
Ack
Register Address
Stop
Ack
NAck
Ack
Data
Ack
Data
Ack
Stop
Ack
NAck
Data
Stop
ADXL345
INTERRUPTS
OVERRUN
OVERRUN is set when new data has replaced unread data. The
precise operation of OVERRUN depends on the FIFO mode.
In Bypass Mode, OVERRUN is set when new data replaces
unread data in the DATAX, DATAY, and DATAZ registers. In
all other modes, OVERRUN is set when the FIFO is filled.
OVERRUN is cleared by reading the FIFO contents, and is
automatically cleared when the data is read.
DATA_READY
FIFO
The ADXL345 contains a 32 level FIFO that can be used to
minimize host processor intervention. The FIFO has four
modes as described in Table 15 in the Register Definitions
section. Mode selection is made by setting the appropriate
MODE bits in the FIFO_CTL register. Each FIFO mode is
described below.
Bypass Mode
INACTIVITY
In Trigger Mode, the FIFO fills and holds the latest 32 X, Y, and
Z samples. Once a trigger event occurs (as described by the
TRIG_SOURCE bit in the FIFO_CTL register), the FIFO will
keep the last n samples (where n is the value specified by
SAMPLES in the FIFO_CTL register) and then operate in FIFO
mode, collecting new samples only when the FIFO is not full.
Additional trigger events will not be recognized until Trigger
Mode is reset. This can be done by setting the device in Bypass
Mode, reading the FIFO_STATUS register and then setting the
device back into Trigger Mode. The FIFO data should be read
first, as placing the device into Bypass Mode will clear the FIFO.
ADXL345
Vs = 2.5 V
Min.
Max.
Min.
X-Axis
+40
+130
+70
+225
Y-Axis
-40
-130
-70
-225
Z-Axis
+60
+210
+105
+365
Vs = 2.5 V
Min.
Max.
Min.
+65
+35
+113
Y-Axis
-20
-65
-35
-113
Z-Axis
+30
+105
+52
+183
Vs = 2.5 V
Min.
X-Axis
X-Axis
+80
+260
+140
Typ.
-80
-260
-140
-455
+120
+420
+210
+730
Vs = 2.5 V
Max.
Min.
+33
+17
Typ.
Max.
+57
-10
-33
-17
-57
+15
+53
+26
+92
Max.
Z-Axis
+10
Typ.
Z-Axis
+455
Y-Axis
Max.
Y-Axis
Vs = 3.3 V
Min.
Typ.
Typ.
Vs = 2.5 V
+20
Typ.
Max.
X-Axis
Vs = 2.5 V
Typ.
SELF TEST
Min.
Typ.
Vs = 3.3 V
ADXL345
REGISTER MAP
Table 12. Register Map
Hex
0
1
Dec
0
1
Name
DEVID
Reserved
Type
R
Reset Value
11100101
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R
R
R
R
R/W
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00001010
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
to
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Reserved
THRESH_TAP
OFSX
OFSY
OFSZ
DUR
LATENT
WINDOW
THRESH_ACT
THRESH_INACT
TIME_INACT
ACT_INACT_CTL
THRESH_FF
TIME_FF
TAP_AXES
ACT_TAP_STATUS
BW_RATE
POWER_CTL
INT_ENABLE
INT_MAP
INT_SOURCE
DATA_FORMAT
DATAX0
DATAX1
DATAY0
DATAY1
DATAZ0
DATAZ1
FIFO_CTL
FIFO_STATUS
Description
Device ID.
Reserved. Do not access.
Reserved. Do not access.
Reserved. Do not access.
Tap threshold
X axis offset
Y axis offset
Z axis offset
Tap duration
Tap latency
Tap window
Activity threshold
Inactivity threshold
Inactivity time
Axis enable control for ACT/INACT
Free-fall threshold
Free-fall time
Axis control for Tap/Double Tap
Source of Tap/Double Tap
Data Rate and Power Mode control
Power Save features control
Interrupt enable control
Interrupt mapping control
Source of interrupts
Data format control
X axis data
Y axis data
Z axis data
FIFO control
FIFO status
ADXL345
REGISTER DEFINITIONS
0x00 DEVID (read-only)
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
D7
MSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
OFSX/OFSY/OFSZ offer user offset adjustments in twoscompliment form with a scale factor of 15.6 mg/LSB (i.e. 0x7F =
+2 g).
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
ADXL345
0x2A TAP_AXES (read/write)
D6
D5
D4
D3
D2
D1
D0
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
LSB
D7
D6
D5
D4
D3
SUPPRESS
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
ACT_X ACT_Y ACT_Z
TAP_X TAP_Y TAP_Z
ASLEEP
Source Source Source
Source Source Source
D6
D5
D4
LOW_POWER
D3
D2
D1
D0
RATE
ADXL345
D6
D5
D4
D2
D1
D0
WAKEUP
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
Table 13 below:
0x31 DATA_FORMAT (read/write)
D0
0
1
0
1
D7
Frequency (Hz)
8
4
2
1
D6
SELF_TEST SPI
D5
D4
INT_INVERT
D3
D2
FULL_RES JUSTIFY
D1
D0
RANGE
ADXL345
D0
0
1
0
1
g-Range
2 g
4 g
8 g
16 g
D7 D6 MODE Function
0
0
0 Bypass
1 FIFO
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
Stream
Trigger
D6
D5
D4
D3
D2
D1
D0
D6
D5
FIFO_MODE TRIGGER
D4
D3
D2
D1
D0
SAMPLES
D7
FIFO_TRIG
D6
X
D5
D4
D3
D2
D1
D0
ENTRIES
ADXL345
APPLICATION
POWER SUPPLY DECOUPLING
In many applications, a 0.1 F capacitor at VS and VDD I/O placed
close to the ADXL345 supply pins adequately decouples the
accelerometer from noise on the power supply. However, in
applications where noise is present at the 50 kHz internal clock
frequency, or any harmonic thereof, additional care in power
supply bypassing is required because this noise may cause errors
in acceleration measurement. If additional decoupling is
necessary, a 10 resistor or ferrite in series with VS and an
additional larger bypass capacitor (2.2 F or greater) at VS may
be helpful.
FIRST TAP
XHI BW
SECOND TAP
THRESHOLD
(THRESHC)
ACCELEROMETER
PCB
Figure 11. Tap Interrupt Function with Valid Single and Double Taps
If only the single tap function is in use, the single tap interrupt
will trigger at the point that the acceleration goes below the
threshold as long as DUR is not exceeded. If both single and
double tap functions are in use the single tap interrupt will
trigger once the double tap event has been either validated or
invalidated.
Several events can occur to invalidate the second tap of a double
tap event. First, if the SUPPRESS bit in the TAP_AXES register
is set, any acceleration spikes above the threshold during the
LATENT time window will invalidate the double tap as seen in
Figure 12.
06238-014
MOUNTING POINTS
INT
LATENCY
TIME
(LATENT)
XHI BW
TAP DETECTION
TIME LIMIT
FOR TAPS
(DUR)
LATENCY
TIME (LATENT)
Figure 12. Double Tap event invalid due to high-g event with SUPPRESS set
06238-011
ADXL345
XHI BW
THRESHOLD
LINK MODE
The LINK function can be used to reduce the number of
activity interrupts the processor must service by only looking
for activity after inactivity. For proper operation of the link
feature, the processor must still respond to the activity and
inactivity interrupts by reading the INT_SOURCE register to
clear them. If the activity interrupt is not cleared, the part will
not go into Auto Sleep Mode. The ASLEEP bit in the
ACT_TAP_STATUS register indicates if the part is in Auto
Sleep Mode.
TIME LIMIT
FOR TAPS
(DUR)
TIME LIMIT
FOR TAPS
(DUR)
LATENCY
TIME
(LATENT)
XHI BW
TIME LIMIT
FOR TAPS
(DUR)
INVALIDATES
DOUBLE TAP AT
END OF DUR
ADXL345
0.5500
0.2500
3.0500
0.2500
1.1450
06238-015
0.3400
5.34
ADXL345
tP
TP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
06238-016
TEMPERATURE
RAMP-UP
t25C TO PEAK
TIME
Sn63/Pb37
3C/sec max
Condition
Pb-Free
3C/sec max
100C
150C
60 sec to 120 sec
150C
200C
60 sec to 180 sec
3C/sec max
3C/sec max
183C
60 sec to 150 sec
240 + 0/5C
10 sec to 30 sec
6C/sec max
6 minutes max
217C
60 sec to 150 sec
260 + 0/5C
20 sec to 40 sec
6C/sec max
8 minutes max
ADXL345
OUTLINE DIMENSIONS
ORDERING GUIDE
Model
ADXL345BCCZ1
Measurement
Range
2, 4, 8, 16g
Specified
Voltage (V)
2.5
Temperature
Range
40C to +85C
ADXL345BCCZRL1
2, 4, 8, 16g
2.5
40C to +85C
ADXL345BCCZRL71
2, 4, 8, 16g
2.5
40C to +85C
EVAL-ADXL345Z1
1
Package Description
14-Lead Land Grid Array
Package [LGA]
14-Lead Land Grid Array
Package [LGA]
14-Lead Land Grid Array
Package [LGA]
Evaluation Board
Z = Pb-free part.
Package
Option
TBD
TBD
TBD
ADXL345
NOTES
ADXL345
NOTES