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EE 211 Electronics
Devices Lab
NAME- Adit Bhardwaj
ROLL NO. 10002004
GROUP MEMBER- Arun kumar singh(10002034)
GROUP NO. - 23

Course instructor Prof. Arup lal

EXPERIMENT NO.8
I-V CHARACTERSTICS OF
JFET

DATE - 27/10/2011

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OBJECTIVE: To observe the Drain Characteristics and

Transconductance Characteristics of JFET.
EQUIPMENTS: JFET, Two variable D.C. voltage sources, 2 multi
meters, two 100 resistors, breadboard.
PRINCIPLE:
JFET: A field effect transistor (FET) is a unipolar device,
conducting a current using only one kind of charge carrier. The
junction field-effect transistor is the simplest type of field-effect
transistor. In a JFET the voltage variable depletion region width
of a junction is used to control the effective cross-sectional area
of a conducting channel.

n-Channel JFET
JFET

p-Channel

PROCEDURE
PART1
1.Circuit components were arranged on the bread board
according to the following circuit diagram.

CIRCUIT DIAGRAM: COMMON SOURCE

CONFIGURATION OF JFET

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2. ID is observed for different values of VDS and VGS is kept

constant. VDD is also kept below of 10V.

TABLE: Drain current (ID) versus the Drain-Source voltage (VDS)

for a common Source configuration and VGS constant.
Table-1 VGS= -0.03V
S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.

VDS

ID (mA)

(V)

0.001

0.004

0.052

0.228

0.107

0.447

0.148

0.619

0.177

0.735

0.206

0.831

0.224

0.903

0.250

1.009

0.314

1.258

0.373

1.466

0.439

1.655

0.478

1.798

0.557

2.000

0.630

2.190

0.695

2.438

0.954

3.008

1.265

3.500

1.765

4.000

2.889

4.500

Table-2 VGS=-.3V
S.no
1.
2.
3.
4.
5.
6.
7.

VDS

ID (mA)

(V)

0.003

0.015

0.081

0.309

0.192

0.696

0.316

1.082

0.45

1.455

0.578

1.762

0.751

2.098

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8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20

0.958

2.4

1.219

2.652

1.493

2.82

1.867

2.951

2.297

2.757

3.014

3.21

3.037

3.69

3.05

4.12

3.062

4.61

3.1

5.07

3.1

5.62

3.1

6.04

3.1

Table-4 VGS= -0.5V

S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.

VDS

(V)

ID (mA)

0.007

0.028

0.039

0.139

0.112

0.38

0.166

0.549

0.235

0.75

0.353

1.068

0.46

1.312

0.554

1.508

0.751

1.831

1.014

2.114

1.174

2.225

1.511

2.366

1.911

2.453

2.429

2.515

2.94

2.551

3.38

2.574

4.52

2.61

5.32

2.626

6.33

2.636

2.647

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Table-3 VGS= -1.5V

S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

VDS

ID (mA)

(V)

0.052

0.01

0.216

0.024

0.471

0.031

1.011

0.039

1.95

0.047

2.89

0.051

3.94

0.055

4.97

0.059

5.97

0.062

6.9

0.064

7.91

0.065

9.96

0.066

Plot:

ID V/s VDS
3.5
3
2.5
2
ID(mA) 1.5
1
0.5
0
0

3
VDS(V)

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PART2
1. Circuit components are arranged on the bread board
according to the following circuit diagram.

CIRCUIT DIAGRAM: COMMON

SOURCE CONFIGURATION OF JFET

2. ID is observed for different values of VGS and VDS is

kept constant. VDD is also kept below of 10V.

TABLE: Drain current (ID) versus the Gate-Source voltage (VGS)
for a common Source configuration and VDS constant.
Table-1 VDS= 3V
S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Table-2 VDS= 5V

VGS

(V)

ID (mA)

-2.26

0.001

-1.67

0.008

-1.5

0.072

-1.41

0.155

-1.3

0.296

-1.21

0.45

-1.1

0.67

-1

0.982

-0.8

1.532

-0.6

2.254

-0.41

2.8

-0.3

3.2

-0.2

3.7

-0.11

4.1

-0.02

4.5

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S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19
20

VGS

ID (mA)

(V)

-2.48

-3.23

0.001

-2.98

0.001

-2.74

0.002

-2.47

0.003

-2.23

0.004

-1.98

0.007

-1.73

0.023

-1.5

0.092

-1.22

0.51

-1

0.971

-0.78

1.61

-0.64

2.31

-0.52

2.55

-0.42

2.9

-0.39

3.1

-0.31

3.4

-0.19

3.8

-0.1

4.2

-0.03

4.5

Table-3 VDS=
S.no
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14
15

VGS

(V)

ID (mA)

-0.02

4.6

-0.12

4.1

-0.25

3.6

-0.51

2.5

-0.39

-0.6

2.26

-0.74

1.772

-0.91

1.284

-1.1

0.748

-1.3

0.341

-1.51

0.064

-1.69

0.007

-2

0.002

-2.5

0.001

-3.5

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5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-4

RESULTS:

-3.5

-3

-2.5

-2

-1.5

-1

-0.5