Professional Documents
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Analog and Digital Electronics
Analog and Digital Electronics
Analog and Digital Electronics
YEAR 2012
MCQ 8.1
MCQ 8.2
MCQ 8.3
(D) XY Z , XYZ, XY Z , XY Z
(B) 9.3 mA
(C) 6.67 mA
(D) 6.2 mA
MCQ 8.4
ONE MARK
(D) 10
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PAGE 420
CHAP 8
MCQ 8.6
TWO MARKS
(A) Av . 200
(B) Av . 100
(C) Av . 20
(D) Av . 10
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CHAP 8
MCQ 8.7
PAGE 421
1
rad/s
(R1 + R2) C
(B) high pass filter with f3dB = 1 rad/s
R1 C
(C) low pass filter with f3dB = 1 rad/s
R1 C
1
(D) high pass filter with f3dB =
rad/s
(R1 + R2) C
(A) low pass filter with f3dB =
YEAR 2011
MCQ 8.8
ONE MARK
MCQ 8.9
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PAGE 422
MCQ 8.10
(A) 1
(B) 0
(C) X
(D) X
YEAR 2011
MCQ 8.11
CHAP 8
TWO MARKS
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CHAP 8
MCQ 8.12
PAGE 423
POP D
(A) DAD H
PUSH D
POP
DAD
INX
(B)
INX
INX
PUSH
POP H
(C) DAD D
PUSH H
XTHL
INX D
(D) INX D
INX D
XTHL
H
D
H
H
H
H
The transistor used in the circuit shown below has a of 30 and ICBO is
negligible
If the forward voltage drop of diode is 0.7 V, then the current through
collector will be
(A) 168 mA
(B) 108 mA
(C) 20.54 mA
MCQ 8.13
(D) 5.36 mA
It the state QA QB of the counter at the clock time tn is 10 then the state
QA QB of the counter at tn + 3 (after three clock cycles) will be
(A) 00
(B) 01
(C) 10
(D) 11
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PAGE 424
MCQ 8.14
CHAP 8
YEAR 2010
MCQ 8.15
ONE MARK
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CHAP 8
MCQ 8.16
(A) 4 V
(B) 6 V
(C) 7.5 V
(D) 12.12 V
Assuming that the diodes in the given circuit are ideal, the voltage V0 is
(A) 4 V
(B) 5 V
(C) 7.5 V
(D) 12.12 V
YEAR 2010
MCQ 8.17
MCQ 8.18
PAGE 425
TWO MARKS
The transistor circuit shown uses a silicon transistor with VBE = 0.7, IC . IE
and a dc current gain of 100. The value of V0 is
(A) 4.65 V
(B) 5 V
(C) 6.3 V
(D) 7.23 V
The TTL circuit shown in the figure is fed with the waveform X (also
shown). All gates have equal propagation delay of 10 ns. The output Y of
the circuit is
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PAGE 426
MCQ 8.19
When a CALL Addr instruction is executed, the CPU carries out the
following sequential operations internally :
Note: (R)
means content of register R
((R)) means content of memory location pointed to by R.
PC
means Program Counter
SP
means Stack Pointer
(A) (SP) incremented
(B)
(PC)!Addr
(PC)!Addr
((SP))!(PC)
((SP))!(PC)
(SP) incremented
(C) (PC)!Addr
(D)
((SP))!(PC)
(SP) incremented
(SP) incremented
((SP))!(PC)
(PC)!Addr
MCQ 8.20
CHAP 8
(B) F = X Y + YZ
(C) F = X Y + Y Z
(D) F = X Y + Y Z
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CHAP 8
MCQ 8.21
YEAR 2009
MCQ 8.22
PAGE 427
ONE MARK
The following circuit has a source voltage VS as shown in the graph. The
current through the circuit is also shown.
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PAGE 428
CHAP 8
MCQ 8.23
The increasing order of speed of data access for the following device is
(I) Cache Memory
(II) CD-ROM
(III) Dynamic RAM
(IV) Processor Registers
(V) Magnetic Tape
MCQ 8.24
The complete set of only those Logic Gates designated as Universal Gates is
(A) NOT, OR and AND Gates
(B) XNOR, NOR and NAND Gates
(C) NOR and NAND Gates
(D) XOR, NOR and NAND Gates
YEAR 2009
MCQ 8.26
TWO MARKS
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CHAP 8
MCQ 8.27
PAGE 429
Transformer and emitter follower can both be used for impedance matching
at the output of an audio amplifier. The basic relationship between the
input power Pin and output power Pout in both the cases is
(A) Pin = Pout for both transformer and emitter follower
(B) Pin > Pout for both transformer and emitter follower
(C) Pin < Pout for transformer and Pin = Pout for emitter follower
(D) Pin = Pout for transformer and Pin < Pout for emitter follower
MCQ 8.28
MCQ 8.29
(D) 10 H
An ideal op-amp circuit and its input wave form as shown in the figures. The
output waveform of this circuit will be
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PAGE 430
YEAR 2008
MCQ 8.30
CHAP 8
ONE MARK
The equivalent circuits of a diode, during forward biased and reverse biased
conditions, are shown in the figure.
(I)
(II)
If such a diode is used in clipper circuit of figure given above, the output
voltage V0 of the circuit will be
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CHAP 8
YEAR 2008
MCQ 8.31
MCQ 8.32
MCQ 8.33
PAGE 431
TWO MARKS
(A) 0 mA
(B) 3.6 mA
(C) 4.3 mA
(D) 5.7 mA
In the voltage doubler circuit shown in the figure, the switch S is closed at
t = 0 . Assuming diodes D1 and D2 to be ideal, load resistance to be infinite
and initial capacitor voltages to be zero. The steady state voltage across
capacitor C1 and C2 will be
The block diagrams of two of half wave rectifiers are shown in the figure.
The transfer characteristics of the rectifiers are also shown within the block.
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PAGE 432
CHAP 8
It is desired to make full wave rectifier using above two half-wave rectifiers.
The resultants circuit will be
MCQ 8.34
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CHAP 8
PAGE 433
MCQ 8.35
MCQ 8.36
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PAGE 434
MCQ 8.37
CHAP 8
Content
26FE
00
26FF
01
2700
02
2701
03
2702
04
g
g
The content of stack (SP), program counter (PC) and (H,L) are 2700 H,
2100 H and 0000 H respectively. When the following sequence of instruction
are executed.
2100 H: DAD SP
2101 H: PCHL
the content of (SP) and (PC) at the end of execution will be
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CHAP 8
YEAR 2007
MCQ 8.39
PAGE 435
ONE MARK
The common emitter forward current gain of the transistor shown is F = 100
MCQ 8.40
MCQ 8.41
(A) 0.6 W
(B) 2.4 W
(C) 4.2 W
(D) 5.4 W
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PAGE 436
CHAP 8
rV
R1 < R2
r < R2
(B) a voltage source with voltage
V
R1
r < R2 V
(C) a current source with current c
R1 + R2 m r
(D) a current source with current c R2 mV
R1 + R2 r
(A) a voltage source with voltage
MCQ 8.42
A, B, C and D are input, and Y is the output bit in the XOR gate circuit
of the figure below. Which of the following statements about the sum S of
A, B, C, D and Y is correct ?
TWO MARKS
The input signal Vin shown in the figure is a 1 kHz square wave voltage that
alternates between + 7 V and 7 V with a 50% duty cycle. Both transistor
have the same current gain which is large. The circuit delivers power to the
load resistor RL . What is the efficiency of this circuit for the given input ?
choose the closest answer.
(A) 46%
(B) 55%
(C) 63%
(D) 92%
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CHAP 8
MCQ 8.44
PAGE 437
MCQ 8.46
(D) 526.632
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PAGE 438
YEAR 2006
MCQ 8.47
MCQ 8.48
CHAP 8
ONE MARK
What are the states of the three ideal diodes of the circuit shown in figure ?
For a given sinusoidal input voltage, the voltage waveform at point P of the
clamper circuit shown in figure will be
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CHAP 8
YEAR 2006
MCQ 8.49
PAGE 439
TWO MARKS
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PAGE 440
MCQ 8.50
MCQ 8.51
CHAP 8
Consider the circuit shown in figure. If the of the transistor is 30 and ICBO
is 20 mA and the input voltage is + 5 V , the transistor would be operating in
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CHAP 8
MCQ 8.52
PAGE 441
A TTL NOT gate circuit is shown in figure. Assuming VBE = 0.7 V of both
the transistors, if Vi = 3.0 V, then the states of the two transistors will be
A student has made a 3-bit binary down counter and connected to the R-2R
ladder type DAC, [Gain = ( 1 k/2R)] as shown in figure to generate a
staircase waveform. The output achieved is different as shown in figure.
What could be the possible cause of this error ?
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PAGE 442
CHAP 8
MCQ 8.55
MCQ 8.56
(D) 65279
INX H
(D)
INR M
XCHG
YEAR 2005
MCQ 8.57
ONE MARK
Assume that D1 and D2 in figure are ideal diodes. The value of current is
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CHAP 8
MCQ 8.58
(A) 0 mA
(B) 0.5 mA
(C) 1 mA
(D) 2 mA
The 8085 assembly language instruction that stores the content of H and L
register into the memory locations 2050H and 2051H , respectively is
(B) SPHL 2051H
(A) SPHL 2050H
(C) SHLD 2050H
MCQ 8.59
MCQ 8.60
Assume that the N-channel MOSFET shown in the figure is ideal, and that
its threshold voltage is + 1.0 V the voltage Vab between nodes a and b is
(A) 5 V
(B) 2 V
(C) 1 V
(D) 0 V
(A) JK flip-flop
(C) T flip-flop
YEAR 2005
MCQ 8.61
PAGE 443
TWO MARKS
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PAGE 444
MCQ 8.62
(A) 0 A
(B) 10 A
(C) 100 A
(D) 1000 A
CHAP 8
(A) Infinity
(B) 1 M
(C) 100 k
(D) 40 k
MCQ 8.63
MCQ 8.64
In the given figure, if the input is a sinusoidal signal, the output will appear
as shown
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CHAP 8
MCQ 8.65
PAGE 445
Select the circuit which will produce the given output Q for the input signals
X1 and X2 given in the figure
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PAGE 446
MCQ 8.66
MCQ 8.67
CHAP 8
If X1 and X2 are the inputs to the circuit shown in the figure, the output Q
is
(A) X1 + X2
(B) X1 : X2
(C) X1 : X2
(D) X1 : X2
(A) at 1
(B) at 0
(D) unstable
Data for Q. 68 and Q. 69 are given below. Solve the problems and
choose the correct option.
Assume that the threshold voltage of the N-channel MOSFET shown in
figure is + 0.75 V. The output characteristics of the MOSFET are also
shown
MCQ 8.68
(D) 10 ms
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CHAP 8
MCQ 8.69
(B) 7.5
(C) + 10
(D) 10
YEAR 2004
MCQ 8.70
MCQ 8.71
MCQ 8.72
PAGE 447
ONE MARK
(A) 33 mA
(B) 3.3 mA
(C) 2 mA
(D) 0 mA
(A) 0 mA
(B) 2.3 mA
(C) 4.3 mA
(D) 7.3 mA
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PAGE 448
MCQ 8.73
CHAP 8
The digital circuit using two inverters shown in figure will act as
YEAR 2004
MCQ 8.75
MCQ 8.76
TWO MARKS
Assuming that the diodes are ideal in figure, the current in diode D1 is
(A) 9 mA
(B) 5 mA
(C) 0 mA
(D) 3 mA
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CHAP 8
MCQ 8.77
MCQ 8.78
(A) 10.0 k
(B) 8.3 k
(C) 5.0 k
(D) 2.5 k
PAGE 449
The value of R for which the PMOS transistor in figure will be biased in
linear region is
(A) 220
(B) 470
(C) 680
(D) 1200
(C) 10 rad/s
(D) 1 rad/s
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PAGE 450
MCQ 8.79
MCQ 8.80
MCQ 8.81
MCQ 8.82
CHAP 8
(A) + 100 k
(B) 100 k
(C) + 1 M
(D) 1 M
(B) AD + B $ C $ D
(C) (A + D) (B $ C + D )
(D) A $ D + BC $ D
The digital circuit shown in figure generates a modified clock pulse at the
output. Choose the correct output waveform from the options given below.
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CHAP 8
MCQ 8.83
MCQ 8.84
PAGE 451
(D) 16
In the Schmitt trigger circuit shown in figure, if VCE (sat) = 0.1 V , the output
logic low level (VOL) is
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PAGE 452
(A) 1.25 V
(B) 1.35 V
(C) 2.50 V
(D) 5.00 V
YEAR 2003
MCQ 8.85
CHAP 8
ONE MARK
MCQ 8.87
In the circuit of figure, assume that the transistor has hfe = 99 and VBE = 0.7
V. The value of collector current IC of the transistor is approximately
(A) [3.3/3.3] mA
(B) [3.3/(3.3+3.3)] mA
(C) [3.3/.33] mA
(D) [3.3(33+3.3)] mA
For the circuit of figure with an ideal operational amplifier, the maximum
phase shift of the output vout with reference to the input vin is
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CHAP 8
MCQ 8.88
MCQ 8.89
(A) 0c
(B) 90c
(C) + 90c
(D) ! 180c
PAGE 453
YEAR 2003
MCQ 8.90
TWO MARKS
(A) 2.8 mA
(B) 2.0 mA
(C) 1.4 mA
(D) 1.0 mA
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PAGE 454
MCQ 8.91
MCQ 8.92
MCQ 8.93
CHAP 8
Assuming the operational amplifier to be ideal, the gain vout /vin for the
circuit shown in figure is
(A) 1
(B) 20
(C) 100
(D) 120
A voltage signal 10 sin t is applied to the circuit with ideal diodes, as shown
in figure, The maximum, and minimum values of the output waveform Vout
of the circuit are respectively
(A) + 10 V and 10 V
(B) + 4 V and 4 V
(C) + 7 V and 4 V
(D) + 4 V and 7 V
The circuit of figure shows a 555 Timer IC connected as an astable multivibrator. The value of the capacitor C is 10 nF. The values of the resistors
RA and RB for a frequency of 10 kHz and a duty cycle of 0.75 for the output
voltage waveform are
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CHAP 8
PAGE 455
MCQ 8.95
MCQ 8.96
MCQ 8.97
can be
(D) XY + YZ + X Z
The shift register shown in figure is initially loaded with the bit pattern
1010. Subsequently the shift register is clocked, and with each clock pulse
the pattern gets shifted by one bit position to the right. With each shift, the
bit at the serial input is pushed to the left most position (msb). After how
many clock pulses will the content of the shift register become 1010 again ?
(A) 3
(B) 7
(C) 11
(D) 15
(A) J = X, K = Y
(B) J = X, K = Y
(C) J = Y, K = X
(D) J = Y , K = X
A memory system has a total of 8 memory chips each with 12 address lines
and 4 data lines, The total size of the memory system is
(A) 16 kbytes
(B) 32 kbytes
(C) 48 kbytes
(D) 64 kbytes
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PAGE 456
CHAP 8
MCQ 8.98
YEAR 2002
ONE MARK
The frequency of the clock signal applied to the rising edge triggered D-flipflop shown in Figure is 10 kHz. The frequency of the signal available at Q is.
MCQ 8.99
MCQ 8.100
(A) 10 kHz
(C) 20 kHz
(D) 5 kHz
The forward resistance of the diode shown in Figure is 5 and the remaining
parameters are same at those of an ideal diode. The dc component of the
source current is
(A) Vm
(B) Vm
50
50 2
Vm
(C)
(D) 2Vm
50
100 2
MCQ 8.101 The cut-in voltage of both zener diode DZ and diode D shown in Figure
is 0.7 V, while break-down voltage of DZ is 3.3 V and reverse break-down
voltage of D is 50 V. The other parameters can be assumed to be the same
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CHAP 8
PAGE 457
as those of an ideal diode. The values of the peak output voltage (Vo) are
(A) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.
(B) 4 V in the positive half cycle and 5 V in the negative half cycle.
(C) 3.3 V in both positive and negative half cycles.
(D) 4 V in both positive and negative half cycle
MCQ 8.102
The logic circuit used to generate the active low chip select (CS ) by an 8085
microprocessor to address a peripheral is shown in Figure. The peripheral
will respond to addresses in the range.
(A) E000-EFFF
(B) 000E-FFFE
(C) 1000-FFFF
(D) 0001-FFF1
YEAR 2002
MCQ 8.103
MCQ 8.104
TWO MARKS
The output voltage (vo) of the Schmitt trigger shown in Figure swings
between + 15 V and 15 V . Assume that the operational amplifier is ideal.
The output will change from + 15 V to 15 V when the instantaneous value
of the input sine wave is
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PAGE 458
CHAP 8
For the circuit shown in Figure, the boolean expression for the output Y in
terms of inputs P, Q, R and S is
(A) P + Q + R + S
(B) P + Q + R + S
(C) (P + Q ) (R + S )
(D) (P + Q) (R + S)
MCQ 8.106
MCQ 8.107
MCQ 8.108
(B) 1.1 mA
(C) 1.20 mA
(D) 1 mA
(B) 14 Volt
Value of resistance RF is
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CHAP 8
PAGE 459
(A) 110.9 k
(B) 124.5 k
(C) 130.90 k
MCQ 8.109
MCQ 8.110
MCQ 8.111
Vy
of the first network is
Vx
(A)
jCR
(1 R2 C 2) + j3CR
(B)
jCR
(1 R2 C 2) + j2CR
(C)
jCR
1 + j3CR
(D)
jCR
1 + j2CR
(B)
1
2RC
Value of RF is
(A) 1 k
(B) 4 k
(C) 2 k
(D) 8 k
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PAGE 460
MCQ 8.112
MCQ 8.113
CHAP 8
(A) 7
(B) 5
(C) 4
(D) 8
*In Figure , the ideal switch S is switched on and off with a switching
frequency f = 10 kHz . The switching time period is T = tON + tOFF s.
The circuit is operated in steady state at the boundary of continuous and
discontinuous conduction, so that the inductor current i is as shown in
Figure. Values of the on-time tON of the switch and peak current ip . are
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CHAP 8
PAGE 461
that the capacitance C has a finite value which is large enough so that the
voltage. VC has negligible ripple, calculate the following under steady state
conditions, in terms of D , I and R
MCQ 8.114
MCQ 8.115
The average output voltage V0, with the polarity shown in figure
(B) I D2 T
(A) I T
C
2C
(C) I (1 DT)
(D) I (1 D) T
2C
2C
YEAR 2001
MCQ 8.116
ONE MARK
(A) increase
(B) decreases
(C) is unaffected
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PAGE 462
MCQ 8.117
CHAP 8
MCQ 8.118
The output of a logic gate is 1 when all its inputs are at logic 0. The
gate is either
(A) a NAND or an EX-OR gate
(B) a NOR or an EX-OR gate
(C) an AND or an EX-NOR gate
(D) a NOR or an EX-NOR gate
MCQ 8.119
MCQ 8.120
(A) xy + x
(B) x + y
(C) x + y
(D) xy + x
YEAR 2001
MCQ 8.121
TWO MARKS
For the oscillator circuit shown in Figure, the expression for the time period
of oscillation can be given by (where = RC )
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CHAP 8
MCQ 8.122
(A) ln 3
(B) 2 ln 3
(C) ln 2
(D) 2 ln 2
MCQ 8.123
MCQ 8.126
(D) 2.5 A
MCQ 8.125
(D) 4
MCQ 8.124
PAGE 463
(D) 3.0
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PAGE 464
CHAP 8
MCQ 8.127
(A) 4
(B) 15
(C) 7
(D) 6
*For the op-amp circuit shown in Figure, determine the output voltage vo .
Assume that the op-amps are ideal.
(A) 8 V
7
(B) 20 V
7
(C) 10 V
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CHAP 8
MCQ 8.128
MCQ 8.129
PAGE 465
(D) 1
What is the required value of CE for the circuit to have a lower cut-off
frequency of 10 Hz
(A) 0.15 mF
(B) 1.59 mF
(C) 5 F
(D) 10 F
MCQ 8.130
MCQ 8.131
************
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PAGE 466
CHAP 8
SOLUTION
SOL 8.1
F = XY + XY
1prime
44 2
44 3
implicants
SOL 8.2
So,
SOL 8.3
(Assumption is true)
Y = 1, when A > B
A = a1 a 0, B = b1 b 0
a1
a0
b1
b0
Total combination = 6
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CHAP 8
SOL 8.4
PAGE 467
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PAGE 468
VC 100IB 0.7 = 0
VC = 100IB + 0.7
IC - IE = 13.7 VC = ( + 1) IB
12k
13.7 VC = 100I
B
12 # 103
Solving equation (i) and (ii),
CHAP 8
...(i)
...(ii)
IB = 0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current source.
100
= 0.04 s
gm = =
r 2.5 # 1000
Writing KCL at output node
v0 + g v + v0 v = 0
m
RC
RF
v 0 : 1 + 1 D + v :gm 1 D = 0
RC RF
RF
Substituting RC = 12 k, RF = 100 k, gm = 0.04 s
v 0 (9.33 # 105) + v (0.04) = 0
v 0 = 428.72V
Writing KCL at input node
vi = v + v + v vo = v 1 + 1 + 1 v 0
:
Rs
Rs r
RF
Rs r RF D RF
= v (5.1 # 104) v 0
RF
Substituting V from equation (i)
...(i)
vi = 5.1 # 104 v v 0
0
428.72
Rs
RF
vi
6
5
3 = 1.16 # 10 v 0 1 # 10 v 0 Rs = 10 k (source resistance)
10 # 10
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CHAP 8
PAGE 469
vi
= 1.116 # 105
10 # 103
1
Av = v 0 =
- 8.96
vi
10 # 103 # 1.116 # 105
SOL 8.6
If A = 0,
If A = 1,
So state diagram is
SOL 8.7
X 0 = Q , X1 = Q
(toggle of previous state)
0 Vi (j) 0 Vo (j)
=0
+
1 +R
R2
1
j C
Vo (j)
Vi (j)
=
1 +R
R2
1
j C
Vo (j) =
At " 0 (Low frequencies),
At " 3 (higher frequencies),
Vi (j) R2
R1 j 1
C
1 " 3, so V = 0
o
C
1 " 0, so V (j) = R2 V (j)
o
R1 i
C
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PAGE 470
2
2
H (3) =
=
R1
R1
At 3 dB frequency, gain will be
So,
H ^ j0h = 1 H (3)
2
R2
R2
1
=
b
l
2 R1
R 12 + 21 2
0 C
2R 12 = R 12 +
0 =
SOL 8.8
1 & R2 = 1
1
C2
2C 2
2
0
1
R1 C
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CHAP 8
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CHAP 8
SOL 8.9
PAGE 471
SOL 8.10
Y = X5X
= X X + XX
= XX + X X
= X+X = 1
SOL 8.11
& HL = HL + DE
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PAGE 472
CHAP 8
= LP + 3 + DE
PUSH H
& The last two value of the stack will be HL value i.e,
LP + DISP + 3
SOL 8.12
We can see that both BE and BC Junction are forwarded biased. So the
BJT is operating in saturation.
Collector current IC = 12 0.2 = 5.36 mA
2.2k
Y IB
Note:- In saturation mode IC SOL 8.13
J = QB ; K = QB
The output of JK flip flop
QA (n + 1) = QB QA + QB QA = QB (QA + QA) = QB
Output of T flip-flop
QB (n + 1) = Q A
Clock pulse
QA
QB
QA (n + 1)
QB (n + 1)
Initially(tn )
tn + 1
tn + 2
tn + 3
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CHAP 8
SOL 8.14
PAGE 473
The output
vo = 0.7 V
2. When 0.7 1 vi # 5.7 , both zener and diode D will be off. The circuit is
vo = 5 + 0.7 = 5.7 V
SOL 8.15
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PAGE 474
CHAP 8
2 + (2 vo) = 0
R
2R
4 + 2 vo = 0
vo = 6 volt
SOL 8.16
10
10
10 + 10 #
= 5 volt
SOL 8.17
So,
...(1)
IC - IE = IB
V0 = 100I
B
100
V0
IB =
10 # 103
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CHAP 8
10 (10 # 103)
&
SOL 8.18
PAGE 475
V0
0.7 V0 = 0
10 # 103
9.3 2V0 = 0
V0 = 9.3 = 4.65 A
2
Output Y is written as
Y = X5B
Since each gate has a propagation delay of 10 ns.
SOL 8.19
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PAGE 476
SOL 8.20
CHAP 8
F = X Y + YZ
SOL 8.21
SOL 8.22
SOL 8.23
SOL 8.24
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CHAP 8
PAGE 477
Feedback samples output voltage and adds a negative feedback voltage (vfb)
to input.
So, it is a voltage-voltage feedback.
SOL 8.25
Option () is correct.
NOR and NAND gates considered as universal gates.
SOL 8.26
SOL 8.27
SOL 8.28
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PAGE 478
SUB B &A
A
B
2s complement of ( B)
A + ( B) = A B
SOL 8.29
= AB
= 00000000
= 1111 0 0 0 0
= 0 0 010 0 0 0
= 0 0 010 0 0 0
= 10 H
SOL 8.30
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CHAP 8
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CHAP 8
PAGE 479
V0 = 10 sin t # 10 = 5 sin t
10 + 10
Due to resistor divider, voltage across diode VD < 0 (always). So it in reverse
bias for given input.
Output,
V0 = 5 sin t
Output voltage
SOL 8.31
This is a current mirror circuit. Since is high so IC1 = IC2, IB1 = IB2
VB = ( 5 + 0.7)
= 4.3 volt
Diode D1 is forward biased.
So, current I is,
I = IC2 = IC1
0 ( 4.3)
=
= 4.3 mA
1
SOL 8.32
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PAGE 480
CHAP 8
Option () is correct.
Let input Vin is a sine wave shown below
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CHAP 8
PAGE 481
To get output V0
V0 = K ( VP + VQ)
K gain of op-amp
So, P should connected at inverting terminal of op-amp and Q with noninverting terminal.
SOL 8.34
Option () is correct.
SOL 8.35
a R1 = R 2 = R A
Similarly,
vA vi + vA 0 = 0
R3
R4
2vA = vin ,
a R 3 = R 4 = RB
So,
vo = 0
It will stop low frequency signals.
For high frequencies,
" 3 , then 1 " 0
C
Equivalent circuit is,
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PAGE 482
Output,
vo = vi
So it will pass high frequency signal.
This is a high pass filter.
SOL 8.36
A
AC
2
C
2
L = 2h
When both the circuits are connected together, equivalent circuit is,
SOL 8.37
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CHAP 8
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CHAP 8
PAGE 483
F = X Z + Y Z + XYZ
In POS form
F = (Y + Z) (X + Z) (X + Y + Z )
Since all outputs are active low so each input in above expression is
complemented
F = (Y + Z ) (X + Z ) (X + Y + Z)
SOL 8.38
SOL 8.39
100
IB 1 IB(sat), so transistor is in forward active region.
IB(sat) =
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VCE - 0
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PAGE 484
SOL 8.40
CHAP 8
` IC - IE = 0.6 amp
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CHAP 8
PAGE 485
v1 c R1 + R2 m = V
R1
R1 R2
R2
R1 + R2 m
Since the op-amp is ideal therefore
iL = i1 = v1 = V c R2 m
r R1 + R2
r
v1 = V c
SOL 8.42
SOL 8.43
Option () is correct.
This is a class-B amplifier whose efficiency is given as
= VP
4 VCC
where VP " peak value of input signal
VCC " supply voltage
here VP = 7 volt, VCC = 10 volt
so,
SOL 8.44
So at any time t , voltage across capacitor (i.e. at inverting terminal of opamp) is given by
vc (t) = vc (3) + [vc (0) vc (3)] e
-t
RC
-t
RC
vc (t) = 20 (1 e )
Voltage at positive terminal of op-amp
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PAGE 486
CHAP 8
v+ vout v+ 0
=0
+
10
100
v+ = 10 vout
11
Due to zener diodes, 5 # vout # + 5
So,
v+ = 10 (5) V
11
Transistor form 5 V to + 5 V occurs when capacitor charges upto v+ .
So
20 (1 e - t/RC ) = 10 # 5
11
1 e - t/RC = 5
22
17 = e - t/RC
22
t = RC ln ` 22 j = 1 # 103 # .01 # 10 - 6 # 0.257 = 2.57 sec
17
Voltage waveforms in the circuit is shown below
SOL 8.45
SOL 8.46
(AB.CD) H = (253.632) 8
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CHAP 8
PAGE 487
RA = RB
TC = TD
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PAGE 488
CHAP 8
Since there is no feed back to the op-amp and op-amp has a high open loop
gain so it goes in saturation. Input is applied at inverting terminal so.
VP = VCC = 12 V
In negative half cycle of input, diode D1 is in forward bias and equivalent
circuit is shown below.
SOL 8.49
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CHAP 8
Output,
PAGE 489
Vo = 10 volt
Output,
Vo = Vi
Transfer characteristic of the circuit is
SOL 8.50
=0
= 20 # 5 36 , Vi = 5 V
= 2.78 V
= 15 K || 100 K
= 13.04 K
So the circuit is
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PAGE 490
CHAP 8
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CHAP 8
PAGE 491
node equation
Vth + 12 + Vth 0 = 0
2
10
5 Vth + 60 + Vth = 0
Vth = 10 volt (negative threshold)
So the capacitor will discharge upto 10 volt.
At terminal P voltage waveform is.
SOL 8.52
Option () is correct.
SOL 8.53
Option () is correct.
SOL 8.54
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PAGE 492
SOL 8.55
CHAP 8
XCHG&
SOL 8.57
Voltage Vn is given by
Vn = 1 # 2 = 2 Volt
Vp = 0
Vn > Vp (so diode is in reverse bias, assumption is true)
Current through D2 is ID2 = 0
SOL 8.58
SOL 8.59
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CHAP 8
PAGE 493
Due to 10 V source VDS > VDS(sat) so the NMOS goes in saturation, channel
conductivity is high and a high current flows through drain to source and it
acts as a short circuit.
So,
Vab = 0
SOL 8.60
and
Q (t + 1) = D
= Q (t) 5 X
= Q (t) X + Q (t) X
= Q (t), if X = 1
Q (t + 1) = Q (t), if X = 0
100
SOL 8.62
R1 = 1 # 10
Av
Av = 10 to 25 so value of R1
6
R1 = 10 = 100 k
10
for Av = 10
6
R1' = 10 = 40 k
25
for Av = 25
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CHAP 8
SOL 8.64
SOL 8.65
CHECK
SOL 8.66
SOL 8.67
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CHAP 8
SOL 8.69
(2 1) mA
= 1 mS
(2 1) V
So,
Voltage gain
SOL 8.70
PAGE 495
vo = gm vgs RD
vgs = vin
vo = gm RD vin
Av = vo = gm RD = (1 mS) (10 k) = 10
vi
In the circuit
V1 = 3.5 V (given)
Current in zener is.
IZ = V1 VZ = 3.5 3.33 = 2 mA
RZ
0.1 # 10
SOL 8.71
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PAGE 496
CHAP 8
IR = IC2 c1 + 2 m
IR
IC2 = I =
2
c1 + m
IR can be calculate as
a IB1 = IB2
So,
SOL 8.72
IR = 5 + 03.7 = 4.3 mA
1 # 10
4. 3
I =
- 4.3 mA
2
1
+
`
100 j
Here the feedback circuit samples the output voltage and produces a feed
back current Ifb which is in shunt with input signal. So this is a shunt-shunt
feedback configuration.
SOL 8.73
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CHAP 8
SOL 8.74
PAGE 497
SOL 8.75
Here
RB = (10 k < 10 k) = 5 k
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PAGE 498
CHAP 8
gm = 10 ms
50
a gm r = & r =
= 5 k
10 # 10 - 3
Input resistance
Rin = RB < r = 5 k < 5 k = 2.5 k
SOL 8.77
= 3 Volt
<3
<3
<3
< ID R
> 1,
VSD
VS VD
4 ID R
1
ID R
R > 1000
ID = 1 mA
SOL 8.78
Option () is correct.
SOL 8.79
Option (B is correct.
If op-amp is ideal, no current will enter in op-amp. So current ix is
v vy
...(1)
ix = x
1 # 106
(ideal op-amp)
v+ = v = vx
vx vy
+ vx 0 3 = 0
3
100 # 10
10 # 10
vx vy + 10vx = 0
11vx = vy
For equation (1) & (2)
ix = vx 11v6 x = 10v6x
1 # 10
10
Input impedance of the circuit.
6
Rin = vx = 10 = 100 k
10
ix
...(2)
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CHAP 8
SOL 8.80
PAGE 499
SOL 8.81
SOL 8.82
SOL 8.83
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PAGE 500
times.
HALT " 1-instruction cycle.
=0
=0
= 1.35
= 1.35
"a V0 = 5 IC RC
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CHAP 8
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CHAP 8
PAGE 501
SOL 8.85
SOL 8.86
a IE = (hfe + 1) IB
4 (33 # 103) IB 0.7 (3.3 # 103) (hfe + 1) IB = 0
3.3 = 6(33 # 103) + (3.3 # 103) (99 + 1)@ IB
3.3
IB =
33 # 103 + 3.3 # 103 # 100
IC = hfe IB
99 # 3.3
3.3
=
mA =
mA
[0.33 + 3.3] # 100
0.33 + 3.3
SOL 8.87
..(1)
Similarly,
v+ vin
v 0
=0
+ +
R
1
c jC m
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PAGE 502
v+ vin + v+ (jCR)
v+ (1 + jCR)
By equation (1) & (2)
2vin
1 + jCR
2
1E
vin ;
1 + jCR
CHAP 8
=0
= Vin
..(2)
"a v+ = v- (ideal op-amp)
= vin + vout
= vout
vout = vin
(1 jCR)
1 + jCR
= 2 tan - 1 (CR)
=
Cin
Sum
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CHAP 8
SOL 8.90
PAGE 503
'
ID' = K (VGS
VTH ) 2
'
ID' = 1 (VGS
2) 2
4
'
'
VGS
= VDS
= 10 ID' # RD' = 10 4ID'
So,
4ID' = (10 4ID' 2) 2 = (8 4ID' ) 2
= 16 (2 ID' ) 2
ID' = 4 (4 + I'D2 4ID' )
4I'D2 17 + 16 = 0
I'D2 = 2.84 mA
SOL 8.91
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PAGE 504
SOL 8.92
CHAP 8
...(1)
vx + vx vout + 10vx = 0
12 vx = vout
vx = vout
12
vin + vx = 0
1
10
vin = vout
120
vout = 120
vin
Vout = + 4 Volt
In the negative half cycle diode D1 conducts and D2 will be off so the circuit
is,
Applying KVL
Vin 10I + 4 10I = 0
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CHAP 8
PAGE 505
Vin + 4 = I
20
Vin = 10 V (Maximum value in negative half cycle)
So,
I = 10 + 4 = 3 mA
20
10
Vin Vout = I
10
10 Vout = 3
10
10
Vout = (10 3)
Vout = 7 volt
SOL 8.93
Frequency
...(1)
...(2)
and
SOL 8.94
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PAGE 506
CHAP 8
= Y Z + Y (X + X ) (X + Z )
= Y Z + Y (X + Z )
= Y Z + YX + YZ
SOL 8.95
X = X1 5 X 0 , Y = X 2
Serial Input Z = X 5 Y = [X1 5 X0] 5 X2
Truth table for the circuit can be obtain as.
Clock pulse
Serial Input
Shift register
Initially
1010
1101
0110
0011
0001
1000
0100
7
1
1010
So after 7 clock pulses contents of the shift register is 1010 again.
SOL 8.96
Qn
Qn+1
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CHAP 8
PAGE 507
SOL 8.98
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PAGE 508
CHAP 8
SOL 8.101
Vm
(Vm /)
=
=
rf + R
(5 + 45)
= Vm
50
Vo = VD + Vz
= 0.7 + 3.3
= 4 Volt
In the negative halt cycle, zener diode (Dz ) is in forward bias and diode (D)
Output
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CHAP 8
PAGE 509
10 # 1
(1 + 1)
Vo = 5 Volt
SOL 8.102
SOL 8.103
Transfer function
V0 (j)
1
1
=
# 1 =
j
cR
+1
V1 (j)
1
j
C
R+
j C
H (j1) = 0.25
H (j) =
Given that
1
=1
4
12 C2 R2 + 1
16 = 12 R2 C2 + 1
12 R2 C2 = 15
42 f12 (50) 2 (5 # 10 - 6) 2 = 15
f 1 = 2.46 kHz
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PAGE 510
SOL 8.104
CHAP 8
SOL 8.105
a AB = A + B
99 (1 mA) = 0.99 mA
I =
IC =
( + 1) E
(99 + 1)
In the circuit
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CHAP 8
PAGE 511
In the circuit
VBE = 0.7 V
VE = IE # 1 k
=1V
VB VE = 0.7
VB = 0.7 + 1 = 1.7 volt
Current throughR1
IR = VB = 1.7 = 100 A
17 k
17 k
IB = IE = 1 mA = 10 A
+1
(99 + 1)
Current through RF , by writing KCL at Base
1
IRF = IB + IR1
= 10 + 100 = 110 A
Current through RC
I1 = IC + IRF = 0.99 mA + 110 A = 1.1 mA
SOL 8.107
SOL 8.108
SOL 8.109
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PAGE 512
CHAP 8
Va Vx + V Cs + (V V ) Cs = 0
a
a
y
R
Va (1 + 2RCs) Vx sCRVy = 0
or
(Vy Va) Cs +
or
Vy
=0
R
or
Vy (1 + sCR) Va sCR = 0
From equation (1) & (2)
1 + sCR
c sCR m (1 + 2sCR) Vy Vx sCRVy = 0
(1 + sCR) (1 + 2sCR)
Vy ;
sCR E = Vx
sCR
Vy
...(1)
...(2)
Transfer function
Vy
sCR
=
Vx
1 + 3sCR + s2 C2 R2
jCR
jCR
T (j) =
=
2 2 2
2 2 2
1 + j3CR C R
(1 C R ) + 3jCR
T (s) =
SOL 8.110
SOL 8.111
Vy =
T (j)
So,
Vy
V0
R
RF + R
RF = 2R = 2 # 1 = 2 k
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CHAP 8
SOL 8.112
PAGE 513
Q2
Q1
Q0
Initially
1
0
1
All flip flops are reset. When it goes to state 101, output of NAND gate
becomes 0 or CLR = 0, so all FFs are reset. Thus it is modulo 4 counter.
SOL 8.113
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PAGE 514
CHAP 8
SOL 8.114
i p = 106 # TON
= 63.33 # 10 6 # 106 = 63.33 A
&
Initially
At
Duty cycle
I = C dVc
dt
Vc = I t + Vc (0)
C
Vc (0) = 0
Vc = I t
C
t = Toff
Vc = I Toff
C
TON
D =
= TON
TON + TOFF
T
TON = DT
TOFF = T TON = T DT
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CHAP 8
PAGE 515
Vc = I (T DT)
C
= I (1 D) T
C
During TOFF , output voltage V0 = 0 volt .
So,
SOL 8.115
I2 = C I
C
V0 = Vc = I t
C
Average output voltage
DT = T
I
V0 = 1 ; #
bC t l dt +
T 0
ON
TOFF
#0
0 dtE
2 DT
2
2
2
= 1 . I :t D = 1 . I . D T = I D .T
2
T C 2 0
T C
C 2
SOL 8.116
In the circuit
ib = vs
hie
...(1)
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CHAP 8
h R
Voltage gain Av = vo = fe C
vi
hie
Equivalent hybrid circuit when RE is not bypassed by the capacitor.
1
In the circuit
vs = ib hie + (ib + hfe ib) RE
vs = ib [hie + (1 + hfe) RE ]
v0 = hfe ib .RC
from equation (2) and (3)
...(2)
...(3)
vs
hie + (1 + hfe) RE
hfe RC
Voltage gain,
Av2 = v0 =
vs
hie + (1 + hfe) RE
Av1 = hie + (1 + hfe) RE = 1 + (1 + hfe) RE
So
hie
hie
Av2
v0 = hfe .RC
Av < Av
2
SOL 8.117
SOL 8.118
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CHAP 8
SOL 8.119
So,
SOL 8.120
SOL 8.121
=
So,
SOL 8.122
PAGE 517
v+
=1
vo
2
J1 + 1 N
2 O = 2 ln 3
T = 2 ln KK
1
K1 OO
2P
L
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PAGE 518
CHAP 8
BACK :
NOP
ADDB & Adds contents of register B to accumulator and result stores in
accumulator
A = A + B = (10) H + (10) H
000 10000
ADD 0 0 0 1 0 0 0 0
A=001 00000
= (20) H
RLC & Rotate accumulator left without carry
A = (A0) H
JNC BACK
NOP
ADDB & A = A + B
= (A0) H + (10) H
1010 0000
ADD 0 0 0 1 0 0 0 0
A=1011 0 0 0 0
A = (B0) H
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CHAP 8
PAGE 519
CY = 1 So it goes to HLT.
therefore NOP will be executed 3 times.
SOL 8.123
SOL 8.124
SOL 8.125
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PAGE 520
SOL 8.126
CHAP 8
Option () is correct.
The circuit is a synchronous counter.
Where input to the flip flops are
D3 = Q3 + Q2 + Q1
D2 = Q3 , D1 = Q2 , D 0 = Q1
Truth table of the circuit can be drawn as
CLK
Q3
Q2
Q1
Q0
Initial state
8
1
0
0
0
From the truth table we can see that counter states at N = 4 and N = 8 are
same. So mod number is 4.
SOL 8.127
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...(1)
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CHAP 8
4v1 vo = 0
At the negative terminals of op-amp-2
1 v2 + 1 vo = 0
m
c
m c
4
8
...(2)
2 2v2 1 vo = 0
vo + 2v2 = 3
From equation (1) and (2)
3 vo 2v2 = 1
4
From equation (3)
3 v 2 ( 3 v ) = 1
o
4 o
3 v + v = 5
o
4 o
7 v = 5
4 o
vo = 20 volt
7
SOL 8.128
...(3)
PAGE 521
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PAGE 522
So gain
SOL 8.129
Av =
CHAP 8
200 # (1 k)
= 6.62
(25 k + 5.2 k)
f0 =
1
2Req CE
RE (RB + r)
RE + RB + r
1 (RE + RB + r)
f0 =
= 10 Hz (given)
2RE (RB + r) CE
Req = RE < RB + r =
So
So,
SOL 8.130
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CHAP 8
PAGE 523
vo = R2 vi
R1
So it does pass the high frequencies. This is a high pass filter.
SOL 8.131
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