2EI5 Project 4

MOSFET based XOR Gate Group 39

Giuseppe Querques
Mashal Sharfaz

Design Considerations:

According to the rules discussed in module 7:

1) an OR gate is modeled as a parallel NMOS circuit.
2) An AND gate is modeled as a series NMOS circuit
3) Not implimentation is provided by the dual of the NMOS circuitry with PMOS transistor.
According to these rules, with the understanding that a XOR gate is modeled by the function
(Anot*B)+(A*Bnot), the following diagram was derived using MOSFET transistors:

An initial design was implemented using twelve MOSFETs, but pspice cannot handle more than 10
MOSFET units for the purposes of simulation. Therefore a new design needed to be constructed.
Furthermore a pulse source was used to model A and B inputs, however, it overcomplicated the design.
Instead, four Digiclocks were used to model A, B, Anot, and Bnot for ease of use. The period of the A
inputs are twice as long as the period of the B inputs to simulate a 2 bit binary clock going through the
digits 00, 01, 10, 11.
From the data sheets for our ALD1115, capacitance was found to be 3 picofarad, Vto(p)=-1, Vto(n)=1,
kn=1.8, kp=0.67

Old Design (Too many MOSFETs, used A and B Pulse Sources):

New Design (Implementing 8 MOSFETs, and 4 Digiclocks for A, Anot, B, Bnot):

New Design Netlist:

Results:

The results are correct as per XOR operations:

From 0-0.5 us we have 00 -> false -> 0V

From 0.5-1.0 us we have 10 -> true -> 5V

From 1.0-1.5 us we have 01 -> true -> 5V
From 1.5-2.0 us we have 11 -> false -> 0V
Dynamic Power Consumption:
Since power for a single switiching operation is P = Cl*Vdd^2*f(0->1);
Dynamic power consumption is found to be Cl*((Vdd^2)/2)*f(clk)*sw; (where sw is the average
switching factor). For our clock, Ceff = 3/16 * Cl (since our transition probability is chance of getting a
0, and a chance of getting a 1 from the clock output 0.75 * 0.25 = 3/16 = switching factor).
Dynamic power consumption = (3x10^-12 F)*(5^2 V)* (500k Hz) * (3/16) = 7.03*10-6 W