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Mitsubishi Melsec PLC Ladder Logic Application
Mitsubishi Melsec PLC Ladder Logic Application
Mitsubishi Melsec PLC Ladder Logic Application
- 1 -
Content
I. The Structure and Understanding of PLC.
The Instruction and History of PLC.
Digital Input Module.
Digital Output Module.
Terminologies of Ladder Logic.
The Relationship between PLC Hardware and Software
Numeric System of PLC.
Karnaugh Map
II. Application Examples for Logical Command.
Logical AND
Logical OR
Logical NAND
Logical NOR
Logical Exclusive OR
1 Scan-time Oscillator
Self-Holding, 0 or 1 Dominant SR/RS Flip-Flop
Detect Rising Edge / Falling Edge, Differentiation
Dual action Pushbutton
Trouble Acknowledge/ Reset
III. Application Example for Sequential Command.
On Delay / Off Delay Timer
One Shot Multi-vibrator
Multi-Vibrator
Speed Monitor using OFF Delay Timer
Preventing Chattering Noise for Mechanical Contacts
Finding Stable Value by TIME Filter from Analog Input Hunting
Measuring Time for Continuous Production.
Optimizing Surveillance Timer of Speed Monitor
Surveillance of Motor Drive System
Detecting Value Changed
- 2 -
- 3 -
Appendix
MODICON Concept Version 2.1 PID Simulation Function Block Diagram
Bit Division for MMI Analog tag
SIMATIC TI545 PLC PID Simulation
SIMATIC TI545 PLC vs Intouch 8.0
Modicon E785 PLC vs Intouch 7.1 PID Simulation
- 4 -
- 5 -
PLC are
manufactured more compact and lower cost and applied to almost industrial fields. When
users control the machine or equipment with PLC, users ought to make a program so that
PLC can decide memory content of control algorism. The standards Methods of PLC
Programming are presented but there are many differences according to Manufacturers and
kinds. IEC 1131-3(International Electro-technical Commission- Standard for Programmable
Controllers-Part 3: Programming Languages)
language as belows;
- LD(:Ladder diagram)
- IL(mnemonic :Instruction List)
- SFC(Sequential Function Charts)
- 6 -
defined
international standards of
PLC
Input Polling
LOGIC
SCAN
Output Processing
System Processing
- 7 -
- 8 -
to convert from analog value to digital value is represented as the figure shows that digital
value corresponding to analog voltage signal as below. The input voltage range, output bits of
A/D converter are different according to kinds. The resolution of AD converter is determined
by output bits.
256
Digital Value
102
0
2V
0V
5V
Analog DC Voltage
Resolution= 2 = 256
If analog input voltage varies from 0V to 5V, output digital value will be varied from 0 to 255.
discriminal minimum variation voltage to change Digital value is;
VIMIN = 5 / 256 = 0.019531 , and
Digital value= 2V / 0.019531V = 102.4 = 102
F. Analog Output Unit (D/A Converter)
This unit is for Digital/Analog conversion and used to output analog signal form CPU to
outside. The principal to convert from analog value to digital value is that output digital value
N
is corresponded to analog value. The resolution is proportional to the bit numbers to input(2 ),
the output digital value will be converted to analog value from 0V to maximum reference
voltage.
Let's find analog value corresponding to digital value 102 if analog value is 0-5V voltage, the
resolution is 256, the voltage difference is 5V. Therefore the variation of digital 1 results
variation of analog signal 0.019531V(5/ 256). and we find 102 x 0.019531V 2 V calculation
result.
- 9 -
- 10 -
PID Unit is not used alone, but used together with analog input unit and analog output unit.
H. High speed Counter Unit
The counter in the CPU has nearly scan time below several ms for the CPU is scanning the
program. For this reason, CPU cannot count the pulse shorter than this scan time. Therefore
high speed counter unit operates separately with CPU, counts pulse as dedicated I/O unit. Also
high speed Counter Unit has comparing output function between set value and present value of
counter. It provides up and down counter and is used to detect position like the CNC machine.
I. Positioning Unit
The positioning Unit is used for precise motor control like Servo-Motor, Stepping Motor. This
unit will be applied to positioning decision of X-Y table, provides various operation patterns
like constant speed, acceleration, deceleration.
3. Data Link Methods.
It is commonly demanded the PLC has data exchanges between distributed remote I/O group,
different PLC system, high level computer. The data link unit can reduce or eliminate I/O points
and bulk cable installation, intends to
management, monitoring system. The data link unit has function for data collecting of PLC,
extended I/O group.
C e ll L e v e l
F ie ld L e v e l
- 11 -
P24
Sink Type
A
Digital Input
Module
N24
- 12 -
P24
Source Type
Digital Input
Module
N24
C. In case of that proximity switch of PNP Open-Collector Type is connected to sink type
digital input module .
P24
Proximity
Switch
PNP OpenofCollector
PNP
Open
Type
Collector
Switch
Type
Sink Type
A
Digital Input
Module
N24
N24
- 13 -
D. In case of that proximity switch of NPN Open-Collector Type is connected to source type
digital input module .
P24
Source Type
Digital Input
Module
P24
Proximity
NPN
OpenSwitch
Collector
of NPN
Type
Open
Switch
Collector
Type
N24
- 14 -
P24
A
Sink Type
Digital Output
Module
N24
- 15 -
P24
Source Type
Digital Output
Module
N24
AC HOT
A
Relay Type
Digital Output
Module
NEUT
- 16 -
AC HOT
A
SSR Type
Digital Output
Module
NEUT
This module includes TRIAC(a kind of semiconductor with large electric capacity) what we
call "SSR (Solid State Relay)", this semiconductor drives output device, once input signal
excites to signal gate, even gate signal is removed, turn-on state of SSR in the main driving
line will go on until main line current driving output device is ZERO. Therefore we cannot use
in the DC current that not to return to Zero current but can use in the AC current that crossing
zero voltage.
Gate
- 17 -
and
Internal
Address
Internal
Address
Internal
Address
Internal
Address
Internal &
External
Address
Description
Remarks
Bit
Address
Bit
Address
Bit
Address
Bit
Address
Bit
Address
Bit
Address
Bit
Address
Word
Address
- 18 -
Device I/O Address can be divided to internal address and external address. The external is
allocated and related to real hardware I/O module, the internal address is used only in the
program logic.
B. Identification of Device I/O Address.
Device I/O Address consists of Identifier and decimal number or hexadecimal number. For
example,
NULL
UC24
DO 16pt
DO 32pt
DI 32pt
DI 16pt
U
P
C
POWER
X060-Y07F
Y040-Y05F
Y030-Y03F
X010-X02F
X000-X00F
- 19 -
D. Rung
Rung can be represented to grouping of input condition and output task. If this group is
continuous, not separated, this group can be called " Rung".
E. Step
The step is represented to Word Number consisting of Instruction, and we can calculate total
program memory size.
- 20 -
P24
PLC Internal
LogicLogic
PLC
PLC
External
Circuit
PLC
X000
Instruction
X000
Y010
X000
Power Flow
N24
Power
Power
Rail
Left
Rail
Right
The current from power P pole cannot flow to PLC input module address X000 because of
opening of pushbutton switch(NO: Normal Open state) in the electrical circuit. This is to say, at
the input point addressed to X000 of input module, there exists not external electrical excitation,
we can say this "Electrically Dry State". Otherwise, in the PLC inside, NO(Normal Opened)
contact of un-identified X000(not excited because of opening of pushbutton switch) can not
make power flow proceed, so this NO contact is electrically OFF state. But in the PLC inside,
NC(Normal Closed) contact of un-identified X000 can proceed power flow, so this contact is
electrically ON state.
- 21 -
P24
PLC
External
Circuit
PLC
PLC Internal
PLCLogic
Logic
Instruction
X000
X000
Y010
Power Flow
X000
N24
Power
Power
Rail
Left
Rail
Right
Now by pressing the A contact of Push-Button Switch, there exists electrical excitation at the
X000 and we can say this "Electrically Wet State". In the PLC Logic, NO(Normal Opened)
contact of identified X000(excited because of closing of pushbutton switch) can proceed power
flow and change to closed state, so this NO contact is electrically ON state. But in the PLC
inside, NC(Normal Closed) contact of identified X000 can not make power flow proceed and
changed to opened state, so this contact is electrically OFF state.
Totally, we can say them as follows;
Electrical State
Lamp Status
INPUT point
OFF
OFF
ON
ON
Possibility to pass
NO(Normal
NC(Normal
NO(Normal
NC(Normal
- 22 -
Open)
Close)
Open)
Close)
No
Yes
Yes
No
Instruction
X000
X000
P24
Y010
Y011
Y010
Power
Power
Rail
Left
Rail
Right
Source Type
Digital Output
Module
Relay 010
Relay 011
Y011
N24
If Y010 Coil Instruction in the PLC internal Logic is Energized, the Relay 010 connected to
addressed Y010 of Digital Output Module is also Energized. Otherwise if Y011 Coil Instruction
in the PLC internal Logic is De-energized, the Relay 011 connected to addressed Y011 of Digital
Output Module is also De-energized.
- 23 -
Data Unit
Bit
Nibble
Digit
Byte
Decimal
Binary
Octal
Hexadecimal
0
0
0
0
1
1
1
1
2
10
2
2
3
11
3
3
4
100
4
4
5
101
5
5
6
110
6
6
7
111
7
7
8
1000
10
8
9
1001
11
9
10
1010
12
A
11
1011
13
B
12
1100
14
C
13
1101
15
D
14
1110
16
E
15
1111
17
F
16
10000
20
10
17
10001
21
11
18
10010
22
12
19
10011
23
13
20
10100
24
14
Numbers in Decimal, Binary, Octal and Hexadecimal
In the each numeric system, even it's basic numeric system is different, existing real
value will not be changed. Now from here, let's consider for numeric system and
conversion between the different systems needed to understanding the instruction used
in the PLC(Programmable Logic Controller).
- 24 -
2. Numeric System
A. Binary Numeric System
Binary number is commonly used in the computer. 1 digit of binary number will be
regarded as the state of 1 electric wire, if the voltage on the wire is ON state, it's bit
value is 1, if the voltage on the wire is OFF state, it's bit value is 0. If two wires
are used, bits will be generated asa well as wires number used. The following figure
is represented that 10 decimal number equivalent to each binary numbers, minimum
number is positioned from right side. Minimum number is 1, and position number is
0. The way to find from binary number to decimal number is changing the position
number to exponent number of 2 and converting to decimal number, adding all each
values. As this way, the conversion from other numeric system to decimal number is
possible.
6
2 =64
2 =32
2 =16
2 =8
2 =4
2 =2
2 =1
1 1 1 0 0 0 1
6
1(2 )= 64
In every numeric system, the
1(25)= 32
4
1(2 )= 16
1(2 )= 8
1(2 )= 4
1
1(2 )= 2
1(2 )= 1
-----113
Conversion of a Binary Number to a Decimal Number
- 25 -
Decimal number can be converted to binary number by dividing as next example. This
method is also applied to convert from decimal number to any numeric system. The
quota value after dividing decimal number by 2 will be MSD(Most significant
number), after dividing remained decimal number by 2 again will be next significant
digit fo binary number. With this way, until total number becomes zero final binary
number will be found.
to begin decimal
number 932
to binary
(Base 2)
932
2
= 466 0
2(0.0)=0
466
2
= 233 0
2(0.0)=0
233
= 116 5
2
2(0.5)=1
116
= 58 0
2
2(0.0)=0
58
2
= 29 0
2(0.0)=0
29
2
= 14 5
2(0.5)=1
14
2
= 7
2(0.5)=0
7
2
= 3
2(0.5)=1
3
2
= 1
2(0.5)=1
1
2
= 0
2(0.5)=1
1110100100
calculate
end
- 26 -
BYTE
WORD
MSB
LSB
MSB
01101011
LSB
0110101101000010
Most
Significant
Byte
Least
Significant
Byte
0(21)= 0
1(20)= 1
1(2-3)= 1/8
Name
Example
Result
AND
0010*1010
0010
OR
0010+1010
1010
NOT
0010
1101
EOR
0010EOR1010
1000
NAND
0010*1010
1101
Shift Left
111000
110001
Shift Right
111000
011100
Boolean Operations on Binary Numbers
B. Calculation of binary number.
The calculation for the negative binary number needs for special calculation method,
the numeric system for negative binary number used generally is shown as next 3 type
method. One of them, Unsigned binary number can be used, represents only positive
number. When signed and 2's complement method is used, the maximum number can
be represented is reduced to half size. 2's complement method is generally used for the
calculation of addition and subtraction is simple and fast on the hardware and
software. In the PLC system, all of methods of calculation are used.
Signed binary numeric systems are shown as next. the MSD is used to sign Bit when
display negative binary number.
Decimal
2
1
0
-0
-1
-2
Binary Byte
00000010
00000001
00000000
10000000
10000001
10000010
- 27 -
2's complement method to represent negative binary number are shown as next.
Basically if binary number to represent is positive number, binary number is
represented to normal binary number. But if binary number to represent is negative
number, after performing the complement calculation(inverting of all bits) for binary
number to represent and add 1 to it. Otherwise to get normal binary number from
negative binary number represented by 2's complement method, subtract 1 and
perform the complement calculation(inverting of all bits).
Decimal
2
1
0
-1
-2
2s Compliment
Binary Byte
00000010
00000001
00000000
11111111
11111110
Numbers
10000001=-127
+11111111=-1
10000001=-127
+11111110=-2
10000000=-1
C=1
O=0(No Error)
01111111=127
C=1
O=1(Error)
- 28 -
16 =4096
16 =256
16 =16
16 =1
F 8 A 3
15(163)= 61440
2
2048
160
8(16 )=
10(16 )=
3(16 )=
63651
16(0.75)=12(C)
357
=22.3125
16
16(0.3125)=5
22
=1.375
16
16(0.375)=6
1
=0.0625
16
16(0.0625)=1
1 6 5 C
- 29 -
1 2 6 3 Decimal
BCD
- 30 -
4. Data Characterization.
A.
To handle character, not number, identification number are given to each character and
string. And we can store to memory and interpret again.
ASCII (American Standard
Code for Information Interchange) is most generally used to character coding system
and represented as next table. This table represents not only character but also special
symbol and control code. At each codes, identification number are given, for example,
65 are given to character A.
ASCII Character Table
Char
Ctrl-@
NUL
Ctrl-A SOH
Ctrl-B STX
Ctrl-C ETX
Ctrl-D EOT
Ctrl-E ENQ
Ctrl-F ACK
Ctrl-G BEL
Ctrl-H BS
Ctrl-I HT
Ctrl-J LF
Ctrl-K VT
Ctrl-L FF
Ctrl-M CR
Ctrl-N SO
Ctrl-O SI
Ctrl-P DLE
Ctrl-Q DCI
Ctrl-R DC2
Ctrl-S DC3
Ctrl-T DC4
Ctrl-U NAK
Ctrl-V SYN
Ctrl-W ETB
Ctrl-X CAN
Ctrl-Y EM
Ctrl-Z SUB
Ctrl-[ ESC
Ctrl- FS
Ctrl-] GS
Ctrl-^ RS
Ctrl_ US
000
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
040
32
40 100 64
041
042
043
044
045
046
047
050
051
052
053
054
055
056
057
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
]
^
_
- 31 -
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
60 140 96
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
In this ASCII Character Table, code number is used from 0 to 127, but more
complicated special figure symbol or international character are generally used and
handled. The character is combined to string and LF or CR code is located at the end
of line.
B. Parity
When data is transmitted or stored the error often happen. In the harsh environment, especially
in the factory or plants, there exists some mis-occurrence in the data transmission line and
telephone due to noise. To prevent to occur errors, parity bit can be added to end of data
frame to detect data transmission error. If error is detect after parity checking, the data will be
transmitted again or ignored.
Parity Bit is located at the additional 9th bit to data byte 8 Bit. When the data is encoded,
communication device counts active data bits number. And parity bit is calculated whether
total active data bits has odd or even number. Transmitted data byte is confirmed with parity
bit, whether total active data bits has odd or even number. If error is detect after parity
checking, the data will be ignored and re-transmission is required. There are two types of
parity check methods, odd parity check and even parity check.
Odd
Parity
Even
Parity
Data Bit
10101110
10111000
00101010
10111101
Parity Bit
1
0
0
1
C. Check-sums
Parity Bit is favorable to combination of a few datum, otherwise Checksum is advantageous
for more complicate and large data transmission check. Checksum is simple algebraical sum of
total datum. Before perform a transmission, total bytes of datum is added. and this checksum is
sent with datum together. The checksum of received datum is calculated by addition and
checksum compared with checksum sent. If result of checksum comparing is concurrent, the
datum is accepted. The example of checksum calculation is shown as belows:
DATA
124
43
255
9
27
47
CHECKSUM
505
- 32 -
D. Gray Code
Parity Bit and Checksum is possible to check for every data values. Gray Code is used
to check data that should be accordance with binary order. Gray code is generally
used to measure angular value for encoders. The basic is that 1 bit changes once
when the binary number increase or decrease by 1. By this way, it's easier to check
the error of data bit. The example of Gray code is represented as belows:
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Gray Code
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
- 33 -
Karnaugh Map
1. Introduction of Karnaugh Map.
Karnaugh map makes possible to convert directly from complicated boolean algebra to
simplified boolean algebra without simplifying calculation using a truth table.
Before converting from truth table to boolean algebra, truth table can be shown as next.
Row and column can be determined form input variable. we may select arbitrarily which
variable will be used to row or column, we can find the same solution even Karnaugh
map are shown differently. The variables is assigned to both of row and column to
represent bit value considering also NOT. The assignment order of bits is the same as
00, 01, 11, 10. Describe bit status of true value for output variable A from truth table
to the Karnaugh map.
Step1 : Making of truth
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
table for
M W
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
S,M,W,Q,A.
Q A
0 0
1 0
0 0
1 0
0 0
1 0
0 0
1 0
0 0
1 1
0 0
1 0
0 0
1 1
0 0
1 1
MW(=00)
SQ(=00)
SQ(=01)
SQ(=11)
SQ(=10)
MW(=01)
MW(=11)
MW(=10)
M is common.
All is in SQ row.
W is common.
- 34 -
After written truth status to Karnaugh map, we can find typical identity of pattern for
1's(True state). When two or more bits exists on the in the same column or row, make
a circling these identity. Also after putting left side to right side or upper side to lower
side like a belt, two or more bits exists on the in the same column or row will appear.
this identity has to make circling.
These patterns is to be expressed to boolean algebra, the fact that all truth bits is
located at 3th line is meaning that SQ will be expressed to AND relation. Also in the
3th line, two pattern with common M and W exists. These pattern will be appeared to
relationship of boolean result and it can be converted to ladder logic.
Step4: Observe Map Pattern.
M is common.
All is in SQ row.
W is common.
Karnaugh map is alternative method that simplify the boolean algebra, is the way to
verify the calculation result of boolean algebra. In this example, there are four input
variables, two variables exists in row, also two variables exists in column. It is also
possible for more input variables, if 5 input variable exists, 3 input variables patterns
for row or column can be made like 000, 001, 011, 010, 110, 111, 101, 100. If
output variable exists two or more, Several karnaugh maps can be exist as well as
number of output variables.
- 35 -
2. Practical Example.
A. Express the following truth table to Karnaugh map.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Result
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
Result:
AB
1
1
0
0
CD
CD
CD
CD
AB
1
1
0
0
AB
1
0
0
0
AB
1
1
1
1
B. Express to ladder logic after simplifying truth table using Karnaugh map.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
- 36 -
CD
AB
00
01
11
10
00
0
0
0
0
01
0
0
0
0
11
0
1
1
0
10
0
1
1
0
X = BC
AB
AB
AB
AB
CD
1
0
0
0
CD
0
0
0
1
CD
0
0
0
1
CD
1
0
0
0
D. Express to ladder logic after simplifying truth table using Karnaugh map.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
- 37 -
Y
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
For X
AB
CD
01
0
0
1
1
00
0
0
1
1
00
01
11
10
11
0
0
0
0
10
0
0
0
0
For Y
E. Express to ladder logic after simplifying truth table using Karnaugh map.
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
E
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
F
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
G
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
- 38 -
00
0
0
0
0
00
01
11
10
DE
FG
01
0
1
1
1
11
0
1
1
1
10
0
0
0
0
Y = G(E+D)
G. Express to ladder logic using Karnaugh map without finding relation of Boolean
Algebra.
DE
DE
DE
DE
ABC
1
1
1
1
AB
ABC
1
1
1
1
ABC
0
0
0
0
ABC
1
0
0
1
ABCE
ABC
0
0
0
0
ABC
0
0
0
0
ABC
0
0
0
0
ABC
0
0
0
0
Output=AB+ABCE
- 39 -
- 40 -
X0 is Input Switch A and X1 Input Switch B. This Logic is equivalent to the next electrical
circuit.
Input Switch A
Input Switch B
Pilot Lamp
In this circuit, Pilot Lamp Y10 is ON When Input Switch A and Input Switch B is closed state.
We call this circuit AND, the output state according to each input switch is represented as next
Truth Table and Boolean Equation.
A * B = C or A x B = C
Input Switch A X0
0(OFF)
0(OFF)
1(ON)
1(ON)
Input Switch B X1
0(OFF)
1(ON)
0(OFF)
1(ON)
- 41 -
X0 is Input Switch A and X1 Input Switch B. This Logic is equivalent to the next electrical
circuit.
Input Switch A
Pilot Lamp
Input Switch B
In this circuit, Pilot Lamp Y10 is ON When Input Switch A or Input Switch B is closed state.
We call this circuit OR, the output state according to each input switch is represented as next
Truth Table and Boolean Equation.
A+B=C
Input Switch A X0
0(OFF)
0(OFF)
1(ON)
1(ON)
Input Switch B X1
0(OFF)
1(ON)
0(OFF)
1(ON)
- 42 -
X0 is Input Switch A and X1 Input Switch B. This Logic is equivalent to the next electrical
circuit.
Input Switch A
Pilot Lamp
Input Switch B
In this circuit, Pilot Lamp Y10 is OFF When Input Switch A and Input Switch B is opened state.
But Pilot Lamp Y10 will be not OFF When only one of Input Switch A and Input Switch B is
opened state. We call this circuit NAND, the output state according to each input switch is
represented as next Truth Table and Boolean Equation.
A+B=C
Input Switch A X0
0(OFF)
0(OFF)
1(ON)
1(ON)
Input Switch B X1
0(OFF)
1(ON)
0(OFF)
1(ON)
- 43 -
+ B)= A * B = C or A x B = C
- 44 -
X0 is Input Switch A and X1 Input Switch B. This Logic is equivalent to the next electrical
circuit.
Input Switch A
Input Switch B
Pilot Lamp
In this circuit, Pilot Lamp Y10 is OFF When Input Switch A or Input Switch B is opened state.
But Pilot Lamp Y10 will be ON When both of Input Switch A and Input Switch B is closed
state. We call this circuit NOR, the output state according to each input switch is represented as
next Truth Table and Boolean Equation.
A * B = C or A x B = C
Input Switch A X0
0(OFF)
0(OFF)
1(ON)
1(ON)
Input Switch B X1
0(OFF)
1(ON)
0(OFF)
1(ON)
- 45 -
+ B)= A * B = C or A x B = C
- 46 -
X0 is Input Switch A and X1 Input Switch B. This Logic is equivalent to the next electrical
circuit.
Input Switch A
Input Switch B
Pilot Lamp
In this circuit, Pilot Lamp Y10 is ON When only one of Input Switch A or Input Switch B is
pressed. But Pilot Lamp Y10 will be OFF When both of Input Switch A and Input Switch B is
pressed or not pressed state. We call this circuit Exclusive OR, the output state according to each
input switch is represented as next Truth Table and Boolean Equation.
A+B=A*B+A*B=C
Input Switch A X0
0(OFF)
0(OFF)
1(ON)
1(ON)
Input Switch B X1
0(OFF)
1(ON)
0(OFF)
1(ON)
- 47 -
Output M100
The total scan time is 2 scan including on duty(1 scan)and off duty(1 scan).
2 Scan Oscillator
Output M100
The total scan time is 4 scan including on duty(2 scan) off duty(2 scan).
2. Explanation.
This 1 Scan Oscillator used special characteristic of PLC I/O batch processing that updates I/O
device and reference Image and solves logic. 2 scan oscillator also can be made using special
characteristic of PLC referring to I/O status table. The order of PLC logic solving proceed from
left to right and from top to bottom.
- 48 -
Scan-time
1st Scan 2nd Scan 3rd Scan 4th Scan 5th Scan 6th Scan 7th Scan
Contact M100
Pass Disconnect Pass Disconnect Pass Disconnect Pass
Solving
Off
Off
Off
On
Result of
On
On
On
Coil M100
In case of 2 Scan Oscillator, I/O status table are as following.
Scan-time 1st Scan 2nd Scan 3rd Scan 4th Scan 5th Scan 6th Scan 7th Scan 8th scan
M100
On
On
Off
Off
On
On
Off
Off
M101
Off
On
On
Off
Off
On
On
Off
M102
Off
On
On
Off
Off
On
On
Off
- 49 -
2. Explanation.
The self holding circuit is generally used and there are two type of self holding circuit, 0
Dominant Self Holding circuit and 1 Dominant Self Holding circuit. This circuit can be also
regarded as SR Flip-Flop and RS Flip-flop and has two inputs and one or two outputs. When
two input are 1(truth state), The next truth table are shown that output Y0 becomes 0 in case of 0
Dominant Self Holding and output Y0 becomes 1 in case of 1 Dominant Self Holding.
- 50 -
Time Chart
X0
X1
Y10
Y11
2. Explanation.
The scan time of output of PLS command is 1 scan time at the moment when input is ON(at the
rising edge). The scan time of output of PLF command is 1 scan time at the moment when input
is OFF(at the falling edge). These command is used to detect synchronized task for inputting
event.
The equivalent circuit can be used in PLC that PLS /PLF command is not supported, M100,
M101 is auxiliary contact.
- 51 -
2. Explanation.
In the above ladder logic, SET/RESET command has a function of Flip-Flop, adding it's inverted
output to the input of the SET/RESET, total circuit acts as Toggle Flip-Flop by excitation of PLS
M30. Whenever input X9 is excited(like pushbutton), Output M31 will repeat ON/OFF action.
Generally, Actuator has each ON switch and OFF switch, in this case, this switch can operate
ON/OFF action of output by 1 switch.
X9
M31
- 52 -
2. Explanation.
If Level low-low Trouble occurs, M100 is latched, pilot lamp Y20 blinks slowly. When
push-button switch X11 is pressed, M101 is latched, pilot lamp stop flickering action, keep on
being ON state. If trouble occurs again, acknowledge state is broken by PLS M102, annunciator
returns to initial state. If pushbutton X10 is pressed, trouble annunciating state is re-scanned.
- 53 -
- 54 -
X0
5 sec
Y10
- 55 -
X1
Y11
5 sec
2. Explanation.
Timer function of Mitsubishi Melsec PLC is basically On Delay Timer. After Input X0 is
activated, output Y10 of On delay timer T50 will be ON after 5 sec. If T51 Timer is activated by
inverted input X1 and output Y11 is activated by inverted timer contact T51, Off Delay Timer
T51 is represented. Even X1 is OFF, output Y11 of timer T51 hold ON state during 5 sec.
- 56 -
X0
Y10
5 sec
X1
Y11
2. Explanation.
One Shot Timer as described above consists of self holding logic and 1 timer. After Input X0 is
activated, output Y10 of timer T50 hold ON state during 5 sec. To perform Re-triggerable timer,
adding RST T50 Logic makes it possible.
- 57 -
2. Explanation.
By inverted feedback of activated T51 timer at the initial time, this circuit begins oscillation. T50
Timer determines on duty time, T51 Timer determines off duty time. Real output Y10 uses T51
Flicker Contact, total blinking will be 1 sec.
Y10
0.5S
0.5S
- 58 -
- 59 -
Proximity
Switch
MOTOR
2. Explanation.
Using a TOF(Off Delay Timer), we can monitor continuous revolution state of motor or rotator.
Whatever motor or rotator have any forms, by installation of proximity switch and actuator at
shaft of motor or rotator, continuous surveillance of speed or belt, bearing can be possible. We
can adjust the excitation period of proximity switch and actuator at the logic, this can be the
setting time of TOF(Off Delay Timer). To prevent happening of trouble, the excitation period
time of proximity switch and actuator is within a TOF Preset time so that power flow of trouble
logic isn't discontinuous.
- 60 -
Chattering
Input X0
Filtered
Input M100
Chattering
Input X0
Considering +Edge
Input M101
- 61 -
2. Explanation.
For contact of mechanical Switches, if it becomes obsoleted, this will cause electrical transition
noise. These chattering noise will cause mal-function of the machine. This can be prevented by
PLC logic. Using a TON logic, the noise can be suppressed at the transition of rising edge of
electrical signal. Also using a TOF logic, the noise can be suppressed at the transition of falling
edge of electrical signal. But programmer should accept the result asynchronous timing signal
by delaying of TON and TOF.
- 62 -
2 Explanation.
Sometimes Analog Input value is hunted by noise or process problem to be impossible to find
comparing point. In this case this logic make hunting analog input value stable. It is possible to
make rapidly changing input value so dull by constant time increasing and decreasing. Time
constant should adjust to fit to site situation.
D500 : Simulated Input for Hunting
D20 : Time Filtered Input
- 63 -
Example 2.
- 64 -
2. Explanation.
This program is for measuring of production time, total operation time is stored at D100-D103.
At below 60 sec, this will be cut down and not included to total operation time. To prevent this,
programmer should use time base of 1 second, not a 1 minute.
- 65 -
2. Explanation.
Drive system of AC General Motor has function of surveillance for operation state of magnet
switch and feedback signal of speed monitor of motion System. But for more delicate
surveillance of speed monitor, this example will be applicable.
M300 is Trouble Flag, this can be reset by Pushbutton Switch X0 at any time. T50 Timer is used
to maintain time until the motor has the normal speed and torque after overcome inertia.
At this time, T150 is OFF Delay timer by excitation of input X9 of proximity switch for
surveillance of speed monitoring .
- 66 -
At first, we make Dual Action Switch Logic to measure excitation period from the proximity
switch, let timers T151 AND T152 operate by it's A/B contact. T151 is regarded as odd
excitation period, T152 is regarded as even excitation period.
- 67 -
Using Falling Edge of M31, we store instant value of odd and even excitation period to D52
register. By using X3 pushbutton, when motor drive system is stable, this value can be reflected
to preset value of running surveillance timer.
- 68 -
2. Explanation.
This example is for surveillance and operation of general Motor Drive System. For Manual
mode or Auto Mode, the things to have to be monitored and checked is the ON state of magnet
switch supplying power to motor and motor system is operated with normal speed within a set
time after magnet switch is ON. By this means, normal condition should be also checked
whether mechanical power transferring device of motor drive system is in good condition.
Driving belt, looseness of chain belt and speed reducer will be included.
Seeing ladder logic, after PLC Output Y10 is On, two timer will be operated. Before first timer is
done, Return Signal(X30) of magnet switch should be returned and cut the operation of T30
- 69 -
timer. Before second timer is done, Return Signal(X31) of speed monitor should be returned and
cut the operation of T31 timer. If it's not, cutoff of trouble flag M300, M301 cause motor trip by
timer operation.
The trouble flag in trip can be reset by pressing the reset pushbutton Switch. The preset value of
surveillance timer should be optimized during test-run.
PLC Output
Module
RST
PLC Input
Module
Y10
Magnet
Return
Signal
X30
X31
Motor Fan
Speed
Monitor
Return
Signal
- 70 -
2. Explanation.
Seeing command Move D100 D101 after M9036, Analog value 01(D100) is transferred to D101
to compare at next scan. At next scan if new Analog value 01(D100)is different with Analog
value 01(D101) stored at the previous scan, One shot timer annunciate that the value is changed.
- 71 -
- 72 -
2. Explanation.
Sequence Control generally can be performed by consisting of NO/NC Contact Coil and
programming of AND/OR/NOT. At this time, the ladder logic example of batch manufacturing
process that has constant processing cycle is shown.
Bit Shift command is initiated by energizing of X0 Input. After this each process step of Event
- 73 -
are proceeded by sensor or switch from the bit M48 to M54, total process cycle completes by
bits Shifting. At the end of ladder logic, [MOV H0 K4M40] is for initial reset and program
restart after 1cycle completion.
This sub-routine will be initiated by bit start of M49 from main logic and completed from the bit
M80 to M83. After completion of Sub-routine processing, program flow return to main logic by
energizing of M84 and all bits related Sub-routine Bit will be initialized.
- 74 -
- 75 -
Material
Reached
Belt
Conveyor
Stop
Material
Reached
Belt
Conveyor
Start
Drill
Advance
Blower
Retract
Cleaning
Tool move
To 1st
Position
Drilling
Blower
Advance
Tool
Change
- 76 -
Drill
Retract
2. Explanation.
Sequence Control generally can be performed by consisting of NO/NC Contact Coil and
programming of AND/OR/NOT. At this time, the ladder logic example of batch manufacturing
process that has constant processing cycle is shown.
Bit Shift command is initiated by energizing of X0 Input. After this each process step of Event
are proceeded by sensor or switch from the bit M48 to M58, total process cycle completes by
bits Shifting. At the end of ladder logic, [MOV H0 K4M40] is for initial reset and program
restart after 1cycle completion.
- 77 -
- 78 -
Material
Reached
Belt
Conveyor
Stop
Material
Reached
Belt
Conveyor
Start
Drill
Advance
Blower
Retract
Cleaning
Tool move
To 1st
Position
Drilling
Blower
Advance
Tool
Change
- 79 -
Drill
Retract
2. Explanation.
This example is to process sub-routine using a CALL/RET command. Subroutine is generally
used to substitute repetition of the same, will prevent to re-edit ladder logic and make logic
simple, save the program memory by reduce program step number.
X2 and X3 is to SET/RESET Y30 at each Subroutine of P1 and P2. If these two switch are ON
and X0 is ON, Y30 will be SET by calling subroutine1. If X1 is On, Y30 will be RESET by
calling subroutine2.
- 80 -
- 81 -
- 82 -
2. Explanation.
Using a For/Next command, the ladder logic example that sort number in the data table by order
of maximum number. The outer loop of For/Next command is to store found maximum value to
new table D40-D49, The inner loop of For/Next command is to find maximum value. At this
time, Index Register z acts as Pointer of Sorted Table , Index Register v acts as pointer that take
out the data from table to sort. Also this Pointer substitute pointer value to D101 register for
storing zero value to register of maximum value already found.
The first part of his logic is to initialize all register value.
- 83 -
- 84 -
- 85 -
Jumper Item
Decimal/ Hexa-decimal Select
Latch Active High/Low Select
Dynamic(Serial)/ Parallel Select
Settings
Decimal
Active low
Parallel
8 8 8 8
4 Latch lines
Y25
Y26
Y27
Y28
- 86 -
Output from Y28 to Y2B is used to transfer data to 7 Segment Unit. If Data/ Strobe Train and
Move Logic is add, user can add any number of 7 Segment Unit as far as speed limit.
- 87 -
- 88 -
Y2C
Y2D
Y2E
Y2F
X00
X01
X01
X02
X02
X03
X03
X04
X04
::
:
::
::
:
:
:
:X16
X0F
16 core
- 89 -
example, At first scan of PLC RUN start, Strobe train(MOV H2 K4M0) and DATA Train(MOV
H7 K4M16) is synchronized. The meaning of hexa-decimal value H2 and H7 is as next figure;
M0
M16
- 90 -
- 91 -
- 92 -
210
212
215
0~1023
204~1023
-1023~+1023
0~4095
817~4095
-4095~+4095
0~16383
1638~16383
-16383~+16383
- 93 -
Signal
Transmitter
(-)
(+)
DC4-20mA
(+)
(+) Sink
(-) Source
(-)
Shield
Power
Supply
Chassis
Shield
- 94 -
Power
Supply
(-)
(-)
(+)
Signal
Transmitter
(+) Sink
(-) Source
(+)
DC4-20mA
Shield
Chassis
Shield
210
212
215
0~1023
204~1023
-1023~+1023
0~4095
817~4095
-4095~+4095
0~16383
1638~16383
-16383~+16383
- 95 -
DC4-20mA
(+) Sink
(+)
(-)
(-) Source
Shield
Chassis
Shield
- 96 -
Signal
Transmitter
- 97 -
- 98 -
2. Explanation.
Let Register D1 Raw Value 32767 ~ +32767 from Analog Input Module. When the electric
signal has a value between 10V ~ +10V, and Process Variable has a value between 1000rpm ~
+1000rpm, The "Scaling" is expressed as this value make value Register D1 return to process
variable. K constant of Long Decimal Format in the Double Precision Multiplication/Division is
defined as Scaling ratio. K1000 is defined value to scale raw value to Engineering Unit RPM,
dividing by input range after multiplying Engineering Unit is to prevent bad deformity of
resolution.
PLC Logic
+10 V
Analog Input
Module
+10V~-10V
+32767
* 1000
/ 32767
+1000 RPM
+1000 RPM
Tacho
Generator
-1000 RPM
-32767
-10 V
- 99 -
-1000 RPM
2. Explanation.
If analog value 01(D1) is value over than 800, the output Y10 is ON. If analog value 01(D1) is
value below than 600, the output Y10 is OFF. As this matter, transit ON-OFF control that
overlapped ON point and OFF point is called "Schmitt Circuit".
Y10
ON
OFF
600
800
- 100 -
D1
2. Explanation.
If new value Analog value 01(D100) is bigger than Analog value 01(D101) stored before, new
value Analog value 01(D100) is transferred to D101. Therefore, The highest value analog value
01 up to now is stored to D200.
Minimum peak Hold function is represented as next:
- 101 -
2. Explanation.
D100 is Scaled PV(Process variable), also temperature value in the tank. By means of comparing
command, if D100 is below than 70 , Heating Coil is On. If D100 is value over than 80,
heating Coil is Off. Therefore, this system will have dead band of 10.
- 102 -
2. Explanation.
If new value Analog value 01(D100) is bigger than Analog value 01(D101) stored before and
this value is bigger than 1000 and is smaller than 5000, new value Analog value 01(D100) is
transferred to D101. Therefore, The analog value 01 smaller than 1000 and bigger than 5000 is
clamped.
to clamp only lower limit, the logic is as follow:
- 103 -
2. Explanation.
Bit Shift can be performed by Bit Shift command, also by multiplying or dividing by binary
weight. In this example, dividing Hexadecimal value HFF00( Binary 1111 1111 0000 0000) by
32 results bit shifting to right side as 4 bits is shown. Also multiplying Hexadecimal value
H00FF(Binary (0000 0000 1111 1111) with 32 results bit shifting to left side as 4bits is shown.
- 104 -
2. Explanation.
When the slow acceleration and deceleration of motor speed drive is performed, The next logic
can be shown. Acceleration is preset at D30, T50 and deceleration is preset at D31, T51 by
thumb-wheel switches.
- 105 -
- 106 -
2. Explanation.
Sometimes Analog Input value is hunted by noise or process problem to be impossible to find
comparing point. In this case this logic make hunting analog input value stable. It is possible to
make rapidly changing input value so dull by sampling data at every constant period and storing
to Q buffer and calculating datum . And calculation can be perform by adding all sampled datum
and finding its average.
D500 : Simulated Input for Hunting
D200 D205 : Queue Buffer
D400 : Averaged Value for Simulated Input for Hunting
- 107 -
2. Explanation.
Suppose stacker crane run on the rail in the warehouse. The logic is for this stacker crane is
controlled by motor drive of multi-stage speed control with encoder feedback.
D1 is corresponding to input Feedback of encoder. D3 is target position that stacker crane is
stopped. At that time of start, the position information will be stored to D110-D111 (double
precision Format). PLC calculates elapsed value(D120-121) of encoder and remained value to
target position(D130-131). This is useful when PLC get flags for multi-stage speed control at the
next logic.
- 108 -
After Stacker-Crane start, if the elapsed value of encoder is over than 5000, motor drive is
entered to 1st speed stage, if the elapsed value of encoder is over than 10000, motor drive is
entered to 2nd speed stage, if the elapsed value of encoder is over than 15000, motor drive is
entered to 3rd speed stage. And if the elapsed value of encoder is remained below than 15000,
motor drive is entered to 3rd speed stage, if the elapsed value of encoder is remained below than
10000, motor drive is entered to 2nd speed stage, if the elapsed value of encoder is remained
below than 5000, motor drive is entered to 1st speed stage.
Speed
Start Point
Stop Point
- 109 -
- 110 -
B.
2. Explanation.
In case of that blending and mixing control of liquid or powder by ratio should be performed,
this logic can be applied. For example, color combination of dyeing line or painting line,
ingredients mixing of
FACTOR
FACTOR
FACTOR
FACTOR
FACTOR
- 111 -
- 112 -
2. Explanation.
For the Batch Control, loading of liquid or powder by measuring the volume or weight with
scale or encoder pulse signal is often performed. At this time, loading speed should be
maximized for job efficiency, but if loading valve is simply opened and closed, when the loading
action is about to end, the excessive loading sometimes happens. To avoid this malfunction,
Before the loading end, left several percent loading job, by opening valve quite little bit, this can
be prevented . This action is called trickle or drizzle control.
Loading speed
or valve open
state
Trickle
Point
- 113 -
Loading
End
Weight
- 114 -
2 Explanation.
In case of that the rotator drives incremental encoder of simple counting (Uni-directional
Counting) for finding R.P.M.(Revolution Per Minute) of rotator, we can get simple count from
only 1 register, this value will be value from 32767 to 32767. To make calculation easier,
Adding +32767 to real count value for the minus value. By this way, we find the difference after
storing count variation during constant time, calculate sampled counting rate. In case of that,
sampling period should be shorter than 32767 counting time at the maximum speed of rotator.
- 115 -
- 116 -
2 Explanation.
When scaling for zero point shifted analog signal to X axis as figure shown is performed, the
formula as next can be applied.
(X-A) * C
Y= -------------------(B-A)
- 117 -
At this time each section and register allocation of X and Y can be shown as next:
X: D500
Y: D510
A: D2000 C: D4000
B: D2010
- 118 -
2. Explanation.
When scaling for zero point shifted analog signal to Y axis as figure shown is performed, the
formula as next can be applied.
(C-B) * X
Y= -------------------- + B
A
- 119 -
At this time each section and register allocation of X and Y can be shown as next:
X: D500
Y: D510
B: D2000 A: D4000
C: D2010
- 120 -
2. Explanation.
The simplifying method of non-linear characteristic curve is the way that sectional dividing of
non-linear characteristic curve to be indicated piecewise. At any formula curve of non-linear
characteristic, if we accept its deviation, we can represent non-linear characteristic curve to
sectional linear curve.
At this ladder logic example, dividing non-linear characteristic curve into 2 section linear curve
and representing to math logic is shown.
When a proportional line is shown to mathematic formula, the expression is as next;
(E-D) * (x-A)
Y= -------------------- + E
(B-A)
- 121 -
At this time each section and register allocation of X and Y can be shown as next:
X: D500
Y: D510
A: D4000 F: D2000
B: D4010 E: D2010
C: D4020 D: D2020
- 122 -
2. Explanation.
The simplifying method of non-linear characteristic curve is the way that sectional dividing of
non-linear characteristic curve to be indicated piecewise. At any formula curve of non-linear
characteristic, if we accept its deviation, we can represent non-linear characteristic curve to
sectional linear curve.
At this ladder logic example, dividing inverse non-linear characteristic curve into 2 section linear
curve and representing to math logic is shown.
When a inverse proportional line is shown to mathematic formula, the expression is as next;
- 123 -
(F-E) * (x-A)
Y=[ (F-E) - -------------------- ] + E
(B-A)
At this time each section and register allocation of X and Y can be shown as next:
X: D500
Y: D510
A: D4000 F: D2000
B: D4010 E: D2010
C: D4020 D: D2020
- 124 -
- 125 -
2. Explanation.
This example shows linear profiler that Y Analog Output(D3000) varies to X time axis (D1000).
There are total 6 section that perform acceleration, constant speed, deceleration.
- 126 -
- 127 -
Logic Diagram 2
Logic Diagram 3
2. Explanation.
If the exclusive OR is performed for source register with destination register having the same
address to source register's, the result cause that all bits in the register makes to 0. Logic diagram
1 is shown before performing Exclusive OR, Logic diagram 2 is shown after performing
Exclusive OR, Logic diagram 3 is shown after performing Exclusive NOR, the result cause that
all bits in the register makes to 1.
- 128 -
2. Explanation.
Generally 2's complement is performed for all the register, this results that makes opposite side
of the register, using this, we can makes all bit of the register to set to 1 as the ladder logic
example above.
There is data of Hex value HFF0000FF in the D100 and D101, by performing 2's complement,
inverted data H00FFFF00 is generated to D102, D103 registers. Also by performing AND
operation, this result that makes all bit of the register to reset to 0.
- 129 -
2. Explanation.
Once X0 is excited, D100 is increased by 1.
Output(K4Y10). This can be regards as binary counter that the output has each binary weight
12
value. If D100 is increase to 2 , by [= HFFF D100] command, D100 is to reset. Therefore, this
can be regards as 212binary counter.
- 130 -
- 131 -
Bits Disassembling
2. Explanation.
Assembly and disassembly of bits is represented as the example using FMOV and BMOV
command, there exists numbers from 1 to 4 in D100-D103. When we want these number to
output to 7 segment display device, we make these numbers Assemble and disassemble using
BMOV command.
If we want the number 1234 stored in D130 disassemble and move to each registers, FMOVE
command can be used.
- 132 -
Bits Assemble
1
D100
D101
D102
D103
2
3
4
Bits Disassemble
K4Y20 / D120
4
3
2
1
- 133 -
D130
D131
D132
D133
2. Explanation.
When we give Analog Set-point to control program and set-point is rapidly changed, the control
system can be unstable or damaged. To prevent this, using a ramp function, set-point can be
made to linear signal, we can get stable control characteristic
D100 is raw analog set-point. is compared to filtered set-point D0. By bigger or smaller, filtered
set-point D0 can be increased or decreased by INCP or DECP command. Acceleration Rate and
Deceleration Rate can be determined by each timer.
- 134 -
:
:
- 135 -
:
:
2. Explanation.
For proper operation, BCD Data of 2digit Thumb wheel Switch from X0 to X8 can be converted
to binary data. using DECO command, we can control from M100 to M124.
If Thumb wheel switch is set to 12,
SET(Valve13 Cylinder).
Available M Bit Flag number will be 100sets(Cylinders of 100sets ).
- 136 -
Thumbwheel Switch
D100
1 2
M115
0
M100
M112
0
M124
M116
Using this M Bit Flags, several actuator can be control to on and off in manual mode. The logic
from Step23 to Step58 are dual action pushbutton logic, once X10 pushbutton switch is
activated, corresponding cylinder will be repeat on/off operation.
- 137 -
2. Explanation.
At initial scan of M9038, M0, first positioned coil of Ring Counter, will be set. By timer T50
having K10 period, Coil from M0 to M33 will be operated as Ring Counter. M9012 as Carry
Flag, this Escape Bit will be returned to set M0 coil.
T50
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
1sec
:
:
:
:
:
- 138 -
2. Explanation.
Trouble Flag of total 64 from M800 to M863 are registered to this logic. Trouble Number from
trouble flag will be displayed to 7 Segment Display Unit. Seeing logic at 33Step, this logic has
like the function. If M800 Trouble is occurred, The trouble number displayed at 7 Segment
Display Unit is 1. Also M804 Trouble is occurred, The trouble number displayed at 7 Segment
Display Unit is 5, M860 Trouble is occurred, The trouble number displayed at 7 Segment
Display Unit is 61.
- 139 -
Input X10~X13 is for simulation for trouble occurrence. In practical use, this should be replaced
to timer contact monitoring trouble, contact element determining defectives. Input X3 is acted as
trouble reset switch, set trouble flag.
- 140 -
Logic Diagram 2
This logic is for drawing out the last saved quality information from Queue Buffer Memory
- 141 -
using a Index Pointer Z. At this time, Physical Buffer Area is located from M1 Roller Conveyor
to M2 Roller Conveyor.
Logic Diagram 3
This logic is to determining product quality and storing to Starting Memory to Queue Memory.
- 142 -
- 143 -
- 144 -
2. Explanation.
This PLC ladder logic represents LIFO (Last In First Out) operation of stack memory. By
energizing Input X0, the data of D500 Register is pushed to Stack Memory register having
starting address D200. By energizing Input X7, The datum 100, 200, 300, 400, 500 pushed
continuous are moved to D510 Register with POP operation. This ladder logic can be performed
simply by Index Register V, Z.
D500 : Source Data Register
D200 D205 : Stack Memory
D510 : Destination Data Register
XO : PUSH Operation
X7 : POP Operation
- 145 -
- 146 -
- 147 -
- 148 -
2. Explanation.
When process Data needs to be managed by cell unit, The memory space that data is saved and
loaded to or from 2-dimensional or 3-dimensional database is required. When various tags or
labels of Data are loaded or saved, this is to say, when the management or distribution of good
stock is performed in the PLC logic, we can refer to this logic.
If Input X0 is pressed, data is stored to database by final cell index pointer V that calculates
PAGE, column, row. In this example, data is stored to cell of database corresponding to page 2,
row number 4, column number 11.
If Input X1 is pressed, data is loaded from database by final cell index pointer V that calculates
PAGE, column, row.
- 149 -
This ladder logic example is to entry/save/sort/ load data to the data base memory to search
optimized data. Data register of PLC state RAM is used as Data memory space for database that
have 2 dimensional assignment.
The logic above is that Factor datum from D90 to D99 is entered from MMI is to be saved to
PLC memory having starting address D100. At this time, index pointer V is varied by INC
command.
- 150 -
Index Register V is the Pointer of 1st assignment element. D30 Register is the Pointer of 2nd
assignment element.
M80 will be the Save Button after MMI Value Entry.
- 151 -
The Logic above is for discrete control with MMI to sort the saved datum. M81 will be Search
Command Button from MMI, initialize for sorting by triggering of this button coil. D51 is
interlocking pointer to stop the sorting after counting sorted record up to 20 record from
data-base. D55 is interlocking pointer to stop the sorting after counting sorted record up to last
record from data-base.
- 152 -
This logic is that move datum to register from D80 to D89 by 1 record( 10 cell register ) with
starting address D100 from data-base for sorting.
- 153 -
This logic is that move datum to register from D80 to D89 by 1 record( 10 cell register ) with
starting address D100 from data-base for sorting.
- 154 -
At this time, we need to check whether record is within positive and negative tolerance getting
from D70 to D79 from the MMI. For this operation, we make threshold value form this by math
logic.
- 155 -
The positive threshold is made to register D60-D69, The negative threshold is made to register
D40-D49 for comparing with tolerance.
- 156 -
We determine by comparison flag if record placed to buffer from database is within tolerance.
The flags from M90 to M99 are by-pass flag to be selected from MMI for sorting.
- 157 -
When the determined Flag(from M200 to M206) are satisfied, this record is moved to sorted data
area(with starting address D8000).
- 158 -
This logic is for displaying sorted data table to MMI displaying table has 7 row's cells and 8
column cell. For the reason of space limitation of MMI table, we can't display all sorted datum to
MMI table and we should make a Scroll-up(M55), Scroll-down(M59) Key. In this logic, for the
saving area of Record is located from D200 to D299(total 20 records), the interlock is needed
after grasping the point number by comparison command before these flags. As the same way,
the interlock M40 is needed to limit moving operation when the last record saved is moved to
MMI buffer table after sorting operation is ended.
- 159 -
8 records, 800 cells will be moved from the data table with D8000 starting address after sorting
ended to the table with D300 starting address and end address D379.
- 160 -
- 161 -
- 162 -
- 163 -
3. Cable interconnection
4. Used message
Test Protocol: ?99TST0123456789@@(CR)(LF)
5. ETC.
(1) Transmission method: Half Duplex type (DTR/DSR Control: Don't use CD Signal)
Cf: DTR/DSR Control or X on/off Control
(2) Need to set at the buffer memory address 10BH
- 164 -
- 165 -
- 166 -
3. Cable interconnection
4. ETC.
Transmission Method: Full Duplex (X on/off Control)
5. Used Ladder logics
-
- 167 -
- 168 -
GPPWin
U
P
C
3. Cable interconnection
- 169 -
6. GPPWin Setting
(1) PC Side; COM1, 9600 bps
(2) PLC Side; 9600 bps, 1 Stop bit, Odd parity, Using Sum-check, 10 sec Time-out delay.
Via UC24, Host Target, Module Unit no. 1.
7. ETC.
-
8. Schematic Diagram
Melsec A2SH PLC
4
2
C
U
GPPWin
4 WIRES
MODEM
MODEM
COM1
- 170 -
U
P
C
3. Cable interconnection
- 171 -
7. GPPWin Setting
(1) PC Side; COM1, 9600 bps
(2) PLC Side; 9600 bps, 1 Stop bit, None parity, Using Sum-check, 15 sec Time-out delay.
Via UC24, Host Target, Module Unit no. 0.
8. ETC.
- Inserted slot of UC24-R2 : Don't care.
- There was no ladder logic to be needed for setting up the communication.
- Located station no. : Station 0
9. Schematic Diagram
Melsec A2SH PLC
4
2
C
U
GPPWin
Phone Lines
MODEM
MODEM
COM1
- 172 -
U
P
C
P
S
R
W
P
3. Cable interconnection
4. ETC.
Transmission method: Full Duplex (DTR/ER)
5. Used Ladder logics
-
- 173 -
GP577R
- 174 -
U
P
C
3. Cable interconnection
4. ETC.
Transmission method: None
5. Used Ladder logics
- Inserted slot of UC24-R2 : Don't care.
- There was no ladder logic to be needed for setting up the communication.
- Located station no. : Station 0
- 175 -
Fix 32
U
P
C
- 176 -
(3) Invoke the MIT Driver and Set-up as I/O Server as follows;
- 177 -
- 178 -
(5) Design and draw as what you want and define MACRO and tag names.
- 179 -
- 180 -
3. Cable interconnection
4. ETC.
Transmission method: None
5. Used Ladder logics
- Inserted slot of UC24-R2 : Don't care.
- There was no ladder logic to be needed for setting up the communication.
- Located station no. : Station 0
- 181 -
Intouch
U
P
C
(3) Enter again Configure> Topic definition>. And set up I/O Server as follows;
- 182 -
(4) Invoke Window maker. Enter Menu Specials> DDE Access Name>. And setup
parameter as follows;
- 183 -
Appendix
MODICON Concept Version 2.1 PID Simulation Function Block Diagram
Bit Division for MMI Analog tag
SIMATIC TI545 PLC PID Simulation
SIMATIC TI545 PLC vs Intouch 8.0
Modicon E785 PLC vs Intouch 7.1 PID Simulation
- 184 -
2. Description.
The PID function is actually controlling the process simulated by this logic. The process
simulator is comprised of two Lead/Lag function that act as a filter and input to a delay queue
that is also a Concept CLC_PRO function block. This arrangement is the equivalent of a
second-order process with dead time. The solution interval for the DELAY queue is set at
1000ms with a delay of 5 interval-i.e. 5s.
The LLAG Filters each have lead term of 4s and lag terms of 10s. The gain for each is 1.0.
In process control terms the transfer function can be expressed as;
(4s+1)(4s+1) e^-5s
Gp(s)= -------------------(10s+1)(10s+1)
3. PID parameters.
The PID controller is tuned to control this process at 20.0 using the Ziegler-Nichols tuning
method. The resulting controller gain is 2.16 equivalent to a proportional band of 46.3 percents
The integral time is set at 12.5 s/repeats/min). The derivative time is initially 3s, then reduced to
0.3s to de-emphasize the derivative effect.
- 185 -
Sub Script1()
While 1
Val1 = GetTagVal("WORD1")
if ( Val1 >= 32768 ) then
SetTagVal "PL15", 1
Val1=Val1 - 32768
else
SetTagVal "PL15", 0
End if
if ( Val1 >= 16384 ) then
SetTagVal "PL14", 1
Val1=Val1 - 16384
else
SetTagVal "PL14", 0
End if
if ( Val1 >= 8192 ) then
SetTagVal "PL13", 1
Val1=Val1 - 8192
else
SetTagVal "PL13", 0
End if
if ( Val1 >= 4096 ) then
SetTagVal "PL12", 1
Val1=Val1 - 4096
else
SetTagVal "PL12", 0
End if
if ( Val1 >= 2048 ) then
SetTagVal "PL11", 1
Val1=Val1 - 2048
else
SetTagVal "PL11", 0
End if
if ( Val1 >= 1024 ) then
SetTagVal "PL10", 1
Val1=Val1 -1024
else
SetTagVal "PL10", 0
End if
if ( Val1 >= 512 ) then
SetTagVal "PL9", 1
Val1=Val1 - 512
else
SetTagVal "PL9", 0
End if
if ( Val1 >= 256 ) then
SetTagVal "PL8", 1
Val1=Val1 - 256
else
- 186 -
SetTagVal "PL8", 0
End if
if ( Val1 >= 128 ) then
SetTagVal "PL7", 1
Val1=Val1 - 128
else
SetTagVal "PL7", 0
End if
if ( Val1 >= 64 ) then
SetTagVal "PL6", 1
Val1=Val1 - 64
else
SetTagVal "PL6", 0
End if
if ( Val1 >= 32 ) then
SetTagVal "PL5", 1
Val1=Val1 - 32
else
SetTagVal "PL5", 0
End if
if ( Val1 >= 16 ) then
SetTagVal "PL4", 1
Val1=Val1 - 16
else
SetTagVal "PL4", 0
End if
if ( Val1 >= 8 ) then
SetTagVal "PL3", 1
Val1=Val1 - 8
else
SetTagVal "PL3", 0
End if
if ( Val1 >= 4 ) then
SetTagVal "PL2", 1
Val1=Val1 - 4
else
SetTagVal "PL2", 0
End if
if ( Val1 >= 2 ) then
SetTagVal "PL1", 1
Val1=Val1 - 2
else
SetTagVal "PL1", 0
End if
if ( Val1 = 1 ) then
SetTagVal "PL0", 1
else
SetTagVal "PL0", 0
End if
Wend
End Sub
- 187 -
PID Simulation
1. Used Software
- 188 -
2. PLC Configuration
- 189 -
- 190 -
- 191 -
- 192 -
- 193 -
- 194 -
Communication setup
1. Testing Software :Intouch 8.0 MMI Software
2. Module Dip switch setting:
3. Cable interconnection
4. ETC.
Transmission method: None
Used Ladder logics
- TI545 CPU should be in RUN state.
- There was no ladder logic to be needed for setting up the communication.
TI545 CPU
5
4
5
I
T
Intouch
- 195 -
O
/
I
5. Settings up of Intouch
A. Executes TIDIR .EXE and Invoke Settings>Communication Port Settings.
- 196 -
E. Invoke InTouch Windows maker and enter Main Menu>Specieals. Define "Access
Names".
- 197 -
- 198 -
In case of defining Real Tag, you will add period after following Item number last.
Result is as below.
H. Result of communication between TI545 CPU and Intouch 8.0 through serial cable.
- 199 -
- 200 -
4. ETC.
Transmission method: None
5. Used Ladder logics
- E785 CPU should be in RUN state.
- There was used PCFL ladder logic to be needed for PID simulation.
Modicon E785 CPU
O
/
I
Intouch
- 201 -
5
8
7
E
4
8
9
6. Settings up of Intouch
A. Executes MODBUS .EXE and Invoke Settings>Communication Port Settings.
- 202 -
D. Invoke InTouch Windows maker and enter Main Menu>Specials. Define "Access
Names". Leave Node Name to blank if system is stand-alone.
- 203 -
- 204 -
F. Result of communication between E785 CPU and Intouch 7.1 through serial cable.
- 205 -
7.
- 206 -
- 207 -
- 208 -
- 209 -
- 210 -
- 211 -
- 212 -
- 213 -
REMARK:
- 214 -
REMARK:
- END -
- 215 -