EE 577A Laboratory #2

Part I
Fully Custom 512-bit SRAM Design

Report
Name: Chaitanya Amin
Email: chaitana@usc.edu
Date: 03/06/15

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Sr.
No.

Topic
Topic

Page No.
Page No.

Schematic, Symbol
Schematics,
Brief Explanation
& Layout ofof1-Bit
Design
Full Adder

Single Cell Operation - Waveforms

12

Functional Test of SRAM

13

Layouts, Successful LVS Report

18

Functional Test on Extracted View

32

Summary

36

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1.

Schematics:

Brief Description:
The given schematic of SRAM was first analyzed and sizing was done.
The sizes had to be carefully decided as per the discussions in the lecture.
The decoder had to be carefully designed so as to reduce the delay. I have
used NOR based array for the decoder logic.
The Schematic was then simulated using cadence SPECTRE simulator to test
the functionality.
After verifying the functionality, I proceeded to create the layout, which
required effective routing so as to ensure that the instance of SRAM cells can
be placed adjacent cells without any DRC violations.

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1.

Circuit Schematics:

Figure 1: SRAM Cell

This is the basic SRAM cell. Sizes of the basic cell are kept as per the one
given in the assignment question.

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Figure 2: SRAM Pre-charge Circuit

Sizing has been done after careful analysis of the circuit and
functionality test of SRAM cell.

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Figure 3: SRAM Sense Amplifier

Sizing has been done after careful analysis of the circuit and
functionality test of SRAM cell.

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Figure 4: SRAM Write Circuit

Sizing has been done after careful analysis of the circuit and
functionality test of SRAM cell.

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Figure 5: SRAM Multiplexer with Flip Flop

Here, to simplify the layout, the both the adjacent columns of a single bank
have been connected so as to make them columns of different banks.
That helped in area reduction and also in less routing complexity.
So, every mux is directly connected to each flip flop.
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Figure 6: SRAM 256

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Figure 7: SRAM Decoder

Sizing has been done after careful analysis of the circuit and
functionality test of SRAM cell.
Inverters are added at the output to improve the drive strength.

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Figure 8: Complete 512 Bit SRAM Schematic

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2.

Single Cell Operation - WAveforms:

Figure A: Write1->Read1->Write0->Read0->Write1

This is the waveform for simulation of a single SRAM cell for Writing
a 1, Reading it, then writing a 0, Reading it and finally Writing a 1.
First, before every Read and Write operation, we need to pre-charge
the SRAM cell, so an active low signal of Pre-Charge enable is given
as shown in the waveform.
Then we enable the word-line, give the data to be written and give
the Write_Enable Signal.
We see the variation in the Bit and Bit_B lines at this point and
finally the cells flip and the corresponding output can be verified by
a read operation at the same location.
For read, we have to first pre-charge, then enable word-line, give
read enable signal and wait for the sense amplifier to produce the
results.
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3.

Functional Test of SRAM Schematic:

My USC ID: 9384-0644-56
Sequence

A[4]-A[0]

data[15]-data[0]

01010

9F44

00111

FF83

01000

18D7

11011

1A2B

10111

80FE

10101

9BD5

10110

7713

10101

4C56

10011

E15C

11111

BA6C

Now, as per my USC ID, I have given the sequence of Write and Read
of the above mentioned data in the corresponding address.
This vector file was used to simulate the design and verify the
functionality.
My USC ID: 9384-0644-56
Sequence
9
3
8
4
0
6
4
4
5
6

A[4]A[0]
11011
10101
01000
10011
10111
01010
10011
10011
11111
01010

data[15]-data[0]
1A2B
4C56
18D7
E15C
80FE
9F44
E15C
E15C
BA6C
9F44

Result
0001-1010-0010-1011
0100-1100-0101-0110
0001-1000-1101-0111
1110-0001-0101-1100
1000-0000-1111-1110
1001-1111-0100-0100
1110-0001-0101-1100
1110-0001-0101-1100
1011-1010-0110-1100
1001-1111-0100-0100

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Write Operation Waveforms:

Set A

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Set B

#Note: Set A and Set b are identical. It is just for more clarity, I have
attached both snapshots.

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Read Operation Waveforms:

Set A

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Set B

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4.

Layouts and Successful LVS Report:

a) Basic Cell of SRAM

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b) Write Circuitry

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c)Flip Flop

d) Multiplexer

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e) Pre-charge Circuit

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f) Row Decoder

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g) Sense Amplifier

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h) SRAM 256 bit Bank

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i) SRAM Complete Layout

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Successful LVS Report:

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@(#)$CDS: LVS version 6.1.5 10/16/2012 03:06 (sjfdl051) $

Command line: /usr/local/cadence/IC615/tools.lnx86/dfII/bin/32bit/LVS -dir /home/scf-25/chaitana/cds/LVS -l
-s -t /home/scf-25/chaitana/cds/LVS/layout /home/scf-25/chaitana/cds/LVS/schematic
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Compiling Diva LVS rules...

Net-list summary for /home/scf-25/chaitana/cds/LVS/layout/netlist

count
1576
66

nets
terminals

1606

pmos

2694

nmos

Net-list summary for /home/scf-25/chaitana/cds/LVS/schematic/netlist

count
1576
66

nets
terminals

1542

pmos

2630

nmos

Terminal correspondence points

N1540

N103

A<0>

N1531

N105

A<1>

N1523

N106

A<2>

N1517

N107

A<3>

N1575

N108

A<4>

N1571

N104

A_B<0>

N1564

N109

A_B<1>

N1558

N110

A_B<2>
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N1550

N111

A_B<3>

N1541

N112

A_B<4>

N1516

N48

Data<0>

N1536

N55

Data<10>

N1528

N16

Data<11>

N1522

N15

Data<12>

N1515

N71

Data<13>

N1573

N74

Data<14>

N1566

N14

Data<15>

N1574

N50

Data<1>

N1567

N49

Data<2>

N1560

N51

Data<3>

N1554

N67

Data<4>

N1544

N68

Data<5>

N1534

N72

Data<6>

N1526

N13

Data<7>

N1520

N54

Data<8>

N1513

N73

Data<9>

N1552

N95

Data_B<0>

N1511

N80

Data_B<10>

N1569

N79

Data_B<11>

N1562

N75

Data_B<12>

N1556

N81

Data_B<13>

N1547

N78

Data_B<14>

N1539

N77

Data_B<15>

N1542

N94

Data_B<1>

N1532

N93

Data_B<2>

N1524

N92

Data_B<3>

N1519

N91

Data_B<4>
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N1512

N90

Data_B<5>

N1570

N89

Data_B<6>

N1563

N88

Data_B<7>

N1557

N82

Data_B<8>

N1548

N76

Data_B<9>

N1510

N12

Decoder_en_active_low

N1535

N34

Out_Mux<0>

N1568

N24

Out_Mux<10>

N1561

N23

Out_Mux<11>

N1555

N22

Out_Mux<12>

N1546

N21

Out_Mux<13>

N1537

N20

Out_Mux<14>

N1530

N19

Out_Mux<15>

N1527

N33

Out_Mux<1>

N1521

N32

Out_Mux<2>

N1514

N31

Out_Mux<3>

N1572

N30

Out_Mux<4>

N1565

N29

Out_Mux<5>

N1559

N28

Out_Mux<6>

N1553

N27

Out_Mux<7>

N1543

N26

Out_Mux<8>

N1533

N25

Out_Mux<9>

N1549

N3

Precharge_en

N1529

N86

Read_en

N1545

N4

Write_en

N1551

N5

clk

N1518

N0

gnd!

N1525

N87

rst

N1538

N1

vdd!
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Devices in the netlist but not in the rules:

pcapacitor
Devices in the rules but not in the netlist:
cap nfet pfet nmos4 pmos4

The net-lists match.

layout schematic
instances
un-matched

rewired

size errors

pruned

active

4300 4172

total

4300 4172
nets

un-matched

merged

pruned

active

1576 1576

total

1576 1576
terminals

un-matched

matched but
different type
total

66

66

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Probe files from /home/scf-25/chaitana/cds/LVS/schematic

devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:

Probe files from /home/scf-25/chaitana/cds/LVS/layout

devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:

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5.

Functional Test of Extracted View:

Write Operation Waveforms:

Set C

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Set D

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Read Operation Waveforms:

Set C

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Set D
#Set C is identical to Set D. The two different background
images are given just for extra clarity.
#For comparing Schematic with Layout, We may compare
Set A and B (Schematic) with Set C and D (Extracted).
#The waveforms in the schematic match completely with
the waveforms in the extracted view.
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6. Summary:

The 512-bit SRAM was successfully designed and simulated.

Careful analysis of the critical path led to changes in the sizing of the circuitry.
The SRAM basic cell was kept with the same sizing as that given in the Lab.
Decoder was designed with NOR based array and 4x followed by 8x inverters were used
to buffer the output of the decoder.
Sense Amplifier M0-M6 was chosen as 1.2u.
Write Circuitry M7-M10 was chosen as 1u.
Pre-charge M10-M12 was chosen as 2u to speed up pre-charging.
Clock cycle of 50% duty cycle was given for simulations.
For stimuli, various combinations of timings were tried for the best possible case of
Read and Write.

Area of SRAM CellLength: 128.8

Height: 116.25
Area: 14,973

TimingRead Timing: 1.8ns

Write Timing: 1.6ns

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