Tr n

nh Nga

ngatrandinh@gmail.com

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ng 1. Cc thi t b logic l p trnh

1.1. ROM- Thi t k h t h p dng ROM

1.1.1. ROM

address data
inputs
m
ng

address data
outputs
n
ng

C u trc ROM 2nxm

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1.1.1.ROM

M t b ng

ghi ROM

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1.1.1.ROM

B ng chn tr c a ROM 8x4 (1)

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1.1.2. Thi t k h t h p dng ROM

Bi ton:
Thi t k m ch gi i m 2 sang 4 v i m c tch
c c ng ra
c l a ch n.
H ng gi i quy t:
S
kh i m ch gi i m
B ng tr ng thi
Rt g n hm
M ch th c hi n

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1.1.2. Thi t k h t h p dng ROM

M ch gi i m 2 -4

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1.1.2. Thi t k h t h p dng ROM

M ch gi i m 2 -4 dng b ng chn tr (1)

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1.2. PLD
Thi t b logic kh trnh (Programmable Logic
Device)

Phn lo i:
SPLD
PLA (Programmable Logic array)
PAL (Programmable Array Logic)
GAL (Generic Array Logic)

CPLD

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1.2.1. PAL

Programmable
Input

And
plane
Fixed
Or
plane

Output

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1.2.1. PAL

C u trc c a 1 PAL

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1.2.1. PAL
c i m c a PAL
Ch l p trnh

cm tl n

C u trc PAL cho php th c hi n t t c cc hm

t ng c a cc tch v i cc bi n
c xc nh
M t m ng l p trnh l 1 ma tr n cc dy d n g m
cc hng v cc c t v chng c th l p trnh
n i v i nhau t i i m giao nhau

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1.2.1. PAL
c i m c a PAL (tt)
M i

i m n i l p trnh c c u t o l c u ch v
c g i l m t cell

B ng cch l p trnh gi nguyn c u ch hay

ph h ng c u ch th c th t o ra b t k
hm t h p no

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1.2.1. PAL
V d : L p trnh cho PAL

t o ra m t hm:

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1.2.1. PAL

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1.2.2. PLA
Programmable
And
plane

Or
plane

Output

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1.2.2. PLA

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1.2.2. PLA

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1.2.3. CPLD

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1.2.3. CPLD
Cc cng ngh l p trnh
PROM: L p trnh 1 l n
EPROM, flash, EEPROM: l p trnh nhi u l n
Non-volatile

V cc

V cc

V cc

After manufacturing
Address

2 -t o-4 De c ode r

2
MSB

2
LSB

4 -1 Mux
Data

V cc

Fuse

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1.2.4. FPGA
V c b n FPGA (Field Programmable
Gate Array) c c u trc khc khng dng
m ng lo i PAL/PLA c m t
tch h p cao
h n nhi u so v i CPLD
Cc ph n t dng
t o ra cc hm logic
trong FPGA th ng th nh h n nhi u so v i
cc thnh ph n trong CPLD
Cc k t n i bn trong
c t ch c theo
hng v c t

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1.2.4. FPGA

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1.2.4. FPGA
Cc kh i IO n m xung quanh c a c u trc t o ra
s truy xu t ng vo, ng ra ho c c hai chi u c
th l a ch n m t cch c l p n th gi i bn
ngoi
Cc FPGA l n c th c 10000 CLB v c thm b
nh v cc ngu n ti nguyn khc
H u h t cc nh ch t o cc thi t b logic l p trnh
th ng s p x p thnh chu i FPGA phn lo i theo
m t
, cng su t tiu tn, i n p ngu n cung
c p, t c
v m t vi m c
khc nhau v c u
trc

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1.2.4. FPGA
FPGA l thi t b c th l p trnh l i v s
cng ngh x l SRAM ho c bn c u ch
trnh cho cc i m n i

d ng
l p

M t
c th n m trong kho ng t vi tr m
module logic
n s p x kho ng 180000 module
logic trong 1 v v i s l ng chn ln n 1000
Ngu n cung c p DC th ng n m trong kho ng
1,2V n 2,5V tu thu c vo lo i chip.

FPGA: XC40xx

I /O

Routing via
Long
switching
lines matrices
I/O

I/O

I/O

I/O

SM

SM

SM

SM

I /O

CLB

SM

CLB

SM

I /O

CLB

SM

CLB

SM

CLB

SM

SM

CLB

SM

SM

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