SCAN, TK AND ATPG

-Mohan

Why DFT?
Why DFT?
Identify defects in chip after Manufacturing
Help to Debug in System Level (Boundary Scan)

Difference between verification and DFT

Verification Checks Functionality of Design
DFT Checks whether Indented Design manufactured correctly

Why not Functional test?

More test time
More Patterns (more memory in ATE)

DFT Overhead:
Area
Power
Routing Congestion
Timing

Goals of DFT
Maximization of test coverage

Maximization of fault coverage

Minimize test patterns

Minimize test time

Ad-Hoc DFT Methods

Good design practices learnt through experience are used

as guidelines:
Avoid asynchronous (unclocked) feedback.
Make flip-flops initializable.
Avoid redundant gates. Avoid large fanin gates.
Provide test control for difficult-to-control signals.
Avoid gated clocks.
Consider ATE requirements (tristates, etc.)

Design reviews conducted by experts or design auditing

tools.
Disadvantages of ad-hoc DFT methods:
Experts and tools not always available.
Test generation is often manual with no guarantee of high fault coverage.
Design iterations may be necessary.

Typical flow for DFT

BIST Insertion
LBIST/MBIST/BSCAN insertion
Scan Insertion
Scan replacement/Test insertion
Compression
Insert comp/decomp/bypass logic
Pattern Generation
Generate the comp/bypass Patterns

Scan Replacement

Mentor -> DFT Advisor

Synopsys -> DFT Compiler
Cadence -> RC Compiler

Test logic Insertion

DRC Violations
S1 - Scanability