8051 - DH Cong Nghiep TP HCm-1

Chng 1: Gii thiu chung v b vi x l.
Trng H Cng nghip Tp.HCM.
CHNG 1
GII THIU CHUNG V B VI X L
I. S PHT TRIN CA CC B VI X L:
1. Th h 1 (1971 - 1973):
c im chung ca cc vi x l th h ny:
Bus d liu: 4 bit.
Bus a ch: 12 bit.
Cng ngh ch to: PMOS.
Tc thc hin lnh: 10 60 s/lnh vi fCLOCK = 0,1 0,8 MHz.
Mt s b vi x l c trng cho th h ny: 4040 (Intel), PPS-4 (Rockwell International),
2. Th h 2 (1974 - 1977):
Bus d liu: 8 bit.
Bus a ch: 16 bit.
Cng ngh ch to: NMOS hoc CMOS.
Tc thc hin lnh: 1 8 s/lnh vi fCLOCK = 1 5 MHz.
Mt s b vi x l c trng cho th h ny: 6502 (Mos Technology), 6800/6809 (Motorola),
8080/8085 (Intel), Z80 (Zilog),
3. Th h 3 (1978 - 1982):
Bus d liu: 16 bit.
Bus a ch: 20 - 24 bit.
Cng ngh ch to: HMOS.
Tc thc hin lnh: 0,1 1 s/lnh vi fCLOCK = 5 10 MHz.
Mt s b vi x l c trng cho th h ny: 68000 / 68010 (Motorola), 8086 / 80186 / 80286
(Intel),
4. Th h 4 (1983 - nay):
Bus d liu: 32 - 64 bit.
Bus a ch: 32 bit.
Cng ngh ch to: HCMOS.
Tc thc hin lnh: 0,01 0,1 s vi fCLOCK = 20 100 MHz.
Mt s b vi x l c trng cho th h ny: 68020 / 68030 / 68040 / 68060 (Motorola), 80386 /
80486 / Pentium (Intel),
II. S KHI CA MT H VI X L:
nh ngha h vi x l:
Kh nng c lp trnh thao tc trn cc d liu m khng cn s can thip ca con
ngi.
Giao trnh Vi x ly.
Bien soan: Pham Quang Tr
Kh nng lu tr v phc hi d liu.

Tng qut, h vi x l gm:
Phn cng (Hardware): cc thit b ngoi vi giao tip vi con ngi.
Phn mm (Software): chng trnh x l d liu.
CPU (Central Processing Unit): n v x l trung tm.

RAM (Random Access Memory): b nh truy xut ngu nhin.
ROM (Read Only Memory): b nh ch c.
Interface Circuitry: mch in giao tip.
Peripheral Devices (Input): cc thit b ngoi vi (thit b nhp).
Peripheral Devices (Output): cc thit b ngoi vi (thit b xut).
Address bus: bus a ch.
Data bus: bus d liu.
Control bus: bus iu khin.
III. N V X L TRUNG TM:
CPU ng vai tr ch o trong h vi x l, n qun l tt c cc hot ng ca h v thc hin
tt c cc thao tc trn d liu.
CPU l mt vi mch in t c tch hp cao. Khi hot ng, CPU c m lnh c ghi di
dng cc bit 0 v bit 1 t b nh, sau n s thc hin gii m cc lnh ny thnh dy cc xung iu
khin tng ng vi cc thao tc trong lnh iu khin cc khi khc thc hin tng bc cc thao
tc v t to ra cc xung iu khin cho ton h.
Giao trnh Vi x ly.
IR (Instruction Register): thanh ghi lnh.

PC (Program Counter / Instruction Pointer): b m chng trnh / con tr lnh.
Instruction decode and control unit: n v gii m lnh v iu khin.
ALU (Arithmetic and Logic Unit): n v s hc v logic.
Registers: cc thanh ghi.
Tm li, khi hot ng CPU s thc hin lin tc 2 thao tc: tm np lnh v gii m thc
hin lnh.
Thao tc tm np lnh:
- Ni dung ca thanh ghi PC c CPU a ln bus a ch (1).
- Tn hiu iu khin c (Read) chuyn sang trng thi tch cc (2).
- M lnh (Opcode) t b nh c a ln bus d liu (3).
- M lnh c chuyn vo trong thanh ghi IR trong CPU (4).
- Ni dung ca thanh ghi PC tng ln mt n v chun b tm np lnh k tip t b nh.
Thao tc gii m thc hin lnh:

- M lnh t thanh ghi IR c a vo n v gii m lnh v iu khin.
- n v gii m lnh v iu khin s thc hin gii m opcode v to ra cc tn hiu
iu khin vic xut nhp d liu gia ALU v cc thanh ghi (Registers).
- Cn c trn cc tn hiu iu khin ny, ALU thc hin cc thao tc c xc nh.
Mt chui cc lnh (Opcode) kt hp li vi nhau thc hin mt cng vic c ngha c
gi l chng trnh (Program) hay phn mm (Software).
IV. B NH BN DN:
B nh bn dn l mt b phn khc rt quan trng ca h vi x l, cc chng trnh v d liu
u c lu gi trong b nh.
B nh bn dn trong h vi x l gm:
ROM: b nh chng trnh lu gi chng trnh iu khin hot ng ca ton h thng.
RAM: b nh d liu lu gi d liu, mt phn chng trnh iu khin h thng, cc
ng dng v kt qu tnh ton.
Giao trnh Vi x ly.
S lc v cu trc v phn loi ROM RAM:

ROM (Read Only Memory): b nh ch c, thng tin trong ROM s khng b mt i ngay
c khi ngun in cung cp cho ROM khng cn.
- Cu trc ROM:
Phn loi mt s loi ROM:

o MROM (Mask ROM): ROM mt n.
o PROM (Programmable ROM): ROM lp trnh c.
o EPROM (Eraseable PROM): ROM lp trnh v xa c.
UV-EPROM (Ultra Violet EPROM): ROM xa bng tia cc tm.
EEPROM (Electric EPROM): ROM lp trnh v xa bng tn hiu in.
Flash ROM: ROM lp trnh v xa bng tn hiu in.
RAM (Random Access Memory): b nh truy xut ngu nhin (b nh ghi c), thng tin
trong RAM s b mt i khi ngun in cung cp cho RAM khng cn..
- Cu trc RAM:
Phn loi mt s loi RAM:

o DRAM (Dynamic RAM): RAM ng
o SRAM (Static RAM): RAM tnh
Cch xc nh dung lng b nh bn dn 8 bit s dng cho chip vi iu khin 8051 nh sau:
Da vo s lng chn a ch:
Dung lng = 2N , vi N l s ng a ch ca b nh.
V d: B nh bn dn 8 bit c 10 ng a ch. Cho bit dung lng ca b nh l bao nhiu?
N = 10 Dung lng = 210 = 1024 = 1 KB
Giao trnh Vi x ly.
Da vo m s ca b nh:
M s: XX YYYY
XX: loi b nh
27: UV-EPROM
28: EEPROM
61,62: SRAM
40,41: DRAM
YYYY: dung lng b nh
Dung lng = YYYY (Kbit) hoc Dung lng = YYYY / 8 (KB)
V d: B nh c m s 27256, dung lng ca b nh l bao nhiu ?

27 B nh UV-EPROM
256 Dung lng = 256 (Kbit) = 32 (KB)
V. CC THIT B NGOI VI (CC THIT B XUT NHP):
Mch in giao tip (Interface Circuitry) v cc thit b xut nhp hay thit b ngoi vi
(Peripheral Devices) to ra kh nng giao tip gia h vi x l vi th gii bn ngoi. B phn giao
tip gia bus h thng ca h vi x l vi cc th gii bn ngoi thng c gi l cng (Port). Nh
vy ty theo tng loi thit b giao tip m ta c cc cng nhp (Input) ly thng tin t ngoi vo h
v cc cng xut (Output) a thng tin t trong h ra ngoi.
Tng qut, ta c 3 loi thit b xut nhp sau:
Thit b lu tr ln: bng t, a t, a quang,
Thit b giao tip vi con ngi: mn hnh, bn phm, my in,
Thit b iu khin / kim tra: cc b kch thch, cc b cm bin,
VI. H THNG BUS:
Bus l tp hp cc ng dy mang thng tin c cng chc nng. Vic truy xut thng tin ti
mt mch in xung quanh CPU th n s dng 3 loi bus: bus a ch, bus d liu v bus iu khin.
CPU s dng h thng bus ny thc hin cc thao tc c (READ) v ghi (WRITE) thng tin gia
CPU vi b nh hoc cc thit b ngoi vi.
Bus a ch (Address bus):
- chuyn ti thng tin ca cc bit a ch.
- L loi bus 1 chiu (CPU MEM hay I/O).
- xc nh b nh hoc thit b ngoi vi m CPU cn trao i thng tin.
- xc nh dung lng b nh hoc ngoi vi m CPU c kh nng truy xut.
Bus d liu (Data bus):
- chuyn ti thng tin ca cc bit d liu.
- L loi bus 2 chiu (CPU MEM hay I/O).
- xc nh s bit d liu m CPU c kh nng x l cng mt lc.
Bus iu khin (Control bus):
- chuyn ti thng tin ca cc bit iu khin (mi ng dy l mt tn hiu iu khin
khc nhau).
- L loi bus 1 chiu (CPU MEM-I/O hoc MEM-I/O CPU).
- iu khin cc khi khc trong h v nhn tn hiu iu khin t cc khi phi
hp hot ng.
Giao trnh Vi x ly.
VII. VI X L VI IU KHIN:
phn bit b vi x l v b vi iu khin ta c th da trn cc yu t nh sau:
Yu t phn loi
Cu trc phn cng

(Hardware
architecture)
Cc ngdng
(Applications)
Cc c trng ca
tp lnh
(Instruction set
feature)
CPU
ROM
RAM
Mch giao tip ni
tip
Mch giao tip song
song
Mch iu khin ngt
Cc mch iu khin
khc
ng dng ln, tnh
ton phc tp
ng dng nh, tnh
ton n gin
Cc kiu nh a ch
di t d liu x
l
Vi x l
(Microprocessor)
X
Vi iu khin
(Microcontroller)
X
X
X
X
X
X
X
X
X
Nhiu
Byte, Word, Double word,
Bit, Byte
VIII. MINH HA KIN TRC CA MT H VI IU KHIN:
WDT (Watch-Dog Timer): B nh thi Watch-Dog.

OSC., OSC/N (Oscillator): B dao ng (N: h s chia tn).
Timer: B nh thi.
A/D (Analog/Digital): B bin i tn hiu tng t/s.
SFR Registers (Special Function Register): Cc thanh ghi chc nng c bit.
RAM Memory: B nh d liu.
Giao trnh Vi x ly.
Program Memory: B nh chng trnh.

EEPROM: B nh EEPROM.
I/O Ports: Cc port xut/nhp.
Instruction Decoder: B gii m lnh.
ALU: n v logic v s hc.
Accumulator: Thanh ghi tch ly.
Control Logic: iu khin logic.
Program Counter: B m chng trnh.
Instructions/Addresses: Cc lnh / a ch.
IX. LA CHN B VI IU KHIN KHI THIT K:
C bn h vi iu khin thng dng trn th trng hin nay l: 68xxx ca Motorola, 80xxx ca
Intel, Z8xx ca Zilog v PIC16xxx ca Microchip Technology. Mi loi vi iu khin trn u c mt
tp lnh v thanh ghi ring nn chng khng tng thch ln nhau. Vy khi ta tin hnh thit k mt h
thng s dng vi iu khin th ta cn da trn nhng tiu chun no? C ba tiu chn chnh:
Tiu chun th nht l: p ng yu cu tnh ton mt cch hiu qu v kinh t. Do vy,
trc tin ta cn phi xem xt b vi iu khin 8 bit, 16 bit hay 32 bit l thch hp nht. Mt s tham s
k thut cn c cn nhc khi chn la l:
o Tc : tc ln nht m vi iu khin h tr l bao nhiu.
o Kiu IC: l kiu 40 chn DIP, QFP hay l kiu ng v khc (DIP: v dng hai hng
chn, QFP: v vung dt). Kiu ng v rt quan trng khi c yu cu v khng gian, kiu lp rp v
to mu th cho sn phm cui cng.
o Cng sut tiu th: l mt tiu chun cn c bit lu nu sn phm dng pin hoc
in p li.
o Dung lng b nh ROM v RAM tch hp sn trn chip.
o S chn vo/ra v b nh thi trn chip.
o Kh nng d dng nng cao hiu sut hoc gim cng sut tiu th.
o Gi thnh trn mt n v khi mua s lng ln. V y l vn c nh hng n gi
thnh cui cng ca sn phm.
Tiu chun th hai l: C sn cc cng c pht trin phn mm, chng hn nh cc chng
trnh m phng, trnh bin dch, trnh hp dch v g ri.
Tiu chun th ba l: Kh nng p ng v s lng hin ti cng nh tng lai. i
vi mt s nh thit k th tiu chun ny thm ch cn quan trng hn c hai tiu chun trn.
Giao trnh Vi x ly.
Chng 2: Phn cng chip vi iu khin 8051.
CHNG 2
PHN CNG CHIP VI IU KHIN 8051
I. TNG QUT:
1. Gii thiu chung:
MCS-51 l h vi iu khin ca hng Intel. Vi mch tng qut ca h MCS-51 l chip 8051.
Chip 8051 c mt s c trng c bn sau:
- B nh chng trnh bn trong: 4 KB (ROM).
- B nh d liu bn trong: 128 byte (RAM).
- B nh chng trnh bn ngoi: 64 KB (ROM).
- B nh d liu bn ngoi: 64 KB (RAM).
- 4 port xut nhp (I/O port) 8 bit.
- 2 b nh thi 16 bit.
- Mch giao tip ni tip.
- B x l bit (thao tc trn cc bit ring l).
- 210 v tr nh c nh a ch, mi v tr 1 bit.
- Nhn / Chia trong 4 s.
Ngoi ra, trong h MCS-51 cn c mt s chip vi iu khin khc c cu trc tng ng nh:
Chip
8031
8032
8051
8052
8751
8752
8951
8952
ROM trong
0 KB
0 KB
4 KB PROM
8 KB PROM
4 KB UV-EPROM
8 KB UV-EPROM
4 KB FLASH ROM
8 KB FLASH ROM
RAM trong
128 byte
256 byte
128 byte
256 byte
128 byte
256 byte
128 byte
256 byte
B nh thi
2
3
2
3
2
3
2
3
2. Cc phin bn ca chip vi iu khin 8051:

2.1
B vi iu khin 8031:
8031 l mt phin bn khc ca h 8051. Chip ny thng c coi l 8051 khng c ROM trn
chip. c th dng c chip ny cn phi b sung thm ROM ngoi cha chng trnh cn thit cho
8031. 8051 c chng trnh c cha ROM trn chip b gii hn n 4KB, cn ROM ngoi ca
8031 th c th ln n 64KB. Tuy nhin, c th truy cp ht b nh ROM ngoi th cn dng thm
hai cng (Port 0 v Port 2) , do vy ch cn li c hai cng (Port 1 v Port 3) s dng. Nhm khc
phc vn ny, chng ta c th b sung thm cng vo/ra cho 8031.
2.2
B vi iu khin 8052:
8052 l mt phin bn ca h 8051. 8052 c tt c cc thng s k thut ca 8051, ngoi ra cn

c thm 128 byte RAM, 4KB ROM v mt b nh thi na. Nh vy, 8052 c tng cng 256 byte
RAM, 8KB ROM v ba b nh thi.
Gio trnh Vi x l.
Bin son: Phm Quang Tr

c tnh k thut
8031
8051
8052
ROM trn chip (KB)
RAM trn chip (byte)
128
128
256
B nh thi
Chn vo/ra
32
32
32
Cng ni tip
Ngun ngt
Nh bng thng s trn ta thy 8051 l mt trng hp ring ca 8052. Mi chng trnh vit
cho 8051 u c th chy c trn 8052 nhng iu ngc li c th l khng ng.
2.3
B vi iu khin 8751:
Chip 8751 ch c 4KB b nh UV-EPROM trn chip. s dng chip ny cn phi c thit b
lp trnh PROM v thit b xo UV-EPROM. Do ROM trn chip ca 8751 l UV-EPROM, nn cn
phi mt khong 20 pht xo 8751 trc khi c lp trnh. V y l qu trnh mt nhiu thi gian
nn nhiu nh sn xut cho ra phin bn Flash ROM v UV-RAM.
2.4
B vi iu khin AT8951 ca Atmel Corporation:
AT8951 l phin bn 8051 c ROM trn chip l b nh Flash. Phin bn ny rt thch hp cho
cc ng dng nhanh v b nh Flash c th c xa trong vi giy. D nhin l dng AT8951 cn
phi c thit b lp trnh PROM h tr b nh Flash nhng khng cn n thit b xa ROM v b nh
Flash c xa bng thit b lp trnh PROM. tin s dng, hin nay hng Atmel ang nghin cu
mt phin bn ca AT8951 c th c lp trnh qua cng COM ca my tnh PC v nh vy s khng
cn n thit b lp trnh PROM.
K hiu
ROM
RAM
I/O
Timer
Ngt
Vcc
S chn IC
AT89C51
4KB
128
32
5V
40
AT89LV51
4KB
128
32
3V
40
AT89C1051
1KB
64
15
3V
20
AT89C2051
2KB
128
15
3V
20
AT89C52
8KB
256
32
5V
40
AT89LV52
8KB
256
32
3V
40
2.5
B vi iu khin DS5000 ca Dallas Semiconductor:
Mt phin bn ph bin khc na ca 8051 l DS5000 ca hng Dallas Semiconductor. B nh

ROM trn chip ca DS5000 l NV-RAM. DS5000 c kh nng np chng trnh vo ROM trn chip
trong khi n vn trong h thng m khng cn phi ly ra. Cch thc hin l dng qua cng COM
Gio trnh Vi x l.
ca my tnh PC. y l mt im mnh rt c a chung. Ngoi ra, NV-RAM cn c u vit l cho

php thay i ni dung RAM theo tng byte m khng cn phi xa ht trc khi lp trnh nh b nh
EPROM.
K hiu
ROM
RAM
I/O
Timer
Ngt
Vcc
S chn IC
DS5000-8
8KB
128
32
5V
40
DS5000-32
32KB
128
32
5V
40
DS5000T-8
8KB
128
32
5V
40
DS5000T-32
32KB
128
32
5V
40
im c bit l cc chip c ch T theo sau k hiu 5000 c ngha l chip c thit k

thm mt ng h thi gian thc (RTC: Real Time Clock) bn trong. Lu ng h thi gian thc RTC
hon ton khc vi b nh thi Timer. RTC to v lu gi thi gian ca ngy (gi/pht/giy) v ngy
thng (ngy/thng/nm) trn thc t ngay c khi khng c ngun cung cp.
2.6
B vi iu khin P89V51xx ca Philips Corporation:
y l mt phin bn ci tin s dng CPU l b vi iu khin 80C51 vi nhiu tnh nng vt

tri: dung lng ROM/RAM trn chip rt ln, 3 Timer 16 bit + 1 Watch-dog Timer, 2 thanh ghi DPTR,
8 ngun ngt, PWM (Pulse Width Modulator), SPI (Serial Peripheral Interface) v c bit l b nh
chng trnh trn chip c tnh nng ISP (In-System Programming) v IAP (In-Application
Programming),
II. CC CHN CA CHIP 8051:
1. S khi v chc nng cc khi ca chip 8051:
Gio trnh Vi x l.
10
- CPU (Central Processing Unit): n v x l trung tm tnh ton v iu khin qu

trnh hot ng ca h thng.
- OSC (Oscillator): Mch dao ng to tn hiu xung clock cung cp cho cc khi trong
chip hot ng.
- Interrupt control: iu khin ngt nhn tn hiu ngt t bn ngoi (INT0\, INT1\), t
b nh thi (Timer 0, Timer 1) v t cng ni tip (Serial port), ln lt a cc tn hiu ngt ny n
CPU x l.
- Other registers: Cc thanh ghi khc lu tr d liu ca cc port xut/nhp, trng thi
lm vic ca cc khi trong chip trong sut qu trnh hot ng ca h thng.
- RAM (Random Access Memory): B nh d liu trong chip lu tr cc d liu.
- ROM (Read Only Memory): B nh chng trnh trong chip lu tr chng trnh
hot ng ca chip.
- I/O ports (In/Out ports): Cc port xut/nhp iu khin vic xut nhp d liu di
dng song song gia trong v ngoi chip thng qua cc port P0, P1, P2, P3.
- Serial port: Port ni tip iu khin vic xut nhp d liu di dng ni tip gia
trong v ngoi chip thng qua cc chn TxD, RxD.
- Timer 0, Timer 1: B nh thi 0, 1 dng nh thi gian hoc m s kin (m
xung) thng qua cc chn T0, T1.
- Bus control: iu khin bus iu khin hot ng ca h thng bus v vic di chuyn
thng tin trn h thng bus.
- Bus system: H thng bus lin kt cc khi trong chip li vi nhau.
2. S chn v chc nng cc chn ca chip 8051:
Gio trnh Vi x l.
11
2.1.
Port 0:
Port 0 (P0.0 P0.7) c s chn t 32 39.
Port 0 c hai chc nng:
Port xut nhp d liu (P0.0 - P0.7) khng s dng b nh ngoi.
Bus a ch byte thp v bus d liu a hp (AD0 AD7) c s dng b nh
ngoi.
Lu : Khi Port 0 ng vai tr l port xut nhp d liu th phi s dng cc in tr ko ln
bn ngoi.
- ch mc nh (khi reset) th cc chn Port 0 (P0.0 - P0.7) c cu hnh l port xut
d liu. Mun cc chn Port 0 lm port nhp d liu th cn phi lp trnh li, bng cch ghi mc logic
cao (mc 1) n tt c cc bit ca port trc khi bt u nhp d liu t port (vn ny c trnh
by phn k tip).
- Khi lp trnh cho ROM trong chip th Port 0 ng vai tr l ng vo ca d liu (D0 D7)
(xem sch H vi iu khin 8051 trang 333-352).
-
2.2.
Port 1:
Port 1 (P1.0 P1.7) c s chn t 1 8.
Port 1 c mt chc nng:
Port xut nhp d liu (P1.0 P1.7) s dng hoc khng s dng b nh
ngoi.
- ch mc nh (khi reset) th cc chn Port 1 (P1.0 P1.7) c cu hnh l port xut
by phn k tip).
- Khi lp trnh cho ROM trong chip th Port 1 ng vai tr l ng vo ca a ch byte thp
(A0 A7) (xem sch H vi iu khin 8051 trang 333-352).
-
2.3.
Port 2:
- Port 2 (P2.0 P2.7) c s chn t 21 28.
- Port 2 c hai chc nng:
Port xut nhp d liu (P2.0 P2.7) khng s dng b nh ngoi.
Bus a ch byte cao (A8 A15) c s dng b nh ngoi.
by phn k tip).
- Khi lp trnh cho ROM trong chip th Port 2 ng vai tr l ng vo ca a ch byte cao (A8
A11) v cc tn hiu iu khin (xem sch H vi iu khin 8051 trang 333-352).
2.4.
Port 3:
Port 3 (P3.0 P3.7) c s chn t 10 17.
Port 3 c hai chc nng:
Port xut nhp d liu (P3.0 P3.7) khng s dng b nh ngoi hoc cc
chc nng c bit.
Cc tn hiu iu khin c s dng b nh ngoi hoc cc chc nng c bit.
by phn k tip).
-
Gio trnh Vi x l.
12
- Khi lp trnh cho ROM trong chip th Port 3 ng vai tr l ng vo ca cc tn hiu iu

khin (xem sch H vi iu khin 8051 trang 333-352).
- Chc nng ca cc chn Port 3:
Bit
Tn
a ch bit
Chc nng
P3.0
RxD
B0H
Chn nhn d liu ca port ni tip.
P3.1
TxD
B1H
Chn pht d liu ca port ni tip.
P3.2
INT0\
B2H
Ng vo ngt ngoi 0.
P3.3
INT1\
B3H
Ng vo ngt ngoi 1.
P3.4
T0
B4H
Ng vo ca b nh thi/m 0.
P3.5
T1
B5H
Ng vo ca b nh thi/m 1.
P3.6
WR\
B6H
iu khin ghi vo RAM ngoi.
P3.7
RD\
B7H
iu khin c t RAM ngoi.
2.5.
Chn PSEN\:
- PSEN (Program Store Enable): cho php b nh chng trnh, chn s 29.
- Chc nng:
L tn hiu cho php truy xut (c) b nh chng trnh (ROM) ngoi.
L tn hiu xut, tch cc mc thp.
PSEN\ = 0 trong thi gian CPU tm - np lnh t ROM ngoi.
PSEN\ = 1 CPU s dng ROM trong (khng s dng ROM ngoi).
- Khi s dng b nh chng trnh bn ngoi, chn PSEN\ thng c ni vi chn OE\ ca
ROM ngoi cho php CPU c m lnh t ROM ngoi.
2.6.
Chn ALE:
- ALE (Address Latch Enable): cho php cht a ch, chn s 30.
- Chc nng:
L tn hiu cho php cht a ch thc hin vic gii a hp cho bus a ch
byte thp v bus d liu a hp (AD0 AD7).
L tn hiu xut, tch cc mc cao.
ALE = 0 trong thi gian bus AD0 - AD7 ng vai tr l bus D0 - D7.
ALE = 1 trong thi gian bus AD0 - AD7 ng vai tr l bus A0 - A7.
- Khi lp trnh cho ROM trong chip th chn ALE ng vai tr l ng vo ca xung lp trnh
(PGM\) (xem sch H vi iu khin 8051 trang 333-352).
Lu : f ALE = fOSC c th dng lm xung clock cho cc mch khc.
6
fALE (MHz): tn s xung ti chn ALE.
fOSC (MHz): tn s dao ng trn chip (tn s thch anh).
- Khi lnh ly d liu t RAM ngoi (MOVX) c thc hin th mt xung ALE b b qua
(xem gin trang 38-39 sch H vi iu khin 8051).
2.7.
-
Chn EA\:
EA (External Access): truy xut ngoi, chn s 31.
Chc nng:
L tn hiu cho php truy xut (s dng) b nh chng trnh (ROM) ngoi.
Gio trnh Vi x l.
13
L tn hiu nhp, tch cc mc thp.

EA\ = 0 Chip 8051 s dng chng trnh ca ROM ngoi.
EA\ = 1 Chip 8051 s dng chng trnh ca ROM trong.
- Khi lp trnh cho ROM trong chip th chn EA ng vai tr l ng vo ca in p lp trnh
(Vpp = 12V 12,5V cho h 89xx; 21V cho h 80xx, 87xx) (xem sch H vi iu khin 8051 trang
333-352).
Lu : Chn EA\ phi c ni ln Vcc (nu s dng chng trnh ca ROM trong) hoc ni
xung GND (nu s dng chng trnh ca ROM ngoi), khng bao gi c php b trng chn ny.
2.8.
Chn XTAL1, XTAL2:

- XTAL (Crystal): tinh th thch anh, chn s 18-19.
- Chc nng:
Dng ni vi thch anh hoc mch dao ng to xung clock bn ngoi, cung
cp tn hiu xung clock cho chip hot ng.
XTAL1 ng vo mch to xung clock trong chip.
XTAL2 ng ra mch to xung clock trong chip.
Lu :
fTYP (MHz): tn s danh nh.
fTYP = 12MHz
2.9.
Chn RST:
RST (Reset): thit lp li, chn s 9.
Chc nng:
L tn hiu cho php thit lp (t) li trng thi ban u cho h thng.
L tn hiu nhp, tch cc mc cao.
RST = 0 Chip 8051 hot ng bnh thng.
RST = 1 Chip 8051 c thit lp li trng thi ban u.
12
Lu :
tRe set 2 TMachine
TMachine =
f OSC
fOSC (MHz): tn s thch anh.
tRESET (s): thi gian reset.
TMACHINE (s): chu k my.
-
Gio trnh Vi x l.
14
V d: Xc nh chu k my v thi gian reset tng ng cho tng trng hp fOSC = 11,0592MHz,
fOSC = 12MHz v fOSC = 16MHz.
Gii
fOSC = 11,0592MHz TMACHINE = 1,085s v tRESET 2,17s.
fOSC = 12MHz TMACHINE = 1s v tRESET 2s.
fOSC = 16MHz TMACHINE = 0,75s v tRESET 1,5s
2.10. Chn Vcc, GND:
- Vcc, GND: ngun cp in, chn s 40 v 20.
- Chc nng:
Cung cp ngun in cho chip 8051 hot ng.
Vcc = +5V 10% v GND = 0V.
III. CU TRC CC PORT XUT NHP CHIP 8051:
Kh nng fanout (s lng ti u ra) ca cc tng chn port chip 8051 l:
Port 0: 8 ti TTL.
Port 1: 4 ti TTL.
Port 2: 4 ti TTL.
Port 3: 4 ti TTL.
Lu :
Khi Port 0 ng vai tr l port xut nhp th s khng c in tr ko ln bn trong do
ngi s dng cn thm vo in tr ko ln bn ngoi (xem Hnh III.1).
ch mc nh (khi reset) th tt c cc chn ca cc port (P0 P3) c cu hnh l

port xut d liu.
Mun cc chn port ca chip 8015 lm port nhp d liu th ta cn phi c lp trnh li,
bng cch ghi mc logic cao (mc 1) n tt c cc bit (cc chn) ca port trc khi bt u nhp d
liu t port (vn ny c trnh by phn k tip).
Gio trnh Vi x l.
15
Cc chn trong cng mt port khng nht thit phi c cng kiu cu hnh (port xut hoc
port nhp). Ngha l trong cng mt port c th c chn dng nhp d liu, c th c chn dng
xut d liu. iu ny l ty thuc vo nhu cu v mc ch ca ngi lp trnh.
Qu trnh ghi chn port (xut d liu ra chn port).
Qu trnh c chn port (nhp d liu t chn port).
Qu trnh c b cht (kim tra d liu ti chn port).
Gio trnh Vi x l.
16
Lu : Vic c d liu ca bt k mt port no c th cho ta hai gi tr khc nhau ty thuc

vo lnh m ta s dng c d liu t port (xem thm trong phn tp lnh). Xy ra hin tng
khng mong mun ny l do qu trnh c d liu ca chip 8051 gm hai qu trnh khc nhau: qu
trnh c chn port v qu trnh c b cht.
o Qu trnh c chn port: Khi ta s dng cc lnh MOV, ADD, D liu nhn
c sau khi thc hin qu trnh c l d liu hin ti cc chn port.
o Qu trnh c b cht: Khi ta s dng cc lnh ANL, ORL, XRL, CPL, INC,
DEC, DJNZ, JBC, CLR bit, SETB bit, MOV bit. D liu nhn c sau khi thc hin qu trnh c l
d liu hin ti cc b cht (l cc d liu c ghi ra port ti thi im trc bi qu trnh
ghi chn port), ch khng phi l d liu hin ti cc chn port. Cho nn, nu ti thi im thc hin
qu trnh c m d liu ti cc chn port c b thay i i chng na th d liu c v cng khng
c cp nht.
IV. T CHC B NH CA CHIP 8051:
-
B vi x l c khng gian b nh chung cho d liu v chng trnh.
chng trnh v d liu nm chung trn RAM trc khi a vo CPU thc thi.
-
B vi iu khin c khng gian b nh ring cho d liu v chng trnh.
chng trnh v d liu nm ring trn ROM v RAM trc khi a vo CPU thc thi.
-
T chc b nh ca chip 8051:
Gio trnh Vi x l.
17
1. B nh trong:
Gio trnh Vi x l.
18
1.1. B nh chng trnh (ROM):

- Dng lu tr chng trnh iu khin cho chip 8051 hot ng.
- Chip 8051 c 4 KB ROM trong, a ch truy xut: 000H FFFH.
1.2. B nh d liu (RAM):
- Dng lu tr cc d liu v tham s.
- Chip 8051 c 128 byte RAM trong, a ch truy xut: 00H 7FH.
- RAM trong ca chip 8051 c chia ra:
RAM a chc nng:
RAM nh a ch bit:
cho php x l tng bit d liu ring l m khng nh hng n cc bit khc trong c byte.
Lu : Nu trong chng trnh khng s dng cc bit trong vng RAM nh a ch bit ny, ta
c th s dng vng nh 20H 2FH cho cc mc ch khc ca ta. Ngc li, ta phi vit chng trnh
cn thn khi s dng vng nh 20H 2FH v nu s sut ta c th ghi d liu ln cc bit c s
dng.
V d: Vit lnh lm cho 8 bit trong nh c a ch 20H thuc RAM ni c gi tr l 1 (xt
trng hp a ch byte v a ch bit).
Gio trnh Vi x l.
19
Cc dy thanh ghi:
cho php truy xut d liu nhanh, lnh truy xut n gin v ngn gn.
Bng s liu di y minh ha a ch ca cc nh trong mt dy v cc k hiu thanh ghi

R0 R7 c gn cho tng nh trong dy tch cc.
Lu :
o
ch mc nh th dy thanh ghi tch cc (ang c s dng) l dy 0 v cc thanh
ghi trong dy ln lt c tn l R0 - R7. C th thay i dy tch cc bng cch thay i cc bit chn
dy thanh ghi RS1 v RS0 trong thanh ghi PSW (xem phn thanh ghi PSW).
o
Nu chng trnh ca ta ch s dng dy thanh ghi u tin (dy 0) th ta c th s dng
vng nh 08H 1FH cho cc mc ch khc ca ta. Nhng nu trong chng trnh c s dng cc dy
thanh ghi (dy 1, 2 hoc 3) th phi rt cn thn khi s dng vng nh t 1FH tr xung v nu s sut
ta c th ghi d liu ln cc thanh ghi R0 R7 ca ta.
V d 1: Quan h gia k hiu thanh ghi R4 vi cc nh c a ch tng ng trong dy thanh
ghi tch cc?
o
Nu dy 0 tch cc: Thanh ghi R4 nh 04H RAM ni.
o
Nu dy 1 tch cc: Thanh ghi R4 nh 0CH RAM ni.
o
Nu dy 2 tch cc: Thanh ghi R4 nh 14H RAM ni.
o
Nu dy 3 tch cc: Thanh ghi R4 nh 1CH RAM ni.
V d 2: Khi chip 8051 thc hin lnh MOV R4, #1AH th gi tr 1AH s c np vo trong
nh c a ch l bao nhiu thuc RAM ni. Xt tng ng cho tng trng hp dy thanh ghi tch
cc l Dy 0 v Dy 3?
Gio trnh Vi x l.
20
1.3. Thanh ghi chc nng c bit (SFR):
Lu :
o
Khng c php c hay ghi d liu vo cc a ch SFR m n cha c ng k
(ngha l cc a ch SFR cha c t tn). V vic c hay ghi d liu vo cc ni ny c th lm
pht sinh nhng hot ng khng mong mun v c th l nguyn nhn lm cho chng trnh ca ta
khng tng thch vi cc phin bn sau ca chip MCS-51 (c th cc phin bn cc a ch SFR
ny c s dng cho mt vi mc ch khc).
o
Ch c truy xut cc SFR bng kiu nh a ch trc tip (tuyt i khng s
dng kiu nh a ch gin tip trong trng hp ny).
V d: Cho bit trc (R0)=90H. Vit lnh dng xut (ghi) gi tr 5AH ra Port1 nh sau (xem
gii thch lnh trong Chng 3: Tp lnh ca 8051.):
S dng kiu nh a ch trc tip:
MOV P1, #5AH
hoc
MOV 90H, #5AH
S dng kiu nh a ch gin tip:
MOV @R0, #5AH

SAI
iu ny khng hp l i vi chip 8051 v phng php nh a ch gin tip nh trn
ch s dng cho vng nh RAM ni. Trong khi RAM ni ca chip 8051 ch c 128 byte (00H
7FH), cho nn khi thc hin lnh ny n s tr v kt qu khng xc nh. (Lu : nu ta dng phin
bn chip 8052 th s trnh c iu ny).
1.3.1. Thanh ghi A:
Accumulator: thanh ghi tch luy
Thanh ghi
A
E0H E7 E6 E5 E4 E3 E2 E1 E0
a ch byte: E0H
a ch bit: E0H - E7H
Cong dung: cha d lieu cua cac phep toan
ma vi ieu khien x ly
1.3.2. Thanh ghi B:
Php nhn 2 s 8 bit khng du kt qu l s 16 bit.

Byte cao cha vo thanh ghi B.
Byte thp cha vo thanh ghi A.
Php chia 2 s 8 bit thng s v s d l s 8 bit.
Gio trnh Vi x l.
21
Thng s cha vo thanh ghi A.

S d cha vo thanh ghi B.
V d: Thc hin php tnh 12H x 2AH. Hi (A)=?, (B)=?
(B)
x1
2
B
2 4
0 2 F
2 H
A H
4
4 H
(A) = F4H
(B) = 02H
(A)
V d: Thc hin php tnh A6H : 21H. Hi (A)=?, (B)=?
V d: Thc hin php tnh FDH : 0CH. Hi (A)=?, (B)=?
1.3.3. Thanh ghi t PSW:
C CY (Carry Flag): c nh bo c nh/mn ti bit 7.

CY = 0: nu khng c nh t bit 7 hoc khng c mn cho bit 7.
CY = 1: nu c nh t bit 7 hoc c mn cho bit 7.
C AC (Auxiliary Carry): c nh ph bo c nh/mn ti bit 3.

AC = 0: nu khng c nh t bit 3 hoc khng c mn cho bit 3.
AC = 1: nu c nh t bit 3 hoc c mn cho bit 3.
- C F0 (Flag 0): c zero c nhiu mc ch dnh cho cc ng dng khc nhau ca

ngi lp trnh (d tr cho cc phin bn chip trong tng lai).
Gio trnh Vi x l.
22
- Bit RS0, RS1 (Register Select): bit chn dy thanh ghi cho php xc nh dy thanh
ghi tch cc (hay dy thanh ghi m cc thanh ghi c tn l R0-R7).
RS1
0
0
1
1
RS0
0
1
0
1
Dy thanh ghi
Dy 0
Dy 1
Dy 2
Dy 3
R0 R7
00H 07H
08H 0FH
10H 17H
18H 1FH
- C OV (Overflow): c trn bo kt qu tnh ton ca php ton s hc (php ton c

du) c nm trong khong t -128 n +127 hay khng.
OV = 0: nu -128 kt qu +127.
OV = 1: nu kt qu < -128 hoc kt qu > +127. Ni cch khc l: i vi php
cng th OV=1 nu c nh t bit 7 nhng khng c nh t bit 6 hoc nu c nh t bit 6 nhng khng
c nh t bit 7. i vi php tr th OV=1 nu c mn cho bit 7 nhng khng c mn cho bit 6
hoc nu c mn bit 6 nhng khng c mn bit 7.
- C P (Parity): c chn l bo s ch s 1 trong thanh ghi A l s chn hay s l (trong

chip 8051 s dng ch parity chn).
P = 0: nu s ch s 1 trong thanh ghi A l s chn (parity chn).
P = 1: nu s ch s 1 trong thanh ghi A l s l (parity chn).
V d: Minh ha cch 8051 biu din s -5.
Gii
Cc bc thc hin:
0000 0101
Biu din s 5 dng nh phn 8 bit.
B1:
B2:
1111 1010
Ly b 1.
1111 1011
Ly b 2.
B3:
Vy s FBH l biu din s c du dng b 2 ca s -5.
V d: Minh ha cch 8051 biu din s -34H.
Cc bc thc hin:
0011 0100
Biu din s 34H dng nh phn 8 bit.
B1:
B2:
1100 1011
Ly b 1.
1100 1100
Ly b 2.
B3:
Vy s CCH l biu din s c du dng b 2 ca s -34H.
Gio trnh Vi x l.
23
V d: Minh ha cch 8051 biu din s -128.
Cc bc thc hin:
B1:
1000 0000
Biu din s -128 dng nh phn 8 bit.
B2:
0111 1111
Ly b 1.
1000 0000
Ly b 2.
B3:
Vy s 80H l biu din s c du dng b 2 ca s -128.
V d: Minh ha trng thi hot ng ca cc c CY, AC, OV v P khi thc hin php cng/tr
s hc hai gi tr vi nhau.
C nh (CY):
Minh ha hot ng ca c CY trong trng hp CY = 1:
Xt c CY trong hai trng hp 7AH+28H v 9AH-5DH:
Xt c CY trong hai trng hp 95H+86H v 00H-A6H:
C nh ph (AC):
Minh ha hot ng ca c AC trong trng hp AC = 1

AC=1
B
+
7 6 5 4 3 2 1 0 B
7 6 5 4 3 2 1 0
AC=1
Gio trnh Vi x l.
Kieu BIN
+
AC=1
H L
H L
B
7 6 5 4 3 2 1 0 B
7 6 5 4 3 2 1 0
H
H
AC=1
-
H L
H L
H
H
Kieu BIN
Kieu HEX
24
Kieu HEX
Xt c AC trong hai trng hp 92H+28H v 4AH-E3H:
Xt c AC trong hai trng hp 7AH+59H v 97H-5DH:
C trn (OV):
Minh ha hot ng ca c OV trong trng hp OV = 1
Xt c OV trong cc trng hp B3H+25H, BBH+C9H, BBH-96H v 4BH-F3H:
Xt c OV trong cc trng hp 53H+45H, 82H+BAH, 9AH-3EH v 66H-DAH:
C Parity (P):
Xt c P trong cc trng hp (A)=45H, (A)=E7H, (A)=00H:
Gio trnh Vi x l.
25
V d: Xc nh ni dung cc nh thuc RAM ni ca on chng trnh sau:
V d: Xc nh ni dung cc nh thuc RAM ni ca on chng trnh sau:
1.3.4. Thanh ghi SP:
- Ngn xp l vng nh dng lu tr tm thi cc d liu.

- i vi chip 8051 th vng nh c dng lm ngn xp c gi trong RAM ni.
- s dng ngn xp th ta phi khi ng thanh ghi SP (ngha l np gi tr cho thanh
ghi SP) vng nh ca ngn xp c a ch bt u: (SP)+1 v a ch kt thc: 7FH.
- Nu khng khi ng SP vng nh ca ngn xp c a ch bt u: 08H v a ch
kt thc: 7FH (ch mc nh).
Lu : Trong trng hp khng khi ng SP (ch mc nh) th dy thanh ghi 1 (v c th
l dy 2 v dy 3) s khng cn hp l v khi vng nh ny c s dng lm ngn xp. iu
ny c ngha l nu ta s dng cc dy thanh ghi ny v lu tr d liu vo th c kh nng s b
mt do tc ng ct d liu vo ngn xp ca cc lnh (PUSH, ACALL, LCALL, ).
Gio trnh Vi x l.
26
V d: Hy cho bit tm a ch ca vng nh ngn xp trong hai trng hp sau: (SP)=5FH v
(SP)=49H.
Theo qui nh th vng nh ca ngn xp c a ch bt u: (SP)+1 v a ch kt thc: 7FH.

Trng hp (SP)=5FH: tm a ch ca vng nh ngn xp l 60H - 7FH.
Trng hp (SP)=49H: tm a ch ca vng nh ngn xp l 4AH - 7FH.
V d: Hy cho bit gi tr cn phi np cho thanh ghi SP vng nh ngn xp c tm a ch

trong hai trng hp sau: 62H 7FH v 50H 7FH.
Theo qui nh th vng nh ca ngn xp c a ch bt u: (SP)+1 v a ch kt thc: 7FH.
Trng hp 62H 7FH: gi tr cn np cho thanh ghi SP l 61H.
Trng hp 50H 7FH: gi tr cn np cho thanh ghi SP l 4FH.
V d: Minh ha vng nh ngn xp trong trng hp khng khi ng SP (ch mc nh) v

c khi ng SP (vi (SP) = 3FH).
Stack
memory
Stack memory
Nu ngi s dng khng khi ng thanh ghi SP (ch mc nh) th: (xem hnh bn
di, pha tri)
Nu ngi s dng mun vng nh ngn xp (ch ty nh) c tm a ch l 40H7FH

th: (xem hnh bn trn, pha phi)
1.3.5. Thanh ghi DPTR:
Data Pointer Register: thanh ghi con tro d lieu
Thanh ghi
DPTR
83H
DPH
82H
a ch byte: 83H va 82H
DPL
a ch bit: khong nh a ch bit

Cong dung: la thanh ghi 16 bit (DPH+DPL), cha a ch cua o
nh can truy xuat thuoc ROM (trong/ngoai) va RAM ngoai.
Gio trnh Vi x l.
27
V d: Khi ta mun truy xut (ghi/c) d liu t mt nh thuc RAM ngoi c a ch l

0123H th ta phi lm sao np c gi tr 0123H vo thanh ghi DPTR v sau thc hin lnh truy
xut MOVX (xem gii thch lnh trong Chng 3: Tp lnh ca 8051.).
(DPTR) = 0123H (DPH) = 01H v (DPL) = 23H
V d: Khi ta mun truy xut (c) byte m t mt nh thuc ROM trong c a ch l
0ABCH th ta phi lm sao np c gi tr 0ABCH vo thanh ghi DPTR v sau thc hin lnh truy
xut MOVC (xem gii thch lnh trong Chng 3: Tp lnh ca 8051.).
(DPTR) = 0ABCH (DPH) = 0AH v (DPL) = BCH
1.3.6. Thanh ghi port xut nhp:
Lu :
Trong trng hp phn cng c s dng ROM hoc RAM bn ngoi th ta khng th s
dng Port 0 v Port 2 xut nhp d liu. V khi chip 8051 s s dng hai port ny xc nh a
ch v d liu cho b nh ngoi. Khi , ta ch c th s dng Port 1 v Port 3 xut nhp d liu.
ch mc nh (khi reset) th tt c cc chn ca cc port (P0 P3) c cu hnh l
port xut d liu. Mun cc chn port ca chip 8015 lm port nhp d liu th ta cn phi c lp
trnh li, bng cch ghi mc logic cao (mc 1) n tt c cc bit (cc chn) ca port trc khi bt u
nhp d liu t port.
V d 1: Hot ng xut (ghi) v nhp (c) d liu ti cc chn port (Port 0) ca chip 8051
(xem hnh minh ha bn di).
Hnh pha tri: Minh ha trng thi hot ng ca port khi thc hin lnh xut
(ghi) d liu ra Port 0 ca chip 8051.
Hnh pha phi: Minh ha trng thi hot ng ca port khi thc hin lnh nhp
(c) d liu t Port 0 ca chip 8051.
LED sang
LED tat
CPU - 8051
CAH
WRITE
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Xuat gia tr CAH

(11001010B) t chip
8051 ra Port 0. (P0)=CAH
Gio trnh Vi x l.
+VCC
Nhan SW
Nha SW
10K
PORT 0
0
1
0
1
0
0
1
1
+VCC
10K
PORT 0
39
38
CPU - 8051
37
36
92H
35
READ
34
33
Nhap gia tr t Port 0

vao chip 8051
32
330
0
1
0
0
1
0
0
1
+VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
(P0)=92H
28
V d 2: on chng trnh di y s cu hnh cho Port 0 lm port nhp (c) d liu. Sau
lin tc c d liu t port ny v gi d liu n Port 1 (xem gii thch lnh trong Chng 3:
Tp lnh ca 8051.):
MOV
P0, #0FFH
;Cu hnh P0 lm port nhp bng
;cch ghi 1 vo tt c cc bit.
BACK:
MOV
A, P0
;c d liu t P0.
MOV
P1, A
;Gi d liu ra P1.
SJMP
BACK
;Lp li.
V d 3: on chng trnh di y s thc hin cc thao tc sau (xem gii thch lnh trong
Chng 3: Tp lnh ca 8051.):
Lin tc kim tra bit P1.2 cho n khi bit ny bng 1.
Khi P1.2 =1, hy xut (ghi) gi tr 45H ra P0.
Gi mt xung mc cao ti P1.3.
SETB
P1.2
;Cu hnh P1.2 lm ng vo.
JNB
P1.2, $
;Kim tra lin tc nu P1.2 = 0.
MOV
P0, #45H
; Xut gi tr 45H ra P0.
SETB
P1.3
;a P1.3 ln cao ri a P1.3
CLR
P1.3
;xung thp to xung.
1.3.7. Thanh ghi port ni tip:
(xem thm trong Chng 5: Hot ng ca port ni tip.)
Gio trnh Vi x l.
29
1.3.8. Thanh ghi nh thi:
(xem thm trong Chng 4: Hot ng ca b nh thi.)
Gio trnh Vi x l.
30
1.3.9. Thanh ghi ngt:
(xem thm trong Chng 6: Hot ng ngt.)

1.3.10. Thanh ghi iu khin ngun:
(xem thm trong Chng 5: Hot ng ca port ni tip.)

-
Bit SMOD (Serial Mode) cho php tng gp i tc truyn d liu ni tip (tc
baud) khi SMOD = 1.
Bit GF1, GF0 (General Function) cho php ngi lp trnh dng vi mc ch ring
(d tr cho cc phin bn chip trong tng lai).
Bit PD (Power Down) dng qui nh ch ngun gim.
Bit IDL (Idle) dng qui nh ch ngh.
Gio trnh Vi x l.
31
Lu : H thng phi phc hi Vcc = 5V trc khi thot khi ch ngun gim.
2. B nh ngoi:
-
Chip 8051 cho ta kh nng m rng:

Khng gian b nh chng trnh ln n 64 KB.
Khng gian b nh d liu ln n 64 KB.
Khi s dng b nh ngoi:

Port 0 bus a ch byte thp v bus d liu a hp (AD0-AD7).
Port 2 bus a ch byte cao (A8-A15).
Port 3 cc tn hiu iu khin (WR\, RD\).
S khc nhau gia a hp v khng a hp bus a ch v bus d liu:
nhm lm gim s lng chn a ra ngoi chip gim kch thc ca chip.
Gio trnh Vi x l.
32
2.1. Kt ni v truy xut b nh chng trnh ngoi:
Gio trnh Vi x l.
33
2.2. Kt ni v truy xut b nh d liu ngoi:
Mot chu ky may
Mot chu ky may
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
PSEN\
RD\
PCH
PORT 2
PORT 0
Gio trnh Vi x l.
PCL
Lenh
DPH
DPL
34
Data
2.3. Gii m a ch:

Nu ta trng hp ROM v RAM c kt hp t nhiu b nh c dung lng nh hoc c hai
giao tip vi chip 8051 th ta cn phi gii m a ch. Vic gii m a ch ny cng cn cho hu ht
cc b vi x l (xem thm trong Chng ph lc 1: Gii m a ch.).
V d nu cc ROM v RAM c dung lng 8KB c s dng th tm a ch m chip 8051
qun l (0000H FFFFH) cn phi c gii m thnh tng on 8 KB chip c th chn tng IC
nh trn cc gii hn 8KB tng ng: IC1: 0000H 1FFFH, IC2: 2000H 3FFFH,
IC chuyn dng cho vic to tn hiu gii m l 74HC138, cc ng ra ca IC ny ln lt c
ni vi cc ng vo chn chip CS\ tng ng ca cc IC nh cho php cc IC nh hot ng (ti
mt thi im ch c mt IC nh c php hot ng). Cn lu l do cc ng cho php IC nh
hot ng ring l cho tng loi (PSEN\ cho b nh chng trnh, RD\ v WR\ cho b nh d liu) nn
8051 c th qun l khng gian nh ln n 64KB cho ROM v 64KB cho RAM.
Gio trnh Vi x l.
35
2.4. Cc khng gian nh chng trnh v d liu gi nhau:
Gio trnh Vi x l.
36
V. HOT NG RESET:
Chn RST = 0 Chip 8051 hot ng bnh thng.
Chn RST = 1 Chip 8051 c reset.
Lu :
o
hon tt qu trnh reset th chn RST phi mc cao ti thiu l 2 chu k my v sau
chuyn xung mc thp.
o
Ni dung ca RAM trong chip khng b nh hng bi hot ng reset.
o
Sau khi reset, vic thc thi chng trnh lun lun bt u vi tr u tin trong b nh
chng trnh: a ch 0000H.
o
Trng thi ca cc thanh ghi sau khi reset h thng:
B m chng trnh (PC)
0000H
Thanh ghi A
00H
Thanh ghi B
00H
Thanh ghi PSW
00H
Thanh ghi SP
07H
Thanh ghi DPTR
0000H
Port 0 Port 3
FFH
Thanh ghi IP
xxx00000B
Thanh ghi IE
0xx00000B
Cc thanh ghi nh thi
00H
Thanh ghi SCON
00H
Thanh ghi SBUF
00H
Thanh ghi PCON (HMOS)
0xxxxxxxB
Thanh ghi PCON (CMOS)
0xxx0000B
VI. PHN BI TP:
Bi 1: S dng mt vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra
cc tn hiu chn chip tng ng cc vng a ch sau:
Tn hiu chn
chip
Vng a ch
c tnh truy xut
CS0
0000H - 3FFFH
PSEN
CS1
4000H - 7FFFH
PSEN
CS2
6000H - 7FFFH
RD, WR
CS3
8000H - 87FFH
RD
CS4
8800H - 8FFFH
WR
Gio trnh Vi x l.
37
Bi 2: S dng mt vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra

cc tn hiu chn chip tng ng cc vng a ch sau:
Tn hiu chn
chip
Vng a ch
c tnh truy xut
CS0
9800H - 9BFFH
PSEN
CS1
9800H - 9BFFH
RD, WR
CS2
9C00H - 9DFFH
RD, WR
CS3
9E00H - 9EFFH
RD, WR
Bi 3: Ch dng mt vi mch 74138 (khng dng thm cng), thit k mch gii m a ch to
ra mt tn hiu chn chip /CS tng ng tm a ch F000H-F3FFH.
Gio trnh Vi x l.
38
Chng 3: Tp lnh ca 8051.
CHNG 3
TP LNH CA 8051
I. M U:
Khung dng tng qut ca mt dng lnh:

[LABEL:] MNEMONIC [OPERAND][,OPERAND] [;COMMENT]
o Nhn (Label): biu th a ch ca dng lnh (hoc d liu) theo sau, c dng trong trng ton
hng ca lnh nhy, lnh r nhnh (SJMP AAA; ACALL BBB; CJNE A, #35H,
LOOP; JNB P3.1, TEST_1).
Lu v nhn:
Do ngi lp trnh t t (khng c trng vi t kho, m gi nh, ch dn, ton t
hoc k hiu tin nh ngha).
Bt u bng k t ch, du chm hi (?), du gch di (_).
Di ti a 31 k t.
Kt thc bng du hai chm (:).
o M gi nh (Mnemonic): biu din cc m ca lnh hoc cc ch dn ca chng trnh dch hp
ng (M gi nh: ADD, SUBB, INC, ; Ch dn: ORG, EQU, DB, ).
o Ton hng (Operand): cha a ch hoc d liu m lnh s s dng. S lng ton hng trong mt
dng lnh ph thuc vo tng dng lnh (RET khng ton hng, INC A mt
ton hng, ADD A, R0 hai ton hng, CJNE A, #12H, ABC ba ton hng).
Lu v ton hng: trong cc lnh c 2 ton hng th ton hng u tin cn c gi l
ton hng ch (Destination), ton hng th hai cn c gi l ton hng ngun (Source).
o Ch thch (Comment): lm cho r ngha cho chng trnh. Cc ch thch phi nm trn cng mt
dng v bt u bng du chm phy (;). Cc ch thch nu nm trn nhiu dng
th mi dng cng phi bt u bng du chm phy (;).
Lu : Chi tit v phn ny xem thm ti Chng 7: Lp trnh hp ng trong sch H
vi iu khin Tng Vn On.
Gio trnh Vi x l.
39
II. CC KIU NH A CH (ADDRESSING MODE):
1. nh a ch thanh ghi (Register Addressing):

c dng truy xut d liu trong cc thanh ghi t R0 n R7.
S byte ca lnh: 1 byte.
Cu trc lnh:
V d: ADD A, R5 Lnh cng ni dung thanh ghi A vi ni dung thanh ghi R5. (Gi s:
(A)=05H, (R5)=9AH).
M lnh:
M t lnh:
Ngoi ra, mt s trng hp c bit kiu nh a ch ny cng dng truy xut d liu trong
cc thanh ghi nh: thanh ghi cha A, thanh ghi con tr d liu DPTR, thanh ghi b m chng
trnh PC, c nh C v cp thanh ghi AB.
V d:
INC A

INC DPTR
Lnh tng ni dung thanh ghi A.

Lnh tng ni dung thanh ghi DPTR.
2. nh a ch trc tip (Direct Addressing):

c dng truy xut d liu trong cc nh (00H - FFH) hay trong cc thanh ghi (A, B,
P0P3, DPH, DPL,) ca b nh bn trong chip.
Cu trc lnh:
Gio trnh Vi x l.
40
V d: ADD A, P1 ADD A, 90H Lnh cng ni dung thanh ghi A vi ni dung thanh ghi
port 1 hay nh 90H. (Gi s: (A) = 05H, (P1) = (90H) = 9AH).
M lnh:
M t lnh:
3. nh a ch gin tip (Indirect Addressing):
c dng truy xut d liu trong cc nh gin tip ca b nh bn trong chip. Cc
thanh ghi R0 v R1 c dng cha a ch ca cc nh gin tip (00H - FFH) trong chip.
Lu rng, trc cc thanh ghi R0, R1 cn phi c du @.
Cu trc lnh:
V d: ADD A, @R0 Lnh cng ni dung thanh ghi A vi ni dung nh c a ch cha
trong thanh ghi R0. (Gi s: (A) = 05H, (R0) = 3BH, (3BH) = 9AH).
M lnh:
M t lnh:
4. nh a ch tc thi (Immediate Addressing):
c dng truy xut mt hng s (gi tr bit trc) thay v l mt bin (gi tr khng bit
trc) nh cc kiu nh a ch trn. Lu rng, trc d liu tc thi cn phi c du #.
Ch nh a ch tc thi c th dng np d liu vo mi nh v thanh ghi bt k (i
vi thanh ghi 8 bit: #00H - #0FFH, i vi thanh ghi 16 bit: #0000H - #0FFFFH).
Cu trc lnh:
V d: ADD A, #9AH Lnh cng ni dung thanh ghi A vi gi tr 9AH. (Gi s: (A) = 05H).
M lnh:
M t lnh:
Gio trnh Vi x l.
41
5. nh a ch tng i (Relative Addressing):

c s dng cho cc lnh nhy.
a ch tng i (hay offset) l mt gi tr 8 bit c du.
Tm nhy gii hn l: -128 byte 127 byte t v tr ca lnh tip theo sau lnh nhy.
Cu trc lnh:
V d 1: SJMP AAA Lnh nhy n nhn AAA (Gi s: nhn AAA t trc lnh a ch
0107H, lnh SJMP nm trong b nh ti a ch 0100H v 0101H).
M lnh:
M t lnh: xem hnh 3.5.2.1.
V d 2: SJMP AAA Lnh nhy n nhn AAA (Gi s: nhn AAA t trc lnh a ch
203BH, lnh SJMP nm trong b nh ti a ch 2040H v 2041H).
M lnh:
M t lnh: xem hnh 3.2.5.2.
6. nh a ch tuyt i (Absolute Addressing):

c s dng cho cc lnh ACALL v AJMP.
a ch tuyt i l mt gi tr 11 bit.
Tm nhy gii hn l: trong cng trang 2K hin hnh (trang 2K cha lnh nhy).
Cu trc lnh:
Gio trnh Vi x l.
42
V d: AJMP AAA Lnh nhy n nhn AAA (Gi s: nhn AAA t trc lnh a ch
0F46H, lnh AJMP nm trong b nh ti a ch 0900H v 0901H).
M lnh:
M t lnh:
FFFFH
F800H
F800H
0FFFH
2K trang 31
1800H
17FFH
1000H
0FFFH
0800H
07FFH
0000H
2K trang 2
32 x 2K
(64K)
AAA
0F46H
2K trang 1
0901H
0900H
2K trang 1
46H
E1H
AJMP AAA
2K trang 0
0800H
Ban o nh 64K c chia thanh

32 trang 2K
A15
Cach
thanh lap
a ch cua
nhan se
nhay ti
A11A10
A0
5 bit xac nh
trang 2K
11 bit xac nh a ch trong

1 trang 2K
T 5 bit (A15...A11)
trong thanh ghi PC
T 11 bit (A10...A0) trong

lenh nhay
7. nh a ch di (Long Addressing):
c s dng cho cc lnh LCALL v LJMP.
a ch di l mt gi tr 16 bit.
Tm nhy gii hn l: ton b khng gian nh 64K.
Cu trc lnh:
Gio trnh Vi x l.
43
V d: LJMP AAA Lnh nhy n nhn AAA (Gi s: nhn AAA t trc lnh a ch
A209H, lnh LJMP nm trong b nh ti a ch 0100H, 0101H v 0102H).
M lnh:
FFFFH
AAA
A209H
64K
0102H
0101H
0100H
09H
A2H
12H
LJMP AAA
0000H
M t lnh:
8. nh a ch ch s (Indexed Addressing):
c dng trong cc ng dng cn to cc bng nhy hay cc bng tm kim. Kiu nh a ch
ny dng mt thanh ghi nn (PC hay DPTR) kt hp vi mt offset (A) to thnh dng a
ch hiu dng cho lnh.
Cu trc lnh:
V d: JMP @A+DPTR Lnh nhy gin tip.
Gio trnh Vi x l.
44
III. TP LNH CA 8051 (8051 INSTRUCTION SET):
Mt s k hiu dng trong lnh:

Rn
a ch thanh ghi s dng (R0 R7).
direct
a ch trc tip ca mt byte trong RAM ni (00H-FFH)
@Ri
a ch gin tip s dng (R0 hoc R1).
source
Ton hng ngun (Rn, direct hoc @Ri).
dest
Ton hng ch (Rn, direct hoc @Ri).
#data
Hng s 8 bit (#00H - #0FFH).
#data16
Hng s 16 bit (#0000H - #0FFFFH).
bit
a ch trc tip ca mt bit (a ch bit).
rel
Offset 8 bit c du.
addr11
a ch 11 bit.
addr16
a ch 16 bit.
c thay th bi
()
Ni dung ca
(( ))
Ni dung c cha bi
rrr
Thanh ghi ca dy thanh ghi (000 = R0, 001 = R1, , 111 = R7).
i
a ch gin tip s dng R0 (i = 0) hoc R1 (i = 1).
dddddddd Cc bit d liu.
aaaaaaaa
Cc bit a ch.
eeeeeeee
a ch tng i.
Mt s lu khi lp trnh b vi iu khin 8051:
thng bo l mt gi tr tc thi th cn phi t thm k hiu # vo trc gi tr .
Nu khng c k hiu # th gi tr c hiu l a ch ca nh.
MOV A, #12H
;Np gi tr 12H vo thanh ghi A.
MOV A, 12H
;Sao chp ni dung ca nh c a
;ch 12H vo thanh ghi A.
y ta cng nn lu rng nu thiu k hiu # th lnh trn cng khng gy ra li trong qu
trnh bin dch. V trnh dch hp ng cho l mt lnh hp l. Tuy nhin, kt qu lp trnh s khng
ng nh mun ca ngi lp trnh.
Cc gi tr tc thi nu c thnh phn ch (A, B, C, , F) ng u th cn phi thm s 0 vo
trc thnh phn ch v sau k hiu #. Vic ny bo rng thnh phn ch l mt s HEX ch
khng phi l mt k t.
MOV A, #BH
;Thiu s 0 gy li khi bin dch.
MOV A, #0BH
;Thm s 0 ng.
MOV A, #F9H
;Thiu s 0 gy li khi bin dch.
MOV A, #0F9H
;Thm s 0 ng.
Gio trnh Vi x l.
45
y ta cng nn lu rng vic thiu s 0 thm vo ny s gy li trong qu trnh bin dch

i vi cc chng trnh bin dch c. Ngy nay, mt s phn mm bin dch h tr vic ny. iu
ny c ngha l ta c th thm hay khng thm s 0 vo th u khng nh hng g n qu trnh bin
dch (khng gy ra li khi bin dch).
Trong lnh, cc gi tr tc thi hay a ch ca nh c th c biu din di bt k dng no
BIN (nh phn), DEC (thp phn) hay HEX (thp lc phn).
o a ch nh: cc cu lnh sau y l tng ng nhau:
MOV A, 64H
MOV A, 100
MOV A, 01100100B
o Gi tr tc thi: cc cu lnh sau y l tng ng nhau:
MOV A, #0C9H
;Np gi tr C9H vo thanh ghi A.
MOV A, #201
MOV A, #11001001B
Lu cc hu t i km tng ng cho tng dng: B dng BIN (nh phn), H dng HEX
(thp lc phn), D hoc khng c hu t dng DEC (thp phn).
Chuyn mt gi tr tc thi hay a ch ca nh ln hn kh nng cha ca mt thanh ghi th
s gy ra li (00H-FFH: cho thanh ghi hoc nh 8 bit; 0000H-FFFFH: cho thanh ghi 16 bit DPTR).
MOV A, #123H
;Khng hp l v 123H > FFH.
MOV A, #214
;Hp l v 214 (D6H) < FFH (255).
MOV A, #0F2H
;Hp l v F2H < FFH.
MOV A, 123H
;Khng hp l v 123H > FFH.
MOV A, 200
;Hp l v 200 (C8H) < FFH (255).
MOV DPTR, #123H
;Hp l v 123H < FFFFH (16 bit).
1. Nhm lnh s hc:
1.1. Lnh ADD A, <src-byte>:
Chc nng: Cng (Add).
M t:
ADD cng ni dung ca thanh ghi A (A) vi ni dung ca mt byte c a ch

c ch ra trong lnh (src- byte) v t kt qu vo thanh ghi A. Cc c b nh
hng.
o C CY = 1 nu c s nh t bit 7. Ngc li CY = 0.
o C AC = 1 nu c s nh t bit 3. Ngc li AC = 0.
o C OV = 1 nu c s nh t bit 6 nhng khng c s nh t bit 7 hoc
nu c s nh t bit 7 nhng khng c s nh t bit 6. Ngc li OV = 0.
o Khi cng hai s nguyn khng du v c du:
S khng du: CY = 1 Php ton c nh.
S c du:
CY = 1 S dng = S m + S m.
S m = S dng + S dng.
Gio trnh Vi x l.
46
Cc dng lnh:
ADD A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
00101rrr
(A) (A) + (Rn)
ADD A, direct
S byte
S chu k
M i tng
Hot ng
2
1
00100101
aaaaaaaa
(A) (A) + (direct)
ADD A, @Ri
S byte
S chu k
M i tng
Hot ng
1
1
0010011i
(A) (A) + ((Ri))
ADD A, #data
S byte
S chu k
M i tng
Hot ng
2
1
00100100
dddddddd
(A) (A) + #data
V d: Cho bit trc (A)=C3H, (R0)=47H, (P1)=(90H)=AAH, (47H)=D2H.

Sau khi thc thi lnh ADD A, R0 th:
(A)=0AH, CY=1, AC=0, OV=0
Sau khi thc thi lnh ADD A, 90H hay ADD A, P1 th:
(A)=6DH, CY=1, AC=0, OV=1
Sau khi thc thi lnh ADD A, @R0 th:

(A)=95H, CY=1, AC=0, OV=0
ADD A, @R0
A C3H
R0
Gio trnh Vi x l.
47H
47H D2H
C3H + D2H = 95H
47
A 95H
Sau khi thc thi lnh ADD A, #4EH th:

(A)=11H, CY=1, AC=1, OV=0
1.2. ADDC A, <src-byte>

Chc nng: Cng c c nh (Add with Carry).
M t:
ADDC cng ng thi ni dung ca thanh ghi A (A) vi ni dung ca byte c a

ch c ch ra trong lnh (src-byte) v c nh (CY), t kt qu vo thanh ghi A.
Cc c b nh hng.
o C CY = 1 nu c s nh t bit 7. Ngc li CY = 0.
o C AC = 1 nu c s nh t bit 3. Ngc li AC = 0.
o C OV = 1 nu c s nh t bit 6 nhng khng c s nh t bit 7 hoc
nu c s nh t bit 7 nhng khng c s nh t bit 6. Ngc li OV = 0.
S khng du: CY = 1 Php ton c nh.
S c du:
CY = 1 S dng = S m + S m.
S m = S dng + S dng.
Cc dng lnh:
Gio trnh Vi x l.
ADDC A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
00110rrr
(A) (A) + (C) + (Rn)
ADDC A, direct
S byte
S chu k
M i tng
Hot ng
2
1
00110101
aaaaaaaa
(A) (A) + (C) + (direct)
ADDC A,@Ri
S byte
S chu k
M i tng
Hot ng
1
1
0011011i
(A) (A) + (C) + ((Ri))
ADDC A, #data
S byte
S chu k
M i tng
Hot ng
2
1
00110100
dddddddd
(A) (A) + (C) + # data
48
V d: Cho bit trc (A)=C3H, (R0)=47H, (P1)=(90H)=AAH, (47H)=D2H v c CY=1.

Sau khi thc thi lnh ADDC A, R0 th:
(A)=0BH, CY=1, AC=0, OV=0
A C3H
R0
47H
ADDC A, R0
CY
C3H + 47H + 1H = 0BH
A 0BH
Sau khi thc thi lnh ADDC A, 90H hay ADDC A, P1 th:
(A)=6DH, CY=1, AC=0, OV=1
Sau khi thc thi lnh ADDC A, @R0 th:

(A)=96H, CY=1, AC=0, OV=0
Sau khi thc thi lnh ADDC A, #4EH th:

(A)=11H, CY=1, AC=1, OV=0
A C3H
4EH
ADDC A, #4EH
C3H + 4EH + 1H = 12H
12H
1.3. SUBB A, <src-byte>

Chc nng: Tr c s mn (Subtract with Borrow).
M t:
SUBB tr ni dung ca thanh ghi A (A) vi ni dung ca byte c a ch c ch

ra trong lnh (src-byte) cng vi c nh v ct kt qu vo thanh ghi A. Cc c b
nh hng.
o C CY = 1 nu c s mn cho bit 7. Ngc li CY = 0.
o C AC = 1 nu c s mn cho bit 3. Ngc li AC = 0.
o C OV = 1 nu c s mn cho bit 6 nhng khng c s mn cho bit 7
hoc nu c s mn cho bit 7 nhng khng c s mn cho bit 6. Ngc
li OV = 0.
S khng du: CY = 1 Php ton c mn.
S c du:
CY = 1 S dng = S m - S dng.
S m = S dng - S m.
Gio trnh Vi x l.
49
Cc dng lnh:
SUBB A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
10011rrr
(A) (A) (C) (Rn)
SUBB A, direct
S byte
S chu k
M i tng
Hot ng
2
1
10010101
aaaaaaaa
(A) (A) (C) (direct)
SUBB A, @Ri
S byte
S chu k
M i tng
Hot ng
1001011i
(A) (A) (C) ((Ri))
SUBB A, #data
S byte
S chu k
M i tng
Hot ng
1
1
100110100 dddddddd
(A) (A) (C) #data
1
1
V d: Cho bit trc (A)=83H, (R0)=78H, (P1)=(90H)=AAH, (78H)=C5H v c CY=1.

Sau khi thc thi lnh SUBB A, R0 th:
(A)=0AH, CY=0, AC=1, OV=1
Sau khi thc thi lnh SUBB A, 90H hay SUBB A, P1 th:
(A)=D8H, CY=1, AC=1, OV=0
Sau khi thc thi lnh SUBB A, @R0 th:

(A)=BDH, CY=1, AC=1, OV=0
Gio trnh Vi x l.
50
Sau khi thc thi lnh SUBB A, #D6H th:

(A)=ACH, CY=1, AC=1, OV=0
1.4. INC byte

Chc nng: Tng thm 1 (Increment).
M t:
Tng ni dung ca byte c a ch c ch ra trong lnh (byte) thm 1. Cc c

khng b nh hng.
Lu :
Khi lnh ny c dng thay i gi tr ca mt port xut th gi tr c dng

lm d liu ban u ca port c ly t b cht d liu xut, khng phi c ly
t cc chn nhp.
Cc dng lnh:
INC A
S byte
S chu k
M i tng
Hot ng
1
1
00000100
(A) (A) + 1
INC Rn
S byte
S chu k
M i tng
Hot ng
1
1
00001rrr
(Rn) (Rn) + 1
INC direct
S byte
S chu k
M i tng
Hot ng
2
1
00000101
aaaaaaaa
(direct) (direct) + 1
INC @Ri
S byte
S chu k
M i tng
Hot ng
1
1
0000011i
((Ri)) ((Ri)) + 1
V d: Cho bit trc (A)=C3H, (R0)=69H, (P1)=(90H)=AAH, (69H)=7FH.

Sau khi thc thi lnh INC A th: (A)=C4H
Sau khi thc thi lnh INC 90H hay INC P1 th: (P1)=(90H)=ABH
Gio trnh Vi x l.
51
Sau khi thc thi lnh INC @R0 th: (@R0)=(69H)=80H
Sau khi thc thi lnh INC R0 th: R0=6AH
1.5. INC DPTR

Chc nng: Tng con tr d liu (Increment Data Pointer).
M t:
Tng ni dung ca thanh ghi con tr d liu 16-bit thm 1. Cc c khng b nh

hng.
S byte
S chu k
M i tng
Hot ng
1
2
10100011
(DPTR) (DPTR) + 1
V d 1: Cho bit trc (DPTR)=1234H.

Sau khi thc thi lnh INC DPTR th:
(DPTR)=1235H vi (DPH)=12H v (DPL)=35H
V d 2: Cho bit trc (DPH)=12H v (DPL)=FFH.

Sau khi thc thi lnh INC DPTR th:
(DPTR)=1300H vi (DPH)=13H v (DPL)=00H
Khng c lnh gim ni dung ca DPTR (DEC DPTR). Nu mun gim ni dung
ca DPTR ta phi vit mt on chng trnh con thc hin iu ny. Chng
trnh con c minh ha nh sau:
DEC_DPTR:
;Chng trnh con gim DPTR.
PUSH ACC
;Ct tm gi tr ACC.
DEC DPL
;Gim byte thp ca DPTR.
MOV A, DPL
;So snh byte thp ca DPTR
CJNE A,#0FFH, SKIP
;vi FFH.
DEC DPH
;Gim byte cao ca DPTR.
SKIP:
POP ACC
;Phc hi gi tr ACC.
RET
Lu :
Gio trnh Vi x l.
52
1.6. DEC byte

Chc nng: Gim bt 1 (Decrement).
M t:
Gim ni dung ca byte c a ch c ch ra trong lnh (byte) bt 1. Cc c

khng b nh hng.
Lu :
Khi lnh ny c dng thay i gi tr ca mt port xut th gi tr c dng

lm d liu ban u ca port c ly t b cht d liu xut, khng phi c
ly t cc chn nhp.
Cc dng lnh:
DEC A
S byte
S chu k
M i tng
Hot ng
1
1
00010100
(A) (A) 1
S byte
S chu k
M i tng
Hot ng
1
1
00011rrr
(Rn) (Rn) 1
DEC Rn
DEC direct
S byte
S chu k
M i tng
Hot ng
2
1
00010101
aaaaaaaa
(direct) (direct) 1
DEC @Ri
S byte
S chu k
M i tng
Hot ng
1
1
0001011i
((Ri)) ((Ri)) 1
V d: Cho bit trc (A)=C3H, (R0)=60H, (P1)=(90H)=AAH, (60H)=7AH.

Sau khi thc thi lnh DEC A th: (A)=C2H
Sau khi thc thi lnh DEC 90H hay DEC P1 th: (P1)=(90H)=A9H
Sau khi thc thi lnh DEC @R0 th: (@R0)=(60H)=79H
Gio trnh Vi x l.
53
Sau khi thc thi lnh DEC R0 th: R0=5FH
1.7. MUL AB
Chc nng: Nhn (Multiply).
M t:
MUL AB nhn cc s nguyn khng du 8-bit cha trong thanh ghi A v thanh ghi
B. Tch s l mt gi tr 16 bit, byte thp (8 bit thp) c ct trong thanh ghi A
cn byte cao (8 bit cao) c ct trong thanh ghi B.
Nu tch s ln hn 255 (0FFH) th c trn OV=1. C nh CY lun lun b xa.
S byte
S chu k
M i tng
Hot ng
1
4
10100100
(B) HIGH BYTE OF (A) (B)
(A) LOW BYTE OF (A) (B)
V d 1: Cho bit trc (A)=02H, (B)=7CH.

Sau khi thc thi lnh MUL AB th: (B)= 00H, (A)= F8H, CY=0, OV=0.
V d 2: Cho bit trc (A)=C3H, (B)=AAH.

Sau khi thc thi lnh MUL AB th: (B)= 81H, (A)= 7EH, CY=0, OV=1.
1.8. DIV AB
Chc nng: Chia (Divide).
M t:
DIV AB chia s nguyn khng du 8-bit cha trong thanh ghi A cho s nguyn
khng du 8-bit cha trong thanh ghi B. Thng s c ct trong thanh ghi A
cn s d c ct trong thanh ghi B. C CY v c OV b xo.
Nu ban u B cha 00H, gi tr tr v trong thanh ghi A v thanh ghi B khng
c xc nh v c OV=1. C CY c xa trong mi trng hp.
S byte
S chu k
M i tng
Hot ng
Gio trnh Vi x l.
1
4
10000100
(A) QUOTIENT OF (A) / (B)
(B) REMAINDER OF (A) / (B)
54
V d 1: Cho bit trc (A)=C3H, (B)=0AH.

Sau khi thc thi lnh DIV AB th: (B)= 05H, (A)= 13H, CY=0, OV=0.
V d 2: Cho bit trc (A)=00H, (B)=0AH.

Sau khi thc thi lnh DIV AB th: (B)= 00H, (A)= 00H, CY=0, OV=0.
V d 3: Cho bit trc (A)=C3H, (B)=00H.

Sau khi thc thi lnh DIV AB th: (B)= yyH, (A)= xxH, CY=0, OV=1.
A C3H
B
00H
DIV AB
C3H / 00H = xxH d yyH
yyH
A xxH
1.9. DA A
Chc nng: Hiu chnh thp phn ni dung ca thanh ghi A i vi php cng (Decimal-adjust
Accumulator for Addition)
M t:
DA A hiu chnh gi tr 8-bit trong thanh ghi A (gi tr ny l kt qu php cng

hai ton hng c dng BCD - gi trc ) to ra hai digit 4 bit. Php cng
c thc hin bi lnh ADD hoc ADDC, lnh DA A khng p dng cho
php tr SUBB).
Nu c AC = 1 hoc nu 4 bit thp ca thanh ghi A c gi tr > 9 (xxxx1010
xxxx1111), th 6c cng vi ni dung ca thanh ghi A to ra s BCD 4
bit thp. Sau khi cng, c CY = 1 nu c s nh t 4 bit thp chuyn n tt c 4
bit cao.
Nu c CY = 1 hoc nu 4 bit cao ca thanh ghi A c gi tr > 9 (1010xxxx
1111xxxx), th 6c cng vi 4 bit cao to ra s BCD 4 bit cao. Sau khi
cng c CY = 1 nu c s nh t 4 bit cao nhng c CY khng b xa. Vy th c
CY ch ra rng tng ca 2 ton hng BCD ban u ln hn 99. C OV khng b
nh hng.
Tt c s kin trn ch xy ra trong mt chu k my. Lnh ny thc hin php bin
i thp phn bng cch cng 00H, 06H, 60H hay 66H vi ni dung ca thanh
ghi A ty thuc vo ni dung ban u ca thanh ghi A v cc iu kin ca t
trng thi chng trnh PSW.
Lu :
DA A khng th n gin bin i s hex trong thanh ghi A thnh s dng BCD,
DA A cng khng p dng cho php tr thp phn.
S byte
S chu k
M i tng
Gio trnh Vi x l.
1
1
11010100
55

Hot ng

Gi s ni dung ca thanh ghi A l BCD
IF [[(A3 A0) > 9] OR [(AC) = 1]]
THEN (A3 A0) (A3 A0) + 6
AND
IF [[(A7 A4) > 9] OR [(C) = 1]]
THEN (A7 A4) (A7 A4) + 6
V d 1: Cho bit trc (A)=56H biu din BCD ca s 56

(R3)=67H biu din BCD ca s 67
ADD A, R3
DA
A
th: c CY=1 v (A)=23 biu din BCD ca s 123 (56+67)
Sau khi thc thi chui lnh:

ADD A, R3
DA A

ADD A, R3
DA A
Gio trnh Vi x l.
56

c CY=1
ADDC A, R3
DA
A
th: c CY=1 v (A)=24 biu din BCD ca s 124 (56+67+1)
Lu :
Cc gi tr BCD c th c tng thm 1 n v hoc gim i 1 n v bng cch

cng vi 01H (khi tng) hoc cng vi 99H (khi gim).
o V d 1: Gi s cho (A)=39H biu din BCD ca s 39.

ADD A, #01H
DA A
th: c CY=0 v (A)=40H biu din BCD ca s 40.
o V d 2: Gi s cho (A)=30H biu din BCD ca s 30.

ADD A, #99H
DA A
th: c CY=1 v (A)=29H biu din BCD ca s 29.
2. Nhm lnh logic:

Bng trng thi ca cc php ton logic
AND OR XOR CPL
A
A AND B
A OR B
A XOR B
CPL A
2.1. ANL <dest-byte>, <src-byte>

Chc nng: AND hai ton hng (Logical-AND).
M t:
ANL thc hin php ton AND tng bit gia hai ton hng c ch ra trong lnh
v lu kt qu vo ton hng ch (dest-byte). Cc c khng b nh hng.
Lu :
Khi lnh ny c dng sa i mt port xut, gi tr c dng lm d liu

ban u ca port c c t b cht d liu xut, khng phi t cc chn port.
Gio trnh Vi x l.
57
Cc dng lnh:
ANL A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
01011rrr
(A) (A) AND (Rn)
ANL A, direct
S byte
S chu k
M i tng
Hot ng
2
1
01010101 aaaaaaaa
(A) (A) AND (direct)
ANL A, @Ri
S byte
S chu k
M i tng
Hot ng
1
1
0101011i
(A) (A) AND ((Ri))
ANL A, #data
S byte
S chu k
M i tng
Hot ng
2
1
01010100
dddddddd
(A) (A) AND #data
ANL direct, A
S byte
S chu k
M i tng
Hot ng
2
1
01010010
aaaaaaaa
(direct) (direct) AND (A)
ANL direct, #data

S byte
S chu k
M i tng
Hot ng
3
2
01010011 aaaaaaaa dddddddd
(direct) (direct) AND #data
V d: Cho bit trc (A)=C3H, (R0)=2AH, (P3)=(B0H)=75H, (2AH)=55H.

Sau khi thc thi lnh ANL A, R0 th: (A)=02H
A C3H
R0 2AH
ANL A, R0
C3H AND 2AH = 02H

AND
A 02H
11000011B
00101010B
00000010B
Gio trnh Vi x l.
58
Sau khi thc thi lnh ANL A, B0H hay ANL A, P3 th: (A)=41H
Sau khi thc thi lnh ANL A, @R0 th: (A)=41H
Sau khi thc thi lnh ANL A, #2AH th: (A)=02H
Sau khi thc thi lnh ANL B0H, A hay ANL P3, A th: (P3)=41H
Sau khi thc thi lnh ANL 2AH, #B0H th: (2AH)=10H
Gio trnh Vi x l.
59
2.2. ORL <dest-byte>, <src-byte>

Chc nng: OR logic hai ton hng (Logical-OR).
M t:
ORL thc hin php ton OR tng bit gia hai ton hng c ch ra trong lnh v
lu kt qu vo ton hng ch (dest-byte). Cc c khng b nh hng.
Lu :

Cc dng lnh:
ORL A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
01001rrr
(A) (A) OR (Rn)
ORL A, direct
S byte
S chu k
M i tng
Hot ng
2
1
01000101
aaaaaaaa
(A) (A) OR (direct)
ORL A, @Ri
S byte
S chu k
M i tng
Hot ng
1
1
0100011i
(A) (A) OR ((Ri))
ORL A, #data
S byte
S chu k
M i tng
Hot ng
2
1
01000100
dddddddd
(A) (A) OR #data
ORL direct, A
S byte
S chu k
M i tng
Hot ng
2
1
01000010
aaaaaaaa
(direct) (direct) OR (A)
ORL direct, #data

S byte
S chu k
M i tng
Hot ng
3
2
(direct) (direct) OR #data
Gio trnh Vi x l.
60
V d: Cho bit trc (A)=C3H, (R0)=2AH, (P3)=(B0)=75H, (2AH)=55H.

Sau khi thc thi lnh ORL A, R0 th: (A)=EBH
Sau khi thc thi lnh ORL A, B0H hay ORL A, P3 th: (A)=F7H
Sau khi thc thi lnh ORL A, @R0 th: (A)=D7H
Sau khi thc thi lnh ORL A, #2AH th: (A)=EBH
A C3H
2AH
ORL A, #2AH
C3H OR 2AH = EBH

OR
A EBH
11000011B
00101010B
11101011B
Sau khi thc thi lnh ORL B0H, A hay ORL P3, A th: (P3)=F7H
Gio trnh Vi x l.
61
Sau khi thc thi lnh ORL 2AH, #B0H th: (2AH)=F5H
2AH 55H
B0H
ORL 2AH, #B0H
55H OR B0H = F5H

OR
2AH F5H
01010101B
10110000B
11110101B
2.3. XRL <dest-byte>, <src-byte>

Chc nng: XOR logic hai ton hng (Logical Exclusive-OR).
M t:
XRL thc hin php ton XOR tng bit gia hai ton hng c ch ra trong lnh
v lu kt qu vo ton hng ch (dest-byte). Cc c khng b nh hng.
Lu :

Cc dng lnh:
XRL A, Rn
S byte
S chu k
M i tng
Hot ng
XRL A, direct
S byte
S chu k
M i tng
Hot ng
1
1
01101rrr
(A) (A) (Rn)
2
1
01100101 aaaaaaaa
(A) (A) (direct)
XRL A, @Ri
S byte
S chu k
M i tng
Hot ng
1
0110011i
(A) (A) ((Ri))
XRL A, #data
S byte
S chu k
M i tng
Hot ng
2
1
01100100
dddddddd
(A) (A) #data
XRL direct, A
S byte
S chu k
M i tng
Hot ng
2
1
01100010
aaaaaaaa
(direct) (direct) (A)
Gio trnh Vi x l.
62

XRL direct, #data
S byte
S chu k
M i tng
Hot ng

3
2
(direct) (direct) #data
V d: Cho bit trc (A)=C3H, (R0)=2AH, (P3)=(B0)=75H, (2AH)=55H.

Sau khi thc thi lnh XRL A, R0 th: (A)=E9H
Sau khi thc thi lnh XRL A, B0H hay XRL A, P3 th: (A)=B6H
Sau khi thc thi lnh XRL A, @R0 th: (A)=96H
Sau khi thc thi lnh XRL A, #2AH th: (A)=E9H
Sau khi thc thi lnh XRL B0H, A hay XRL P3, A th: (P3)=B6H
Gio trnh Vi x l.
63
Sau khi thc thi lnh XRL 2AH, #B0H th: (2AH)=E5H
XRL 2AH, #B0H
2AH 55H
55H XOR B0H = E5H
B0H
XOR
2AH E5H
01010101B
10110000B
11100101B
2.4. CLR A
Chc nng: Xa thanh ghi A (Clear Acc).
M t:
Thanh ghi A b xa (tt c cc bit u bng 0). Cc c khng b nh hng.
Cc dng lnh:
S byte
S chu k
M i tng
Hot ng
1
1
11100100
(A) 0
V d: Cho bit trc (A)=5CH.

Sau khi thc thi lnh CLR A th: (A)=00H
2.5. CPL A
Chc nng: Ly b ni dung thanh ghi A (Complement Acc).
M t:
Mi mt bit ca thanh ghi A c ly b logic (b 1: cc bit 1 c th i thnh

bit 0 v cc bit 0 c th i thnh bit 1). Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
1
11110100
(A) NOT(A)
V d: Cho bit trc (A)=5CH.

Sau khi thc thi lnh CPL A th: (A)=A3H
A 5CH
CPL A
A A3H
01011100B
10100011B
Gio trnh Vi x l.
64
2.6. RL A
Chc nng: Quay tri thanh ghi A (Rotate Acc Left).
M t:
8 bit trong thanh ghi A c quay tri 1 bit. Bit 7 c quay n v tr ca bit 0.
Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
1
00100011
(An+1) (An), n = 0 6
(A0) A7
V d: Cho bit trc (A)=C5H.

Sau khi thc thi lnh RL A th: (A)=8BH
2.7. RLC A
Chc nng: Quay tri thanh ghi A cng vi c nh.
M t:
8 bit trong thanh ghi A v c nh cng c quay tri 1 bit. Bit 7 c di chuyn
n c CY v trng thi ban u ca c CY c a n v tr ca bit 0. Cc c
khc khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
1
00110011
(An+1) (An), n = 0 6
(A0) (C), (C) A7
V d: Cho bit trc (A)=C5H v c CY=0.

Sau khi thc thi lnh RLC A th: (A)=8AH v c CY=1
Gio trnh Vi x l.
65
2.8. RR A
Chc nng: Quay phi thanh ghi A (Rotate Acc Right).
M t:
8 bit trong thanh ghi A c quay phi 1 bit. Bit 0 c quay n v tr ca bit 7.
Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
1
00000011
(An) (An+1), n = 0 6
(A7) A0

Sau khi thc thi lnh RR A th: (A)=E2H
2.9. RRC A
Chc nng: Quay phi thanh ghi A cng vi c nh.
M t:
8 bit trong thanh ghi A v c nh cng c quay phi 1 bit. Bit 0 c di chuyn
n c nh v trng thi ban u ca c nh c a n v tr ca bit 7. Cc c
khc khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
1
00010011
(An) (An+1), n = 0 6
(A7) (C)
(B) A0
V d: Cho bit trc (A)=C5H v c CY=0.

Sau khi thc thi lnh RRC A th: (A)=62H v c CY=1
Gio trnh Vi x l.
66
2.10. SWAP A
Chc nng: Tro i ni dung hai na thp v cao ca thanh ghi A (Swap nibble).
SWAP A tro i ni dung hai na thp v cao ca thanh ghi A (cc bit t 3 n 0
cc bit t 7 n 4). Thao tc ny cn c th c hiu nh l quay thanh ghi A
i 4 bit. Cc c khng b nh hng.
M t:
1
1
11000100
(A3 A0) (A7 A4)
S byte
S chu k
M i tng
Hot ng
Sau khi thc thi lnh SWAP A th: (A)=5CH
Lnh ny c th c dng chuyn i gi tr nh phn trong thanh ghi A (gi

tr ny nh hn 100) thnh s BCD nh sau:
Lu :
MOV
DIV
SWAP
ADD
B, #10
AB
A
A, B
;Chia gi tr cho 10 tch ra

;(A)=digit chc (B)=digit n v.
;a digit chc ln na cao ca ACC.
;Thm digit n v vo na thp.
3. Nhm lnh di chuyn d liu:

3.1. MOV <dest-byte>, <src-byte>
Chc nng: Di chuyn ni dung ca ton hng ngun (src-byte) n ton hng ch (destbyte).
Ni dung ca byte c ch ra bi ton hng th hai c sao chp vo v tr c
xc nh bi ton hng th nht. Byte ngun khng b nh hng. Cc thanh ghi
khc v cc c khng b nh hng.
M t:
Cc dng lnh:
MOV A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
11101rrr
(A) (Rn)
MOV A, direct
S byte
S chu k
M i tng
Hot ng
2
1
11100101 aaaaaaaa
(A) (direct)
Lu :
Gio trnh Vi x l.
MOV A, ACC l lnh khng hp l.

67
MOV A, @Ri
S byte
S chu k
M i tng
Hot ng
1
1
1110011i
(A) ((Ri))
MOV A, #data
S byte
S chu k
M i tng
Hot ng
2
1
01110100 dddddddd
(A) #data
MOV Rn, A
S byte
S chu k
M i tng
Hot ng
1
1
11111rrr
(Rn) (A)
MOV Rn, direct

S byte
S chu k
M i tng
Hot ng
2
2
10101rrr
(Rn) (direct)
MOV Rn, #data

S byte
S chu k
M i tng
Hot ng
2
1
01111rrr
(Rn) #data
MOV direct, A
S byte
S chu k
M i tng
Hot ng
2
1
11110101
aaaaaaaa
(direct) (A)
MOV direct, Rn
S byte
S chu k
M i tng
Hot ng
2
2
10001rrr
(direct) (Rn)
MOV direct, direct

S byte
S chu k
M i tng
Hot ng
3
2
10000101 aaaaaaaa aaaaaaaa
(direct) (direct)
aaaaaaaa
dddddddd
aaaaaaaa
Lu : byte 2 cha a ch ngun, byte 3 cha a ch ch.
Gio trnh Vi x l.
68
MOV direct, @Ri

S byte
S chu k
M i tng
Hot ng
2
2
1000011i
(direct) ((Ri))
MOV direct, #data

S byte
S chu k
M i tng
Hot ng
3
2
(direct) #data
MOV @Ri, A
S byte
S chu k
M i tng
Hot ng
1
1
1111011i
((Ri)) (A)
MOV @Ri, direct

S byte
S chu k
M i tng
Hot ng
2
2
1010011i aaaaaaaa
((Ri)) (direct)
MOV @Ri, #data

S byte
S chu k
M i tng
Hot ng
2
1
0111011i dddddddd
((Ri)) #data
aaaaaaaa
V d: Cho bit trc (A)=5FH, (R0)=30H, (30H)=40H, (P1)=CAH.

Sau khi thc thi lnh MOV A, R0 th: (A)=30H, (R0)=30H
Sau khi thc thi lnh MOV A, 30H th: (A)=40H, (30H)=40H
Sau khi thc thi lnh MOV A, @R0 th: (A)=40H, (R0)=30H, (30H)=40H
Gio trnh Vi x l.
69
Sau khi thc thi lnh MOV A, #30H th: (A)=30H
Sau khi thc thi lnh MOV R0, A th: (A)=5FH, (R0)=5FH
Sau khi thc thi lnh MOV R0, P1 th: (R0)=CAH, (P1)=CAH
Sau khi thc thi lnh MOV R0, #90H th: (R0)=90H
Sau khi thc thi lnh MOV P1, A th: (A)=5FH, (P1)=5FH
Sau khi thc thi lnh MOV P1, R0 th: (R0)=30H, (P1)=30H
Sau khi thc thi lnh MOV P1, 30H th: (30H)=40H, (P1)=40H
Sau khi thc thi lnh MOV P1, @R0 th: (R0)=30H, (30H)=40H, (P1)=40H
Gio trnh Vi x l.
70
Sau khi thc thi lnh MOV 30H, #30H th: (30H)=30H
Sau khi thc thi lnh MOV @R0, A th: (A)=5FH, (30H)=5FH, (R0)=30H
Sau khi thc thi lnh MOV @R0, P1: (30H)=CAH, (P1)=CAH, (R0)=30H
Sau khi thc thi lnh MOV @R0, #90H th: (30H)=90H, (R0)=30H
3.2. MOVC A, @A+ <base-reg>

Chc nng: Di chuyn byte m hoc byte hng s.
MOVC np cho thanh ghi A byte m hoc byte hng s t b nh chng trnh.
a ch ca byte c tm np l tng ca gi tr 8 bit khng du ban u cha
trong thanh ghi A vi ni dung ca thanh ghi nn 16 bit (thanh ghi nn c th l
con tr d liu hoc PC). Trong trng hp sau, thanh ghi PC c tng ch
n a ch ca lnh tip theo trc khi c cng vi ni dung ca thanh ghi A,
cc thanh ghi nn khng b thay i. Php cng bit th 16 do s nh t 8 bit thp
c th truyn qua cc bit cao. Cc c khng b nh hng.
M t:
Cc dng lnh:
MOVC A, @A+DPTR
S byte
S chu k
M i tng
Hot ng
1
2
10010011
(A) ((A)+(DPTR))
MOVC A, @A+PC
S byte
S chu k
M i tng
Hot ng
1
2
10000011
(A) ((A)+(PC))
Gio trnh Vi x l.
71
V d 1: Cho bit trc (A)=7BH, (PC)=345H, (DPTR)=1234H. nh ROM ni

(3C0H)=AAH. nh ROM ngoi (12AFH)=BBH.
Sau khi thc thi lnh MOVC A, @A+PC th: (A)=AAH
Sau khi thc thi lnh MOVC A, @A+DPTR th: (A)=BBH
V d 2: Cho chui lnh sau:

MOVC
A, @A+PC
;(@A+PC)=([A]+[PC])
SJMP
$
; di lnh l 2 byte.
DULIEU:
DB
66H,77H,88H
DB
99H,0AAH
DB
0BBH
Sau khi thc thi chui lnh th:

(A) = 66H nu trc khi thc thi lnh ta c (A) = 02H.




(A) = AAH nu trc khi thc thi lnh ta c (A) = 06H.

(A) = BBH nu trc khi thc thi lnh ta c (A) = 07H.
MOV
DPTR, #CODEDISP
MOVC
A, @A+DPTR
;(@A+DPTR)=([A]+[DPTR])
SJMP
$
; di lnh l 2 byte.
CODEDISP:
DB
48H,5AH,6BH,0A9H,0F5H,90H
Sau khi thc thi chui lnh th:


(A) = 5AH nu trc khi thc thi lnh ta c (A) = 01H.

(A) = 6BH nu trc khi thc thi lnh ta c (A) = 02H.

(A) = A9H nu trc khi thc thi lnh ta c (A) = 03H.

(A) = F5H nu trc khi thc thi lnh ta c (A) = 04H.

Gio trnh Vi x l.
72
3.3. MOVX <dest-byte>, <src-byte>

Chc nng: Di chuyn b nh ngoi (Move External).
MOVX chuyn d liu gia thanh ghi A vi ni dung ca mt byte trong b nh
d liu ngoi (ta dng k hiu X ni tip vi MOV). Cc lnh ny c chia lm 2
loi, hai loi ny khc nhau ch chng cung cp a ch gin tip 8 bit hay 16
bit cho b nh d liu ngoi c dung lng 256 byte hay 64 KB.
Vi loi th nht, s dng thanh ghi R0 hoc R1 lu gi a ch ca d liu
cn truy xut thuc RAM ngoi. Loi ny dng trong trng hp b nh RAM c
dung lng nh (ti a l 256 byte). Port 1 & Port 2 l port xut/nhp d liu.
Vi loi th hai, s dng thanh ghi DPTR lu gi a ch ca d liu cn truy
xut thuc RAM ngoi. Loi ny dng trong trng hp b nh RAM c dung
lng ln (ti a l 64 KB). Port 1 l port xut/nhp d liu.
Trong nhiu tnh hung ta c th trn hai loi trn ca lnh MOVX. Mt dy
RAM ln vi cc ng a ch cao c iu khin bi P2 c th c nh a
ch thng qua con tr d liu hoc vi m xut ra cc bit a ch cao n P2
c tip theo bi mt lnh MOVX s dng R0 hoc R1.
M t:
Cc dng lnh:
MOVX A, @Ri
S byte
S chu k
M i tng
Hot ng
1
2
11100011i
(A) ((Ri))
MOVX A, @DPTR
S byte
S chu k
M i tng
Hot ng
1
2
11100000
(A) ((DPTR))
MOVX @Ri, A
S byte
S chu k
M i tng
Hot ng
1
2
11110011
((Ri)) (A)
MOVX @DPTR, A
S byte
S chu k
M i tng
Hot ng
1
2
11110000
((DPTR)) (A)
Gio trnh Vi x l.
73
V d: Cho bit trc (A)=AAH, (DPTR)=1234H, (R0)=34H. nh RAM ngoi 256 byte:
(34H)=12H & 64 KB: (1234H)=7FH
Sau khi thc thi lnh MOVX A, @R0 th: (A)=12H
Sau khi thc thi lnh MOVX @R0, A th: nh RAM ngoi (34H)=AAH
Sau khi thc thi lnh MOVX A, @DPTR th: (A)=7FH
Sau khi thc thi lnh MOVX @DPTR, A th: (1234H)=AAH
Gio trnh Vi x l.
74
3.4 MOV DPTR, #data16

Chc nng: Np hng s 16-bit cho con tr d liu DPTR.
M t:
Con tr d liu c np bi hng s 16-bit ch ra trong lnh. Hng s 16-bit c

t byte 2 v byte 3 ca lnh. Byte 2 l byte cao c np cho DPH cn byte 3
l byte thp c np cho DPL. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
3
2
10010000 dddddddd dddddddd
(DPTR) #data16
V d:
Sau khi thc thi lnh MOV DPTR, #1234H th:
3.5. PUSH direct

Chc nng: Ct vo ngn xp (stack).
M t:
Con tr stack c tng bi 1. Ni dung ca ton hng c ch ra trong lnh sau

c sao chp vo RAM ni ti a ch c tr n bi con tr stack. Cc c
khng b nh hng.
S byte
S chu k
M i tng
Hot ng
2
2
11000000
aaaaaaaa
(SP) (SP) + 1
((SP)) (direct)
V d: Ct tm thi ni dung ca thanh ghi A, B v R0 vo ngn xp. Cho bit trc (A)=AAH,
(B)=BBH, (R0)=CCH, (SP)=5FH.
PUSH A
PUSH B
PUSH 00H
Th: (SP)=62H, (60H)=AAH, (61H)=BBH, (62H)=CCH
Gio trnh Vi x l.
75
3.6. POP direct

Chc nng: Ly ra t ngn xp (stack).
M t:
Ni dung ca vng RAM ni c nh a ch bi con tr stack SP c c v

ni dung con tr stack c gim bi 1. Gi tr c c sau c chuyn n
byte c nh a ch trc tip ch ra
trong lnh. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
2
2
11010000
aaaaaaaa
(direct) ((SP))
(SP) (SP) 1
V d: Ly li ni dung ca thanh ghi A, B v R0 ct vo ngn xp lc u (v d trn).

POP 00H
POP B
POP A
Th: (SP)=5FH, (R0)=CCH, (B)=BBH, (A)=AAH
Gio trnh Vi x l.
76
3.7. XCH A, <byte>

Chc nng: Tro i ni dung ca thanh ghi A vi ni dung ca mt byte
XCH np cho thanh ghi A ni dung ca byte ch ra trong lnh, ng thi ghi ni
dung ban u ca thanh ghi A cho byte va nu trn. Ton hng ngun ng thi
l ton hng ch v ngc li.
M t:
Cc dng lnh:
XCH A, Rn
S byte
S chu k
M i tng
Hot ng
1
1
11001rrr
(A) (Rn)
XCH A, direct
S byte
S chu k
M i tng
Hot ng
2
1
11000101
aaaaaaaa
(A) (direct)
XCH A, @Ri
S byte
S chu k
M i tng
Hot ng
1
1
1100011i
(A) ((Ri))
V d: Cho bit trc (A)=3FH, (R0)=20H, (20H)=75H.

Sau khi thc thi lnh XCH A, R0 th: (A)=20H, (R0)=3FH
Sau khi thc thi lnh XCH A, 20H th: (A)=75H, (20H)=3FH
Sau khi thc thi lnh XCH A, @R0 th: (A)=75H, (20H)=3FH, (R0)=20H
Gio trnh Vi x l.
77
3.8. XCHD A, @Ri

Chc nng: Tro i digit (Exchange Digit).
XCHD tro i ni dung na thp ca thanh ghi A (biu din mt digit s hex
hoc BCD) vi ni dung na thp ca mt byte trong RAM ni, byte ny c
nh a ch gin tip bi thanh ghi ch ra trong lnh. Na cao ca cc thanh ghi
va nu trn khng b nh hng v cc c cng khng b nh hng.
M t:
S byte
S chu k
M i tng
Hot ng
1
1
110101i
(A3 A0) (Ri3 Ri0)
V d: Cho bit trc (A)=36H, (R0)=20H, (20H)=75H.

Sau khi thc thi lnh XCHD A, @R0 th: (A)=35H, (20H)=76H
4. Nhm lnh x l bit:

4.1. CLR bit
Chc nng: Xa bit.
Bit c ch ra trong lnh c xa. Cc c khng b nh hng. CLR c th thao
tc trn c nh v trn mt bit bt k c nh a ch bit.
M t:
Cc dng lnh:
CLR C
S byte
S chu k
M i tng
Hot ng
1
1
11000011
(C) 0
CLR bit
S byte
S chu k
M i tng
Hot ng
2
1
11000010
(bit) 0
bbbbbbbb
V d: Cho bit trc c CY=1, (P1)=FFH.

Sau khi thc thi lnh CLR C th: c CY=0
Gio trnh Vi x l.
78
Sau khi thc thi lnh CLR P1.3 th: P1.3=0 tc lm (P1)=F7H
4.2. CPL bit

Chc nng: Ly b bit (Complex).
M t:
Bit c ch ra trong lnh c ly b. Mt bit c gi tr 1 c i thnh 0 v

ngc li. Cc c khng b nh hng. CPL c th thao tc trn c nh v trn
mt bit bt k c nh a ch bit.
Lu :
Khi lnh ny c dng lm thay i gi tr ca mt chn xut (bt k chn

no ca mt port) th gi tr c dng lm d liu ban u ca chn c ly t
b cht d liu xut, khng phi c ly t chn nhp.
Cc dng lnh:
CPL C
S byte
S chu k
M i tng
Hot ng
1
1
10110011
(C) NOT(C)
CPL bit
S byte
S chu k
M i tng
Hot ng
2
1
10110010
bbbbbbbb
(bit) NOT(bit)
V d: Cho bit trc c CY=1, (P1)=FFH.

Sau khi thc thi lnh CPL C th: c CY=0
Sau khi thc thi lnh CPL P1.3 th: P1.3=0 tc lm (P1)=F7H
Gio trnh Vi x l.
79
4.3. SETB <bit>

Chc nng: Set bit bng 1 (Set Bit).
SETB set bit c ch ra trong lnh bng 1. SETB c th thao tc trn c nh hoc
cc bit bt k c nh a ch bit. Cc c khng b nh hng.
M t:
Cc dng lnh:
SETB C
S byte
S chu k
M i tng
Hot ng
1
1
11010011
(C) 1
SETB bit
S byte
S chu k
M i tng
Hot ng
2
1
11010010
(bit) 1
bbbbbbbb
V d: Cho bit trc c CY=0, (P1)=00H.

Sau khi thc thi lnh SETB C th: c CY=1
Sau khi thc thi lnh SETB P1.3 th: P1.3=1 tc lm (P1)=08H
4.4. ANL C, <src-bit>

Chc nng: AND logic hai bit.
Nu gi tr ca bit ngun l 0 th lnh ny s xa CY v ngc li nu gi tr ca
bit ngun l 1 th lnh ny gi nguyn gi tr hin hnh ca c CY. Du gch cho
(/) t trc ton hng trong chng trnh hp ng ch ra rng bit ngun c ly
b trc khi AND vi CY nhng gi tr ca bit ngun khng b thay i bi
thao tc ly b ny. Cc c khng b nh hng.
M t:
Cc dng lnh:
ANL C, bit
S byte
S chu k
M i tng
Hot ng
2
2
10000010
bbbbbbbb
(C) (C) AND (bit)
ANL C, /bit
S byte
S chu k
M i tng
2
2
10110000
Gio trnh Vi x l.
80
bbbbbbbb

Hot ng

(C) (C) AND NOT(bit)
V d: Cho bit trc (A)=72H, c CY=1.

Sau khi thc thi lnh ANL C, ACC.7 th: c CY=0, (A)=72H
Sau khi thc thi lnh ANL C, /ACC.7 th: c CY=1, (A)=72H
4.5. ORL C, <src-bit>

Chc nng: OR logic hai bit.
Nu gi tr ca bit ngun l 1 th php ton s set c CY=1 v ngc li nu gi tr
ca bit ngun l 0 th php ton gi nguyn gi tr hin hnh ca c CY. Du gch
cho / t trc ton hng trong chng trnh hp ng ch ra rng bit ngun c
ly b trc khi OR logic vi c nh nhng gi tr ca bit ngun khng b thay
i bi thao tc ly b. Cc c khng b nh hng.
M t:
Cc dng lnh:
ORL C, bit
S byte
S chu k
M i tng
Hot ng
2
2
01110010
bbbbbbbb
(C) (C) OR (bit)
ORL C, /bit
S byte
S chu k
M i tng
Hot ng
2
2
10100000
bbbbbbbb
(C) (C) OR NOT(bit)
V d: Cho bit trc(A)=72H, c CY=0.

Sau khi thc thi lnh ORL C, ACC.7 th: c CY=0, (A)=72H
Gio trnh Vi x l.
81
Sau khi thc thi lnh ORL C, /ACC.7 th: c CY=1, (A)=72H
Lu :
Cc lnh trn bao gm lnh ANL v ORL nhng khng tn ti lnh XRL. Cho nn
nu ta cn XOR hai bit , BIT1 v BIT2, v kt qu c ct vo trong c nh (CY)
th ta s dng on lnh sau y:
MOV
C, BIT1
;Np BIT1 vo c nh.
JNB
BIT2, SKIP
;BIT2=0 th C = BIT1.
CPL
C
;BIT2=1 th C\ = BIT1\.
SKIP:
;BIT1 XOR BIT2
4.6. MOV <dest-bit>, <src-bit>

Chc nng: Di chuyn bit ngun (src-bit) n bit ch (dest-bit).
Ni dung ca bit c ch ra bi ton hng th hai c sao chp vo v tr c
xc nh bi ton hng th nht. Mt trong hai ton hng phi l c nh v ton
hng cn li c th l bit bt k c nh a ch bit. Bit ngun khng b nh
hng. Cc thanh ghi khc v cc c khng b nh hng.
M t:
Cc dng lnh:
MOV C, bit
S byte
S chu k
M i tng
Hot ng
2
1
10100010
bbbbbbbb
(C) (bit)
MOV bit, C
S byte
S chu k
M i tng
Hot ng
2
2
10010010
bbbbbbbb
(bit) (C)
V d: Cho bit trc c CY=1, (P1)=C5H.

Sau khi thc thi lnh MOV C, P1.3 th: c CY=0, (P1)=C5H
Gio trnh Vi x l.
82
Sau khi thc thi lnh MOV P1.3, C th: c CY=1, (P1)=CDH
4.7. JB bit, rel

Chc nng: Nhy nu bit bng 1.
M t:
Nu bit ch ra trong lnh bng 1 th nhy n a ch c ch ra trong lnh cn

ngc li th tip tc vi lnh tip theo. Cc c khng b nh hng, bit c kim
tra s khng b thay i.
S byte
S chu k
M i tng
Hot ng
3
2
00100000 bbbbbbbb eeeeeeee
(PC) (PC) + 3
IF (bit) = 1 THEN
(PC) (PC) + byte_2
Lu :
Lu :
Tm nhy ca lnh JB bit, rel b gii hn khong cch nhy t -128 byte (nhy
lui) n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu kin
ny.
V d 1: Cho bit trc (A)=56H, (P1)=CAH.

JB P1.2, AAA
JB ACC.2, BBB
th chng trnh c tip tc vi lnh ti nhn BBB, (P1)=CAH v (A)=56H.
V d 2: Cho chui lnh:
MOV
A, #0FFH
MOV
P0, #9CH
; 9CH = 10011100B
JB
P0.7, AAA
MOV
A, #00H
AAA:
Sau khi thc thi chui lnh th (A)=FFH, (P0)=9CH (chng trnh thc hin lnh nhy JB P0.7, AAA).
Gio trnh Vi x l.
83

MOV
A, #0FFH
MOV
P0, #9CH
; 9CH = 10011100B
JB
P0.5, AAA
MOV
A, #00H
AAA:
Sau khi thc thi chui lnh th (A)=00H, (P0)=9CH (chng trnh khng thc hin lnh nhy JB P0.5,
AAA).
4.8. JNB bit, rel
Chc nng: Nhy nu bit bng 0.
M t:
Nu bit ch ra trong lnh bng 0 th nhy n a ch c ch ra trong lnh cn

ngc li th tip tc vi lnh tip theo. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
3
2
(PC) (PC) + 3
IF (bit) = 0 THEN
(PC) (PC) + byte_2
Lu :
Lu :
Tm nhy ca lnh JNB bit, rel b gii hn khong cch nhy t -128 byte
(nhy lui) n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu
kin ny.
V d 1: Cho bit trc (A)=56H, (P1)=CAH.

JNB P1.3, AAA
JNB ACC.3, BBB
th chng trnh c tip tc vi lnh ti nhn BBB, (A)=56H v (P1)=CAH.
Gio trnh Vi x l.
84

MOV
P1, #10H
MOV
A, #6BH
; 6BH = 01101011B
JNB
ACC.5, AAA
MOV
P1, #01H
AAA:
Sau khi thc thi chui lnh th (A)=6BH, (P1)=01H (chng trnh khng thc hin lnh nhy JNB
ACC.5, AAA).
MOV
P1, #10H
MOV
E0H, #6BH
; 6BH = 01101011B
JNB
E2H, AAA
MOV
P1, #01H
AAA:
Sau khi thc thi chui lnh th (A)=(E0H)=6BH, (P1)=10H (chng trnh thc hin lnh nhy JNB
E2H, AAA).
4.9. JBC bit, rel
Chc nng: Nhy nu bit bng 1 v xa bit (lm cho bit = 0).
M t:
Nu bit c ch ra trong lnh bng 1 th xa bit ny v r nhnh n a ch cho

trong lnh cn ngc li th tip tc vi lnh tip theo. Bit s khng c xa nu
bit ny l 0. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
3
2
(PC) (PC) + 3
IF (bit) = 1 THEN
(bit) 0
(PC) (PC) + byte_2
Lu :
Gio trnh Vi x l.
85

Lu :
Tm nhy ca lnh JBC bit, rel b gii hn khong cch nhy t -128 byte
(nhy lui) n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu
kin ny.
Khi lnh ny c dng lm thay i gi tr ca mt port xut th gi tr c
dng lm d liu ban u ca port c ly t b cht d liu xut, khng phi
c ly t cc chn nhp.
V d 1: Cho bit trc (A)=56H.

JBC ACC.3, AAA
JBC ACC.2, BBB
th chng trnh c tip tc vi lnh ti nhn BBB v (A)=52H.
MOV
A, #76H
MOV
P3, #9CH
; 9CH = 10011100B
JBC
P3.2, AAA
MOV
A, #67H
AAA:
Sau khi thc thi chui lnh th (A)=76H, (P3)=98H (chng trnh thc hin lnh nhy JBC P3.2,
AAA).
MOV
A, #76H
MOV
B0H, #9CH
; 9CH = 10011100B
JBC
B1H, AAA
MOV
A, #67H
AAA:
Sau khi thc thi chui lnh th (A)=67H, (P3)=(B0H)=9CH (chng trnh khng thc hin lnh nhy
JBC B1H, AAA).
4.10. JC rel
Chc nng: Nhy nu c CY = 1.
M t:
Nu c CY = 1 th nhy n a ch cho trong lnh cn ngc li th tip tc vi

lnh tip theo. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
Gio trnh Vi x l.
2
2
01000000
eeeeeeee
(PC) (PC) + 2
IF (C) = 1 THEN
(PC) (PC) + byte_2
86
Lu :
Lu :
Tm nhy ca lnh JC rel b gii hn khong cch nhy t -128 byte (nhy lui)
n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu kin ny.
V d 1: Cho bit trc (A)=7FH, c CY=0.

JC AAA
ADD A,#0F7H
JC
BBB
th chng trnh c tip tc vi lnh ti nhn BBB, (A)=76H, c CY=1.
MOV
A, #9AH
MOV
R0, #76H
ADD
A, R0
JC
AAA
MOV
R0, #67H
AAA:
Sau khi thc thi chui lnh th (A)=10H, (R0)=76H v c CY=1 (chng trnh thc hin lnh nhy JC
AAA).
4.11. JNC rel
Chc nng: Nhy nu c CY = 0.
M t:
Nu c CY = 0 th nhy n a ch cho trong lnh cn ngc li th tip tc vi

lnh tip theo. Cc c khng b nh hng.
S byte
S chu k
M i tng
Hot ng
Gio trnh Vi x l.
2
2
01010000
eeeeeeee
(PC) (PC) + 2
IF (C) = 0 THEN
(PC) (PC) + byte_2
87
Lu :
Lu :
Tm nhy ca lnh JNC rel b gii hn khong cch nhy t -128 byte (nhy
lui) n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu
kin
ny.
V d 1: Cho bit trc (A)=7FH, c CY=1.

JNC AAA
ADD A,#26H
JNC BBB
th chng trnh c tip tc vi lnh ti nhn BBB, (A)=A5H, c CY=0.
MOV
A, #0B9H
MOV
R1, #52H
ADD
A, R1
JNC
AAA
MOV
R1, #25H
AAA:
Sau khi thc thi chui lnh th (A)=0BH, (R1)=25H v c CY=1 (chng trnh khng thc hin lnh
nhy JNC AAA).
Gio trnh Vi x l.
88
5. Nhm lnh r nhnh:

5.1. ACALL addr11
Chc nng: Gi n a ch tuyt i (Absolute Call)
M t:
ACALL gi khng iu kin mt chng trnh con t ti a ch c ch ra

trong lnh (xem thm gii thch v chng trnh con phn 5.3). Ch rng,
chng trnh con c gi phi c bt u trong cng khi 2K ca b nh
chng trnh vi byte u tin ca lnh theo sau lnh ACALL. Cc c khng
b nh hng.
S byte
S chu k
M i tng
Hot ng
2
2
aaa1001
aaaaaaaa
Lu : aaa = A10A8 v aaaaaaaa = A7A0

(PC) (PC) + 2
(SP) (SP) + 1
((SP)) (PC7PC0)
(SP) (SP) + 1
((SP)) (PC15PC8)
(PC10PC0) a ch trang
M t:
Gio trnh Vi x l.
89
Lu : Do khng gian b nh chng trnh ti a l 64KB cho nn ta c 32 trang (khi) v mi

trang bt u a ch l bin ca 2KB (nh l: 0000H, 0800H, 1000H, 1800H, , F800H).
FFFFH
F800H
F800H
1800H
17FFH
1000H
0FFFH
0800H
07FFH
0000H
1000H
0FFFH
2K trang 31
2K trang 2
32 x 2K
(64K)
2K trang 1
Trang 2
A
2K trang 1
2K trang 0
Ban o nh 64K c chia thanh

32 trang 2K
0800H
07FFH
Trang 0
V d 1: Cho bit trc (SP)=07H, lnh ACALL v tr 0123H v nhn AAA v tr 0345H ca
b nh chng trnh. Lnh k tip lnh ACALL v tr 0125H.
Sau khi thc thi lnh ACALL AAA th: (SP)=09H, (PC)=0345H v 2 nh ca RAM ni
(08H)=23H, (09H)=01H.
V d 2: Cho bit trc (SP)=07H, lnh ACALL v tr 0800H v nhn AAA v tr 0700H ca
b nh chng trnh.
Khng th thc thi lnh ACALL AAA (li lp trnh) v lnh ACALL v nhn AAA khng nm
trong cng mt trang (lnh ACALL thuc trang 1, nhn AAA thuc trang 0).
Gio trnh Vi x l.
90
5.2. LCALL addr16

Chc nng: Gi mt chng trnh con (Long Call).
M t:
LCALL gi mt chng trnh con vi a ch bt u chng trnh con c ch ra

trong lnh (xem thm gii thch v chng trnh con phn 5.3). Ch rng,
chng trnh con c th bt u bt c ni no trong khng gian b nh
chng trnh 64KB. Cc c khng b nh hng.
3
2
S byte
S chu k
M i tng
byte 2 cha cc bit a ch t A15 A8

byte 3 cha cc bit a ch t A7 A0.
Hot ng
(PC) (PC) + 3
(SP) (SP) + 1
(SP) (PC7 PC0)
(SP) (SP) + 1
(SP) (PC15 PC8)
(PC) addr15 addr0
Lu :
M t:
LCALL AAA
64 KB
AAA:
2
RET
V d: Cho bit trc (SP)=07H, lnh LCALL v tr 0123H v nhn AAA v tr 1234H ca
b nh chng trnh. Lnh k tip lnh ACALL v tr 0126H.
Sau khi thc thi lnh LCALL AAA th: (SP)=09H, (PC)=1234H v 2 nh ca RAM ni
(08H)=26H, (09H)=01H.
Gio trnh Vi x l.
91
5.3. RET
Chc nng: Tr v t chng trnh con (Return).
M t:
RET ly li cc byte cao v byte thp ca PC t stack, gim con tr stack bi 2.

Vic thc thi chng trnh tip tc vi lnh a ch cha trong PC, trong trng
hp tng qut l lnh ngay sau lnh ACALL hoc LCALL. Cc c khng b nh
hng.
S byte
S chu k
M i tng
Hot ng
1
2
00100010
(PC15 PC8) ((SP))
(SP) (SP) 1
(PC7 PC0) ((SP))
(SP) (SP) 1
Lu :
Chng trnh con c mt s qui nh sau:
o L mt chui gm nhiu lnh c kt hp li vi nhau thc hin mt cng vic no
.
o Bt u bng mt NHN, do ngi lp trnh t t ra (nhn ny chnh l tn ca chng
trnh con).
o Kt thc bng lnh RET.
o c t cui chng trnh, pha trn ch dn kt thc chng trnh END.
o Gia chng trnh con v chng trnh chnh phi c cch ly bng lnh:
SJMP $.
SJMP MAIN (MAIN: l nhn bt k thuc chng trnh chnh).
o Chng trnh con c th c gi ra nhiu ln ti bt k thi im no, ty thuc vo
ngi lp trnh yu cu (thng qua cc lnh gi ACALL, LCALL v cc tn hiu ngt).
o Trong mt chng trnh c th c mt hoc nhiu chng trnh con.
Gio trnh Vi x l.
92
V d 1: Da vo V d 1 ca phn 5.1. Cho bit trc (SP)=09H; nh RAM ni (08H)=25H

v (09H)=01H .
Sau khi thc thi lnh RET th: (SP)=07H v chng trnh c tip tc vi lnh ti a ch 0125H
(v tr ca lnh k tip lnh ACALL).
V d 2: Da vo V d ca phn 5.2. Cho bit trc (SP)=09H; nh RAM ni (08H)=26H v
(09H)=01H .
Sau khi thc thi lnh RET th: (SP)=07H v chng trnh c tip tc vi lnh ti a ch 0126H
(v tr ca lnh k tip lnh LCALL).
5.4. RETI
Chc nng: Tr v t chng trnh con phc v ngt.
M t:
RETI ly li cc byte cao v byte thp ca PC t stack, phc hi logic ngt c

th nhn cc ngt khc c cng u tin ngt vi ngt va x l. Con tr stack
c gim bi 2. Khng c thanh ghi no khc b nh hng; PSW khng c t
ng phc hi tr li trng thi trc khi x l ngt. Vic thc thi chng trnh
tip tc vi lnh a ch cha trong PC, trong trng hp tng qut l lnh
ngay sau im m yu cu ngt c pht hin. Nu c mt ngt c u tin ngt
thp hn hoc cng u tin ngt c treo khi lnh RETI c thc thi, mt lnh
c thc thi trc khi ngt ang treo c x l.
S byte
S chu k
M i tng
Hot ng
Lu :
1
2
00110010
(PC15 PC8) ((SP))
(SP) (SP) 1
(PC7 PC0) ((SP))
(SP) (SP) 1
Lnh RETI tr iu khin v chng trnh gi t mt ISR (ISR: Interrupt Service

Routine: chng trnh con phc v ngt). im khc nhau gia RETI v RET l
RETI c bo hiu cho h thng iu khin ngt rng qu trnh x l ngt xong.
Nu trng hp khng c mt ngt no c duy tr trong thi gian RETI thc thi
th lnh RETI s hot ng nh lnh RET.
V d: Cho bit trc (SP)=0BH; nh RAM ni (0AH)=23H v (0BH)=01H. mt tn hiu ngt

c pht hin trong lnh a ch 0123H ang thc thi.
Sau khi thc thi lnh RETI th: (SP)=09H v chng trnh c tip tc vi lnh ti a ch 0123H.
Gio trnh Vi x l.
93
5.5. AJMP addr11

Chc nng: Nhy n a ch tuyt i (Absolute Jump).
M t:
AJMP chuyn vic thc thi chng trnh n a ch c ch ra trong lnh. Ch

rng, ch nhy n phi trong cng khi 2K ca b nh chng trnh vi
byte u tin ca lnh theo sau lnh AJMP.
S byte
S chu k
M i tng
2
2
aaa00001
aaaaaaaa
Ghi ch: aaa = A10 A8 v aaaaaaaa = A7 A0

Hot ng
(PC) (PC) + 2
(PC10 PC0) a ch trang
M t:
V d: Cho bit trc lnh AJMP v tr 0345H v nhn AAA v tr 0123H ca b nh chng
trnh.
Sau khi thc thi lnh AJMP AAA th: (PC)=0123H.
Gio trnh Vi x l.
94
5.6. LJMP addr16

Chc nng: Nhy di (Long Jump).
M t:
LJMP to ra mt r nhnh khng iu kin n a ch c ch ra trong lnh. Ch

rng, a ch ch c th bt c ni no trong khng gian a ch ca b
nh chng trnh 64KB. Cc c khng b nh hng.
S byte
S chu k
M i tng
Lu :
Hot ng
3
2
byte 2 cha cc bit a ch t A15A8
byte 3 cha cc bit a ch t A7A0
(PC) addr15 addr0
M t:
V d: Cho bit trc lnh LJMP v tr 0123H v nhn AAA v tr 1234H ca b nh chng
trnh.
Sau khi thc thi lnh LJMP AAA th: (PC)=1234H.
Gio trnh Vi x l.
95
5.7. SJMP rel

Chc nng: Nhy ngn (Short Jump).
M t:
iu khin chng trnh r nhnh khng iu kin n a ch c ch ra trong

lnh. Ch rng, tm nhy cho php l 128 byte trc lnh v 127 byte sau
lnh.
S byte
S chu k
M i tng
Hot ng
2
2
10000000
eeeeeeee
(PC) (PC) + 2
(PC) (PC) + byte_2
M t:
Lu :
Lnh SJMP $ l mt lnh vng lp v tn (lnh nhy ti ch), thng c s

dng khi cn kt thc mt chng trnh iu khin ca chip 8051 (lu rng cc
tn hiu ngt vn hot ng bnh thng, v th y chnh l phng php duy
nht thot khi vng lp v tn ny).
V d: Cho bit trc lnh SJMP nm ti a ch 0100H v nhn AAA nm ti a ch 0123H

trong b nh chng trnh.
Sau khi thc thi lnh SJMP AAA th: (PC)=0123H.
Gio trnh Vi x l.
96
5.8. JMP @A+DPTR

Chc nng: Nhy gin tip.
M t:
Cng gi tr 8-bit khng du cha trong thanh ghi A vi con tr 16-bit v np kt

qu tng cho b m chng trnh PC. y chnh l a ch ca lnh k tip c
tm np. C hai, thanh ghi A v con tr d liu u khng b thay i. Cc c
khng b nh hng.
S byte
S chu k
M i tng
Hot ng
1
2
01110011
(PC) (PC) + (A) + (DPTR)
V d: Cho bit trc (A)=00H, 02H, 04H, 06H.

MOV DPTR, #JMP_TBL
JMP @A+DPTR
JMP_TBL:
th:
AJMP AAA ; di lnh l 2 byte.

AJMP BBB
; di lnh l 2 byte.
AJMP CCC ; di lnh l 2 byte.
AJMP DDD ; di lnh l 2 byte.
nu (A)=00H, chng trnh c tip tc vi lnh ti nhn AAA.
nu (A)=02H, chng trnh c tip tc vi lnh ti nhn BBB.
nu (A)=04H, chng trnh c tip tc vi lnh ti nhn CCC.
nu (A)=06H, chng trnh c tip tc vi lnh ti nhn DDD.
5.9. JZ rel
Chc nng: Nhy nu ni dung thanh ghi A bng 0.
M t:
Nu tt c cc bit ca thanh ghi A u bng 0 th nhy n a ch cho trong lnh

cn ngc li tip tc vi lnh tip theo. Cc c khng b nh hng. Ni dung
thanh ghi A khng b thay i.
S byte
S chu k
M i tng
Hot ng
2
2
01100000
eeeeeeee
(PC) (PC) + 2
IF (A) = 0 THEN
(PC) (PC) + byte_2
Lu :
Gio trnh Vi x l.
97

Lu :
Tm nhy ca lnh JZ rel b gii hn khong cch nhy t -128 byte (nhy lui)
n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu kin ny.
V d: Cho bit trc (A)=01H.

JZ AAA
DEC A
JZ
BBB
th chng trnh c tip tc vi lnh ti nhn BBB.
5.10. JNZ rel
Chc nng: Nhy nu ni dung thanh ghi A khc 0.
M t:
Nu thanh ghi A c mt bit bt k bng 1 th nhy n a ch cho trong lnh cn

ngc li tip tc vi lnh tip theo. Cc c khng b nh hng. Ni dung thanh
ghi A khng b thay i.
S byte
S chu k
M i tng
Hot ng
2
2
01110000
eeeeeeee
(PC) (PC) + 2
IF (A) < > 0 THEN
(PC) (PC) + byte_2
Lu :
Lu :
Tm nhy ca lnh JNZ rel b gii hn khong cch nhy t -128 byte (nhy
lui) n +127 byte (nhy ti) k t lnh k tip theo sau lnh nhy c iu kin
ny.
V d: Cho bit trc (A)=00H.

JNZ AAA
INC A
JNZ BBB
th chng trnh c tip tc vi lnh ti nhn BBB.
Gio trnh Vi x l.
98
5.11. CJNE <dest-byte>, <src-byte>, rel

Chc nng: So snh v nhy nu khng bng.
CJNE so snh gi tr ca 2 ton hng (src-byte) v (dest-byte) ri r nhnh n a
ch c ch ra trong lnh nu cc gi tr ca 2 ton hng ny khng bng nhau.
C CY = 1 nu gi tr nguyn khng du ca (dest- byte) nh hn gi tr nguyn
khng du ca (src-byte) v ngc li CY = 0. Khng c ton hng no trong 2
ton hng b nh hng.
M t:
Cc dng lnh:
CJNE A, direct, rel
S byte
S chu k
M i tng
Hot ng
CJNE A, #data, rel

S byte
S chu k
M i tng
Hot ng
CJNE Rn, #data, rel

S byte
S chu k
M i tng
Hot ng
Gio trnh Vi x l.
3
2
10110101 aaaaaaaa eeeeeeee
(PC) (PC) + 3
IF (A) < > (direct) THEN
(PC) (PC) + a ch tng i
IF (A) < (direct) THEN
(C) 1
ELSE
(C) 0
3
2
10110100 dddddddd eeeeeeee
(PC) (PC) + 3
IF (A) < > #data THEN
IF (A) < #data THEN
(C) 1
ELSE
(C) 0
3
2
10111rrr dddddddd eeeeeeee
(PC) (PC) + 3
IF (Rn) < > #data THEN
IF (Rn) < #data THEN
(C) 1
ELSE
(C) 0
99

CJNE @Ri, #data, rel
S byte
S chu k
M i tng
Hot ng

3
2
1011011i dddddddd eeeeeeee
(PC) (PC) + 3
IF ((Ri)) < > #data THEN
IF ((Ri)) < #data THEN
(C) 1
ELSE
(C) 0
Lu :
V d 1: Cho bit trc (A)=34H, (01H)=(R1)=34H, (34H)=B9H.

CJNE A, 01H, AAA
CJNE @R1, #9BH, BBB
th chng trnh c tip tc vi lnh ti nhn BBB v c C=0.
CLR
C
MOV
A, #40H
MOV
40H, #0B1H
CJNE
A, 40H, AAA
MOV
40H, #1BH
AAA:
ADDC
A, 40H
Sau khi thc thi chui lnh th (A)=F2H, (40H)=B1H, CY=0.
Gio trnh Vi x l.
100
V d 3: ng dng cho php so snh ln hn hay nh hn. Gi s:

o Khi ta mun nhy n nhn BIG nu (A) #20H, th cc lnh sau c s dng:
CJNE
A, #20H, $+3
;So snh (A) vi con s 20H.
JNC
BIG
;Nhy n BIG nu (A) #20H.
o Khi ta mun nhy n nhn SMALL nu (A) < #20H, th cc lnh sau c s dng:
CJNE
A, #20H, $+3
;So snh (A) vi con s 20H.
JC
SMALL
;Nhy n SMALL nu (A) < #20H.
Lu : K hiu $ l mt k hiu ca trnh dch hp ng, biu th a ch ca lnh hin hnh (v

CJNE c di lnh l 3 byte nn $+3 s l a ch ca lnh tip theo CJNE, tc l lnh
JC/JNC).
5.12. DJNZ <byte>, <rel-addr>
Chc nng: Gim v nhy nu byte khc 0.
DJNZ gim byte ch ra bi ton hng u trong lnh v r nhnh n a ch c
ch ra bi ton hng th hai trong lnh nu kt qu sau khi gim khc 0. Nu gi
tr ban u ca byte l 00H ta s c trn sang 0FFH. Cc c khng b nh hng.
M t:
Cc dng lnh:
DJNZ Rn, rel
S byte
S chu k
M i tng
Hot ng
DJNZ direct, rel

S byte
S chu k
M i tng
Hot ng
Lu :
Gio trnh Vi x l.
2
2
11011rrr
eeeeeeee
(PC) (PC) + 2
(Rn) (Rn) 1
IF (Rn) < > 0 THEN
(PC) (PC) + byte_2
3
2
11010101 aaaaaaaa eeeeeeee
(PC) (PC) + 2
(direct) (direct) 1
IF (direct) < > 0 THEN
(PC) (PC) + byte_2
Khi lnh ny c dng lm thay i gi tr ca mt port xut th gi tr c

dng lm d liu ban u ca port c ly t b cht d liu xut, khng phi
c ly t cc chn nhp.
101
Lu :
Lu :
Khi lnh DJNZ c thc hin th gi tr trong thanh ghi Rn c gim (-1) trc
khi em ra so snh vi gi tr 0.

MOV A, #50
MOV R2, #8
AAA: ADD A, #1
DJNZ R2, AAA
Sau khi thc thi chui lnh th (A)=58, (R2)=0.
MOV A, #50
MOV R3, #56
AAA: ADD A, #1
DJNZ R3, AAA
MOV A, #50
MOV R1, #0
AAA: ADD A, #1
DJNZ R1, AAA
Lu rng: Qua ba v d v lnh DJNZ trn cho ta mt nhn xt nh sau:
o Nu (Rn)=8 Lnh ADD c thc hin 8 ln.
5.13. NOP
Chc nng: Khng lm g (No Operation).
M t:
Vic thc thi chng trnh tip tc vi lnh tip theo. Khng c thanh ghi hay c
no b nh hng.
S byte
S chu k
M i tng
Hot ng
Gio trnh Vi x l.
1
1
00000000
(PC) (PC) + 1
102
Danh sch cc lnh lm nh hng ti cc c CY, AC v OV
Ghi ch:
X l c tng ng b nh hng.
0 l c tng ng bng 0.
1 l c tng ng bng 1.
IV. CC V D NG DNG V TP LNH:

V d 1: Vit on lnh xa thanh ghi A v sau cng 9 vo thanh ghi A 10 ln. Sau khi
hon tt th ct gi tr trong thanh ghi A vo thanh ghi R7.
Gii
MOV
A, #0
;Xo ACC, A = 0.
MOV
R0, #10
;Np s ln lp, R0 = 10.
BACK:
ADD
A, #9
;Cng thm 9 vo ACC.
DJNZ
R0, BACK
;Kim tra s ln lp li, 10 ln.
MOV
R7, A
;Ct ACC vo thanh ghi R7.
V d 2: Vit on lnh np vo thanh ghi A vi gi tr FFH v sau ly b thanh ghi A 500
ln.
Gii
MOV
A, #0FFH
;Np A = FFH.
MOV
R0, #10
;Np s ln lp 1, R0 = 10.
LOOP:
MOV
R1, #50
;Np s ln lp 2, R1 = 50.
BACK:
CPL
A
;Ly b ACC.
DJNZ
R1, BACK
;Kim tra s ln lp 2 (vng trong), 50 ln.
DJNZ
R0, LOOP
;Kim tra s ln lp 1(vng ngoi), 10 ln.
Gio trnh Vi x l.
103
V d 3: Vit on lnh xc nh xem R0 c cha gi tr 0 hay khng? Nu khng th np vo

R0 gi tr FFH.
Gii
MOV
A, R0
;Chuyn ni dung R5 vo A.
JNZ
NEXT
;Nhy n NEXT nu A ? 0 (thot ra).
MOV
R0, #0FFH
;Np R0 = FFH nu A = 0.
NEXT:
V d 4: Vit on lnh tm tng ca 79H, F5H v E2H. Ghi byte thp ca tng vo R0 v
byte cao ca tng vo R1.
Gii
MOV
A, #0
;Xo ACC, A = 0.
MOV
R1, #0
;Xo R1, R1 = 0.
ADD
A, #79H
;Cng thm 79H (A = 79H, CY = 0).
JNC
NO_CY1
;Nhy nu CY = 0.
INC
R1
;Nu CY = 1 th tng R1.
NO_CY1:
ADD
A, #0F5H
;Cng thm F5H (A = 6EH, CY =1).
JNC
NO_CY2
;Nhy nu CY = 0.
INC
R1
NO_CY2:
ADD
A, #0E2H
;Cng thm E2H (A = 50H, CY = 1).
JNC
NO_CY3
;Nhy nu CY = 0.
INC
R1
NO_CY3:
MOV
R0, A
;R0 = 50H (byte thp), R1 = 02H (byte cao).
V d 5: H thng s dng 8051 c tn s dao ng ca thch anh l 11,0592MHz. Hy xc nh
thi gian cn thit thc hin cc lnh sau:
MOV R3, #55H
DEC R3
DJNZ R2, AAA
LJMP AAA
SJMP AAA
NOP
MUL AB
Gii
Chu k my:
12
12
TMachine =
=
= 1,085(s )
f OSC 11,0592MHz
Lnh:
MOV R3, #55H
DEC R3
DJNZ R2, AAA
LJMP AAA
SJMP AAA
NOP
MUL AB
Gio trnh Vi x l.
S chu k my:
1
1
2
2
2
1
4
104
Thi gian thc hin:

t = 1 x 1,085 (s) = 1,085 (s)
t = 1 x 1,085 (s) = 1,085 (s)
t = 2 x 1,085 (s) = 2,17 (s)
t = 2 x 1,085 (s) = 2,17 (s)
t = 2 x 1,085 (s) = 2,17 (s)
t = 1 x 1,085 (s) = 1,085 (s)
t = 4 x 1,085 (s) = 4,34 (s)

thi gian cn thit thc hin hon tt on lnh sau:
MOV A, #55H
MOV P1, A
CPL A
END
Gii
Chu k my:
12
12
TMachine =
=
= 1,085(s )
f OSC 11,0592MHz
S chu k my:
on lnh:
MOV
A, #55H
1
MOV
P1, A
1
CPL
A
1
END
Tng thi gian thc hin on lnh trn l:
t = (1 + 1 + 1) x 1,085 (s) = 3,255 (s)
thi gian cn thit thc hin hon tt on lnh sau:
DELAY:
MOV R3, #200
DJNZ R3, $
RET
Gii
Chu k my:
12
12
TMachine =
=
= 1,085(s )
f OSC 11,0592MHz
on lnh:
S chu k my:
DELAY:
MOV R3, #200
1
DJNZ R3, $
2
RET
1
t = [1 + (2 x 200) + 1] x 1,085 (s) = 436,17 (s)
Gio trnh Vi x l.
105
V d 8: H thng s dng 8051 c tn s dao ng ca thch anh l 11,0592 MHz. Hy xc

nh thi gian cn thit thc hin hon tt on lnh sau:
Gii
Chu k my:
TMachine =
on lnh:
12
12
=
= 1,085(s )
f OSC 11,0592MHz
S chu k my:
DELAY:
MOV R3, #250
1
HERE:
NOP
1
NOP
1
NOP
1
NOP
1
DJNZ R3, HERE
2
RET
1
t = [1 + ((1 + 1 + 1 + 1 + 2) x 250) + 1] x 1,085 (s) = 1629,67 (s)
V d 9: Vit on lnh c?t gi tr ca thanh ghi R5, R6 v A vo ngn xp. Sau ly ra v
cho ln lt vo cc thanh ghi R2, R3 v B tng ng.
Gii
PUSH
05H
;Ct R5 vo ngn xp.
PUSH
06H
;Ct R6 vo ngn xp.
PUSH
0E0H
;Ct ACC vo ngn xp.
POP
0F0H
;Ly t ngn xp cho vo B, (B) = (A).
POP
03H
;Ly t ngn xp cho vo R3, (R3) = (R6).
POP
02H
;Ly t ngn xp cho vo R2, (R2) = (R5).
V d 10: Vit on lnh chuyn gi tr trong nh c a ch 55H vo cc nh RAM ti
a ch t 40H 44H, s dng:
o Ch nh a ch trc tip.
o Ch nh a ch gin tip (khng dng vng lp).
o Ch nh a ch gin tip (dng vng lp).
Gii
Ch nh a ch trc tip:
MOV
A, #55H
MOV
40H, A
MOV
41H, A
MOV
42H, A
MOV
43H, A
MOV
44H, A
Gio trnh Vi x l.

;Sao ni dung ca A vo nh 40H.
106
Ch nh a ch gin tip (khng dng vng lp):

MOV
A, #55H
MOV
R0, #40H
;Np a ch bt u, R0 = 40H.
MOV
@R0, A
;Sao ni dung A vo nh do R0 tr n.
INC
R0
;Tng con tr, R0 = 41H.
MOV
@R0, A
INC
R0
MOV
@R0, A
INC
R0
MOV
@R0, A
INC
R0
MOV
@R0, A
Ch nh a ch gin tip (dng vng lp):
MOV
A, #55H
MOV
R0, #40H
MOV
R1, #5
;Np s ln lp li, R1 = 5.
LOOP:
MOV
@R0, A
INC
R0
;Tng con tr.
DJNZ
R1, LOOP
;Kim tra s ln lp cho n khi s ln = 0.
V d 11: Vit on lnh xa 16 nh RAM ni c a ch bt u t 60H.
Gii
CLR
A
;Xo ACC, A = 0.
MOV
R0, #60H
MOV
R1, #16
LOOP:
MOV
@R0, A
INC
R0
;Tng con tr.
DJNZ
R1, LOOP
V d 12: Vit on lnh chuyn mt khi d liu gm 10 byte t v tr nh RAM ni bt
u ti a ch 35H n cc v tr nh RAM ni bt u ti a ch 60H.
Gii
MOV
R0, #35H
;Np a ch bt u (ngun), R0 = 35H.
MOV
R1, #60H
;Np a ch bt u (ch), R1 = 60H.
MOV
R2, #10
LOOP:
MOV
A, @R0
;Sao ni dung nh do R0 tr n vo A.
MOV
@R1, A
INC
R0
;Tng con tr (ngun).
INC
R1
;Tng con tr (ch).
DJNZ
R2, LOOP
Gio trnh Vi x l.
107
V d 13: Gi s ch DHCN c lu trong ROM ni ti vng nh c a ch bt u l

200H. Hy phn tch cch chng trnh sau y hot ng v xc nh xem ch DHCN s c lu
vo u sau khi chng trnh hon tt?
ORG
0000H
;a ch lu chng trnh trong ROM.
MOV
DPTR, #200H
;Np con tr vng d liu, DPTR=200H.
CLR
A
;Xo ACC, A = 0.
MOVC
A, @A+DPTR
;Ly d liu ti nh ROM do
;(A+DPTR) = 200H tr n a vo A.
MOV
R0, A
;Ct d liu vo R0.
INC
DPTR
;Tng con tr, DPTR=201H.
CLR
A
;Xo ACC, A = 0.
MOVC
A, @A+DPTR
MOV
R1, A
;Ct d liu vo R1.
INC
DPTR
CLR
A
;Xo ACC, A = 0.
MOVC
A, @A+DPTR
MOV
R2, A
;Ct d liu vo R2.
INC
DPTR
CLR
A
;Xo ACC, A = 0.
MOVC
A, @A+DPTR
MOV
R3, A
;Ct d liu vo R3.
SJMP
$
;Dng chng trnh.
ORG
200H
MYDATA:
DB
DHCN
;Khai bo d liu.
END
;Kt thc chng trnh.
Gii
Theo chng trnh trn, cc nh ca b nh chng trnh (ROM) c a ch 200H - 203H cha
cc ni dung sau: (200H) = 44H = D, (201H) = 48H = H, (202H) = 43H = C, (203H) = 4EH =
N.
u tin vi (DPTR) = 200H v (A) = 0. Lnh MOVC A, @A+DPTR chuyn ni dung ca nh
c a ch 200H (A + DPTR = 0 + 200H) trong ROM vo A. Thanh ghi A lc ny s cha gi tr 44H l
m ASCII ca k t D. K t ny c ct vo thanh ghi R0.
Tip theo, DPTR c tng ln (DPTR = 201H) v A c xo (A = 0) ly ni dung ca v tr
nh k tip trong ROM c a ch l 201H (A + DPTR = 0 + 200H) vo A. Thanh ghi A lc ny s cha
gi tr 48H l m ASCII ca k t H. K t ny c ct vo thanh ghi R1.
Qu trnh din ra tng t nh vy, sau khi hon tt chng trnh ta c (R0) = 44H, (R1) = 48H,
(R2) = 43H, (R3) = 4EH l m ASCII ca cc k t D, H, C v N.
Gio trnh Vi x l.
108
V d 14: Gi s ch TP.HCM c lu trong ROM ni ti vng nh c a ch bt u l

200H. Hy vit chng trnh chuyn cc byte d liu ny vo cc nh RAM ni bt u t a ch
40H.
Gii
Phng php s dng b m d liu:
ORG
0000H
MOV
DPTR, #MYDATA ;Np con tr vng d liu.
MOV
R0, #40H
;Np a ch bt u cha trong RAM.
MOV
R1, #6
;Np gi tr b m (s lng k t).
LOOP:
CLR
A
;Xo ACC, A = 0
MOVC
A, @A+DPTR
;(A+DPTR) tr n a vo A.
MOV
@R0, A
;Ct vo nh RAM do R0 tr n.
INC
DPTR
;Tng con tr d liu.
INC
R0
;Tng a ch vng RAM.
DJNZ
R1, LOOP
;Lp li cho n khi b m = 0.
SJMP
$
;Dng chng trnh.
ORG
200H
MYDATA:
DB
TP.HCM
;Khai bo d liu.
END
;Kt thc chng trnh.
Phng php s dng k t NULL kt thc chui:
ORG
0000H
MOV
MOV
R0, #40H
LOOP:
CLR
A
;Xo ACC, A = 0
MOVC
A, @A+DPTR
JZ
EXIT
;Thot ra nu c k t NULL.
MOV
@R0, A
;Ct vo nh RAM do R0 tr n.
INC
DPTR
;Tng con tr d liu.
INC
R0
;Tng a ch vng RAM.
SJMP
LOOP
;Lp li.
EXIT:
SJMP
$
;Dng chng trnh.
ORG
200H
MYDATA:
DB
TP.HCM, 0
;Khai bo d liu, c k t NULL.
END
;Kt thc chng trnh.
Gio trnh Vi x l.
109
V d 15: Vit chng trnh ly gi tr x t P1 v lin tc gi gi tr x2 n P2.

Gii
ORG
0000H
MOV
MOV
P1, #0FFH
;Cu hnh P1 l port nhp.
LOOP:
MOV
A, P1
;Ly s liu x t P1.
MOVC
A, @A+DPTR
;Ly gi tr x2 t vng d liu.
MOV
P2, A
;Xut gi tr x2 ra P2.
SJMP
LOOP
;Lp li.
ORG
200H
MYDATA:
;Vng d liu tng ng t 02 - 92.
DB
0,1,4,9,16,25,36,49,64,81
END
V d 16: Vit on lnh tnh tng cc gi tr ca cc nh RAM ni c a ch 40H 44H. Kt
qu byte thp ct vo thanh ghi A v byte cao ct vo thanh ghi B.
Gii
MOV
R0, #40H
MOV
R1, #5
;Np gi tr b m (s lng nh).
CLR
A
;Xo ACC, A = 0.
MOV
B, A
;Xo thanh ghi B, B = 0
LOOP:
ADD
A, @R0
;Cng ni dung nh do R0 tr n vo A.
JNC
NO_CY
;Nhy nu khng c nh, CY = 0.
INC
B
;Tng thanh ghi B nu c nh, CY = 1.
NO_CY:
INC
R0
;Tng con tr n nh k tip.
DJNZ
R1, LOOP
V d 17: Vit on lnh tnh tng hai s 16 bit l 3CE7H v 3B8DH. Ct kt qu vo R7 (byte
cao) v R6 (byte thp).
Gii
CLR
C
;Xo c nh, CY = 0.
MOV
A, #0E7H
;Np byte thp 1 vo A, A = E7H.
ADD
A, #8DH
;Cng byte thp 2 vo A, A = 74H, CY = 1.
MOV
R6, A
;Lu byte thp ca tng vo R6.
MOV
A, #3CH
;Np byte cao 1 vo A, A = 3CH.
ADDC
A, #3BH
;Cng c nh byte cao 2 vo A, A = 78H.
MOV
R7, A
;Lu byte cao ca tng vo R7.
Gio trnh Vi x l.
110
V d 18: Vit on lnh tnh tng ca 5 d liu BCD c lu trong RAM ni ti a ch bt

u t 40H nh sau: (40H) = 71H, (41H) = 11H, (42H) = 65H, (43H) = 59H, (44H) = 37H. Kt qu
c lu vo thanh ghi R7 (byte cao) v thanh ghi A (byte thp) di dng s BCD.
Gii
MOV
R0, #40H
MOV
R1, #5
CLR
A
;Xo ACC, A = 0.
MOV
R7, A
;Xo thanh ghi R7, R7 = 0
LOOP:
ADD
A, @R0
;Cng ni dung nh do R0 tr n vo A.
DA
A
;Hiu chnh thnh s BCD.
JNC
NO_CY
;Nhy nu khng c nh, CY = 0.
INC
R7
;Tng thanh ghi R7 nu c nh, CY = 1.
NO_CY:
INC
R0
DJNZ
R1, LOOP
V d 19: Vit on lnh nhn d liu di dng s HEX trong phm vi 00H FFH t Port 1
v chuyn i v dng thp phn. Lu cc s vo cc thanh ghi R7 (LSB), R6 v R5 (MSB).
Gii
MOV
P1, #0FFH
MOV
A, P1
;c d liu t P1.
MOV
B, #10
;Np B = 10.
DIV
AB
;Chia cho 10, tch ly s cao/s thp.
MOV
R7, B
;Lu gi tr hng n v vo R7.
MOV
B, #10
;Np B = 10.
DIV
AB
;Chia cho 10, tch ly s cao/s thp.
MOV
R6, B
;Lu gi tr hng chc vo R6.
MOV
R5, A
;Lu gi tr hng trm vo R5.
V d 20: Vit on lnh c v kim tra Port 1 xem c cha gi tr 45H hay khng? Nu (P1) =
45H th xut gi tr 99H ra Port 2, ngc li th thot khi on lnh.
Gii
MOV
P2, #00H
;Xo P2, P2 = 0.
MOV
P1, #0FFH
MOV
R0, #45H
;Np R0 = 45H, gi tr cn kim tra.
MOV
A, P1
;c d liu t P1.
XRL
A, R0
;Kim tra d liu c bng 45H, nu bng th
JNZ
EXIT
;A = 0, khng bng th A ? 0.
MOV
P2, #99H
;Np P2 = 99H nu P1 = 45H (A = 0).
EXIT:
V d 21: Vit on lnh ly b 2 gi tr cha trong thanh ghi R0.
Gii
MOV
A, R0
;Np d liu cn ly b vo A.
CPL
A
;Ly b 1.
ADD
A, #1
;Cng thm 1 c b 2.
Gio trnh Vi x l.
111
V d 22: Vit on lnh kim tra thanh ghi A xem c cha gi tr 99H hay khng? Nu (A) =
99H th np gi tr FFH vo thanh ghi R1, ngc li th np gi tr 00H vo thanh ghi R1.
Gii
MOV
R1, #0
;Np R0 = 00H.
CJNE
A, #99H, NEXT ;So snh A vi gi tr 99H, nu khng
;bng th nhy n NEXT.
MOV
R1, #0FFH
;Np R0 = FFH nu A = 99H.
NEXT:
V d 23: Gi s mt cm bin nhit c ni ti ng vo P1. Hy vit on lnh c nhit
v so snh vi gi tr 75. Da vo kt qu kim tra t gi tr nhit vo cc thanh ghi nh sau:
Nu t = 75OC th (A) = 75.
Nu t < 75OC th (R1) = t.
Nu t > 75OC th (R2) = t.
Gii
MOV
P1, #0FFH
MOV
A, P1
;c d liu (t) t P1.
CJNE
A, #75, OVER ;So snh d liu (t) vi gi tr 75, nu
;khng bng th nhy n OVER.
SJMP
EXIT
;Nu A = 75 th thot chng trnh.
OVER:
;Trng hp khi d liu (t) khc 75.
JNC
NEXT
;Nhy n NEXT nu d liu (t) > 75, C=0.
MOV
R1, A
;Nu d liu (t) < 75 th np d liu vo
SJMP
EXIT
;R1 (R1 = A = t) v thot chng trnh.
NEXT:
;Trng hp khi d liu (t) > 75.
MOV
R2, A
;Np d liu vo R2 (R2 = A = t).
EXIT:
V d 24: Vit on lnh lin tc kim tra gi tr ti Port 1 nu gi tr ny khc 63H. Nu (P1) =
63H th thot on lnh khng kim tra na.
Gii
MOV
P1, #0FFH
HERE:
MOV
A, P1
;c d liu t P1.
CJNE
A, #63H, HERE ;Duy tr kim tra n khi P1 = 63H.
Gio trnh Vi x l.
112
V d 25: Gi s cc nh trong RAM ni c a ch t 40H 44H cha nhit ca cc ngy

c ch ra di y. Hy vit on lnh kim tra xem c gi tr no bng 65 khng? Nu c th t a
ch ca nh vo R4, ngc li th t R4 = 0.
(40H) = 76, (41H) = 79, (42H) = 69, (43H) = 65, (44H) = 64
Gii
MOV
R4, #0
;Xo R4 = 0.
MOV
R0, #40H
MOV
R1, #5
MOV
A, #65
;Np gi tr cn tm vo A, A = 65.
BACK:
CJNE
A, @R0, NEXT ;So snh d liu do R0 tr n vi 65.
MOV
R4, R0
;Nu bng th lu a ch nh vo R4.
SJMP
EXIT
;Thot chng trnh.
NEXT:
;Trng hp d liu do R0 tr n khc 65.
INC
R0
DJNZ
R2, BACK
;Lp li cho n khi b m bng 0.
EXIT:
V d 26: Vit on lnh tm tng cc ch s 1 trong thanh ghi R0.
Gii
MOV
R1, #0
;Xo R1 = 0, lu s ch s 1.
MOV
R2, #8
;Np gi tr b m (s bit kim tra).
MOV
A, R0
;Np d liu cn kim tra t R0 vo A.
LOOP:
RLC
A
;Xoay tri, a bit cn kim tra vo c CY.
JNC
NEXT
;Kim tra c CY.
INC
R1
;Tng gi tr ca R1 nu c CY = 1.
NEXT:
DJNZ
R2, LOOP
;Lp li cho n khi b m bng 0.
V d 27: Vit on lnh chuyn i s BCD nn cha trong thanh ghi A thnh hai s ASCII
v cha hai s ny trong thanh ghi R2 v R3.
Gii
MOV
A, #29H
;Np A = 29H, m BCD nn ca s 29.
MOV
R2, A
;Lu li s BCD cn chyn i trong R2.
ANL
A, #0FH
;Xo (che) 4 bit cao ca s BCD (A = 09H).
ORL
A, #30H
;Chuyn thnh m ASCII (A = 39H).
MOV
R3, A
;Ct vo R3 (R3 = 39H m ASCII ca 9).
MOV
A, R2
;Ly li s BCD lc ban u (A = 29H).
ANL
A, #0F0H
;Xo (che) 4 bit thp ca s BCD (A=20H).
SWAP
A
;Hon chyn v tr 4 bit cao vp bit thp.
ORL
A, #30H
;Chuyn thnh m ASCII (A = 32H).
MOV
R2, A
;Ct vo R2 (R2 = 32H m ASCII ca 2).
Gio trnh Vi x l.
113
V d 28: Gi s bit P2.3 l mt u vo v biu din nhit ca mt l sy. Nu P2.3 = 1 c

ngha l l qu nng. Hy lin tc kim tra bit ny, nu nhit qu cao th hy gi mt xung mc cao
n P1.5 bt ci bo hiu.
Gii
JNB
P2.3, $
;Duy tr kim tra u vo.
SETB
P1.5
;Khi P2.3 = 1, to mc cao cho P1.5 ri
CLR
P1.5
;to mc thp cho P1.5, pht mt xung.
V d 29: Vit on lnh kim tra xem thanh ghi A c cha mt s chn hay khng? Nu c th
chia cho 2, nu khng th tng ln 1 chn ho s ri chia n cho 2.
Gii
MOV
B, #2
;Gn s chia, B = 2.
JNB
ACC.0, OK
;Kim tra nu l s chn th nhy n OK.
INC
A
;Chn ho nu l s l.
OK:
DIV
AB
;Chia A cho 2.
V. PHN BI TP:
Truy xut RAM ni (theo 2 cch: nh a ch nh trc tip v gin tip):
Bi 1: Vit on lnh ghi (chuyn) gi tr 40H vo nh 30H ca RAM ni.
Bi 2: Vit on lnh xa ni dung nh 31H ca RAM ni.
Bi 3: Vit on lnh ghi (chuyn) ni dung thanh ghi A vo nh 32H ca RAM ni.
Bi 4: Vit on lnh ghi (chuyn) ni dung nh 33H ca RAM ni vo thanh ghi A.
Bi 5: Vit on lnh ghi (chuyn) ni dung nh 34H ca RAM ni vo nh 35H ca RAM
ni.
Bi 6: Vit on lnh ghi (chuyn) ni dung thanh ghi R4 vo nh 36H ca RAM ni.
Bi 7: Vit on lnh ghi (chuyn) ni dung nh 37H ca RAM ni vo thanh ghi R5.
Bi 8: Vit on lnh ghi (chuyn) ni dung thanh ghi A vo thanh ghi R1.
Bi 9: Vit on lnh ghi (chuyn) ni dung thanh ghi R2 vo thanh ghi A.
Bi 10: Vit on lnh ghi (chuyn) gi tr ABH vo thanh ghi A.
Bi 11: Vit on lnh ghi (chuyn) gi tr CDH vo thanh ghi R3.
Truy xut RAM ngoi:
Bi 1: Vit on lnh ghi (chuyn) gi tr 40H vo nh 30H ca RAM ngoi (RAM ngoi c
dung lng 256 byte).
Bi 2: Vit on lnh xa nh 31H ca RAM ngoi (RAM ngoi c dung lng 256 byte).
Bi 3: Vit on lnh ghi (chuyn) ni dung nh 32H ca RAM ngoi vo thanh ghi A (RAM
ngoi c dung lng 256 byte).
Bi 4: Vit on lnh ghi (chuyn) ni dung thanh ghi A vo nh 33H ca RAM ngoi (RAM
ngoi c dung lng 256 byte).
Bi 5: Vit on lnh chuyn d liu nh 34H ca RAM ngoi vo nh 35H ca RAM
ngoi (RAM ngoi c dung lng 256 byte).
Gio trnh Vi x l.
114
Bi 6: Vit on lnh ghi (chuyn) gi tr 40H vo nh 1230H ca RAM ngoi (RAM ngoi
c dung lng > 256 byte).
Bi 7: Vit on lnh xa nh 1231H ca RAM ngoi (RAM ngoi c dung lng > 256
byte).
Bi 8: Vit on lnh ghi (chuyn) ni dung nh 1232H ca RAM ngoi vo thanh ghi A
(RAM ngoi c dung lng > 256 byte).
Bi 9: Vit on lnh ghi (chuyn) ni dung thanh ghi A vo nh 1233H ca RAM ngoi
(RAM ngoi c dung lng > 256 byte).
Bi 10: Vit on lnh chuyn d liu nh 1234H ca RAM ngoi vo nh 1235H ca
RAM ngoi (RAM ngoi c dung lng > 256 byte).
Truy xut Port:
Bi 1: Vit on lnh xut (ghi) gi tr 0FH ra Port 1.
Bi 2: Vit on lnh xut (ghi) gi tr F0H ra Port 2.
Bi 3: Vit on lnh xut (ghi) ni dung thanh ghi A ra Port 1.
Bi 4: Vit on lnh nhp (c) t Port 1 vo thanh ghi A.
Bi 5: Vit on lnh nhp (c) t Port 1 v xut ra Port 2.
Bi 6: Vit on lnh xut (ghi) ni dung nh 37H ca RAM ni ra Port 3.
Bi 7: Vit on lnh nhp (c) t Port 2 vo nh 38H ca RAM ni.
Bi 8: Vit on lnh xut mc 1 (mc logic cao) ra chn P1.0
Bi 9: Vit on lnh xut mc 0 (mc logic thp) ra chn P1.1
Truy xut RAM ni, RAM ngoi v Port:
Bi 1: Vit on lnh chuyn nh 40H (RAM ni) vo nh 2000H (RAM ngoi).
Bi 2: Vit on lnh chuyn ni dung nh 2001H (RAM ngoi) vo nh 41H (RAM ni).
Bi 3: Vit on lnh nhp (c) t Port 1 vo nh 42H (RAM ni).
Bi 4: Vit on lnh nhp (c) t Port 1 vo nh 2002H (RAM ngoi).
Bi 5: Vit on lnh xut (ghi) ni dung nh 43H (RAM ni) ra Port 1.
Bi 6: Vit on lnh xut (ghi) ni dung nh 2003H (RAM ngoi) ra Port 1.
S dng vng lp:
Bi 1: Vit on lnh xa 20 nh RAM ni c a ch bt u l 30H.
Bi 2: Vit on lnh xa cc nh RAM ni t a ch 20H n 7FH.
Bi 3: Vit on lnh xa 250 nh RAM ngoi c a ch bt u l 4000H.
Bi 4: Vit on lnh xa 2500 nh RAM ngoi c a ch bt u l 4000H.
Bi 5: Vit on lnh xa cc nh RAM ngoi t a ch 2000H n 205FH.
Bi 6: Vit on lnh xa cc nh RAM ngoi t a ch 2000H n 3FFFH.
Bi 7: Vit on lnh xa ton b RAM ngoi c dung lng 8KB, bit rng a ch u l
2000H.
Gio trnh Vi x l.
115
Bi 8: Vit on lnh chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l

30H n vng RAM ni c a ch u l 40H.
Bi 9: Vit on lnh chuyn mt chui d liu gm 100 byte trong RAM ngoi c a ch u
l 2000H n vng RAM ngoi c a ch u l 4000H.
Bi 10: Vit on lnh chuyn mt chui d liu gm 1000 byte trong RAM ngoi c a ch
u l 2000H n vng RAM ngoi c a ch u l 4000H.
Bi 11: Vit on lnh chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l
30H n vng RAM ngoi c a ch u l 4000H.
Bi 12: Vit on lnh chuyn mt chui d liu gm 10 byte trong RAM ngoi c a ch u
l 5F00H n vng RAM ni c a ch u l 40H.
Bi 13: Cho mt chui d liu gm 20 byte lin tip trong RAM ni, bt u t a ch 20H.
Hy vit on lnh ln lt xut cc d liu ny ra Port 1.
Bi 14: Gi s Port 1 c ni n mt thit b pht d liu (v d nh 8 nt nhn). Hy vit
on lnh nhn lin tip 10 byte d liu t thit b pht ny v ghi vo 10 nh (RAM ni) lin tip
bt u t nh 50H.
To tr:
Bi 1: Vit chng trnh con delay 100s, bit rng fOSC dng trong h thng l:
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
Bi 2: Vit chng trnh con delay 100ms, bit rng fOSC dng trong h thng l:
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
To xung:
) ti chn P1.0 vi rng xung 1ms, bit
Bi 1: Vit on lnh to mt xung dng (
rng fOSC =12 MHz.
Bi 2: Vit on lnh to chui xung vung c f = 100 KHz ti chn P1.1 (fOSC =12 MHz).
Bi 3: Vit on lnh to chui xung vung c f = 100 KHz v c chu k lm vic D = 40% ti
chn P1.2 (fOSC =12 MHz).
Bi 6: Vit on lnh to chui xung vung c f = 10 Hz ti chn P1.4 (fOSC =12 MHz).
Bi 7: Vit on lnh to chui xung vung c f = 10 Hz v c chu k lm vic D = 25% ti
chn P1.5 (fOSC =11,0592 MHz).
Cc php ton:
Gio trnh Vi x l.
116
Bi 1: Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy

vit chng trnh con cng chui s ny v ghi kt qu vo nh 2FH trong RAM ni (gi s kt qu
nh hn hoc bng 255).
Bi 2: Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy
vit chng trnh con cng chui s ny v ghi kt qu vo hai nh 2EH:2FH trong RAM ni ( nh
2EH cha byte cao ca kt qu v nh 2FH cha byte thp ca kt qu).
Bi 3: Cho mt chui s 16 bit khng du trong RAM ni gm 10 s bt u t nh 30H theo
nguyn tc nh c a ch nh hn cha byte cao v nh c a ch ln hn cha byte thp. (V d:
byte cao ca s 16 bit u tin c ct ti nh 30H v byte thp ca s 16 bit u tin c ct ti
nh 31H; byte cao ca s 16 bit th hai c ct ti nh 32H v byte thp ca s 16 bit th hai
c ct ti nh 33H). Hy vit chng trnh con cng chui s ny v ct kt qu vo hai nh
2EH:2FH trong RAM ni.
Bi 4: Tng t nh cc bi 1, 2, 3 nhng thc hin i vi php tr.
Bi 5: Vit chng trnh con ly b 2 s 16 bit cha trong hai thanh ghi R2:R3.
So snh:
Bi 1: Cho hai s 8 bit, s th nht cha trong nh 30H, s th hai cha trong nh 31H.
Vit chng trnh con so snh hai s ny. Nu s th nht ln hn hoc bng s th hai th set c F0,
nu ngc li th xa c F0.
Bi 2: Cho hai s 16 bit, s th nht cha trong hai nh 30H:31H, s th hai cha trong hai
nh 32H:33H. Vit chng trnh con so snh hai s ny. Nu s th nht ln hn hoc bng s th hai
th set c F0, nu ngc li th xa c F0.
Bi 3: Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch
50H. Vit on lnh xut cc k t in hoa c trong chui ny ra Port 1. Bit rng m ASCII ca k t
in hoa l t 65H (ch A) n 90H (ch Z).
Bi 4: Vit on lnh nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM
ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v
ghi c k t ny vo RAM.
khng ghi k t ny vo RAM.
khng ghi k t ny vo RAM m thay bng k t NULL (c m ASCII l 00H).
Bi 7: Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch
50H. Vit on lnh i cc k t in hoa c trong chui ny thnh k t thng. Bit rng m ASCII
ca k t thng bng m ASCII ca k t in hoa cng thm 32H.
Bi 8: Cho mt chui k t s di dng m ASCII trong RAM ni, di 20 byte, bt u t a
ch 50H. Vit on lnh i cc k t s ny thnh m BCD. Bit rng m ASCII ca cc k t s l t
30H (s 0) n 39H (s 9).
S dng lnh nhy c iu kin:
Bi 1: Cho mt chui d liu di dng s c du trong RAM ngoi, di 100 byte, bt u t
a ch 0100H. Vit on lnh ln lt xut cc d liu trong chui ra Port 1 nu l s dng (xem s 0
l dng) v xut ra Port 2 nu l s m.
Bi 2: Cho mt chui d liu di dng s c du trong RAM ngoi, bt u t a ch 0100H
v kt thc bng s 0. Vit on lnh ln lt xut cc d liu trong chui ra Port 1 nu l s dng v
xut ra Port 2 nu l s m.
Gio trnh Vi x l.
117
Bi 3: Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch

0100H v di chui l ni dung nh 00FFH. Vit on lnh m s s chn (chia ht cho 2) c
trong chui v ct vo nh 00FEH.
Bi 4: Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch
0100H v di chui l ni dung nh 00FFH. Vit on lnh ghi cc s chn (xem s 0 l s chn)
c trong chui vo RAM ni bt u t a ch 30H cho n khi gp s l th dng.
Bi 5: Vit chng trnh con c nhim v ly mt byte t mt chui data gm 20 byte ct trong
RAM ngoi bt u t a ch 2000H v xut ra Port1. Mi ln gi chng trnh con ch xut mt
byte, ln gi k th xut byte k tip, ln gi th 21 th li xut byte u, ...
Gio trnh Vi x l.
118
Chng 4: Hot ng ca b nh thi (Timer).
CHNG 4
HOT NG CA B NH THI
(TIMER)
I. M U:
Bo nh
thi
(TIMER)
La chuoi cac FF (moi FF la 1 mach chia 2).

Ngo vao: nhan tn hieu xung clock t nguon xung.
Ngo ra: truyen tn hieu xung clock cho FF bao tran (c tran).
Tn s: tn s xung ng ra bng tn s xung ng vo chia cho 2N.

Gi tr: gi tr nh phn trong cc FF ca b nh thi l s m ca cc xung clock ti ng vo
t khi b nh thi bt u m.
Trn: xy ra hin tng trn (c trn = 1) khi s m chuyn t gi tr ln nht xung gi tr
nh nht ca b nh thi.
V d: B nh thi 16 bit (cha 16 FF bn trong).
f
f
o Tn s: f
= IN = IN
OUT 216 65536
o Gi tr: s m nm trong khong 0 (0000H) 65535 (FFFFH).
o Trn: c trn bng 1 khi s m t FFFFH chuyn xung 0000H.
Hnh minh ha n gin hot ng ca b nh thi 3 bit:
Hot ng ca mt b nh thi 3 bit n gin c minh ha trong hnh trn. Mi mt tng l D

FF kch khi cnh m hot ng nh mt mch chia 2 do ta ni ng ra Q vi ng vo D. Flipflop c
(Flag FF) l mt mch cht D c set bng 1 bi tng cui ca b nh thi. Gin thi gian cho
Gio trnh Vi x l.
119
thy tng th nht (Q0) chia 2 tn s xung clock, tng th hai (Q1) chia 4 tn s xung clock, S m
c ghi dng thp phn v c kim tra d dng bng cch kho st trng thi ca 3 flipflop. V
d, s m l 4 xut hin khi Q2 = 1, Q1 = 0, Q0 = 0. Cc flipflop trn l cc flipflop tc ng cnh
m (ngha l trng thi ca cc flipflop s thay i theo cnh m ca xung clock). Khi s m trn t
111 xung 000, ng ra Q2 c cnh m lm cho trng thi ca flipflop c i t 0 ln 1 (ng vo D ca
flipflop ny lun lun logic 1).
ng dng nh thi gian (TIMER): b nh thi c lp trnh sao cho s trn sau mt khong
thi gian qui nh v khi c trn ca b nh thi s bng 1.
ng dng m s kin (COUNTER): xc nh s ln xut hin ca mt kch thch t bn
ngoi ti mt chn ca chip 8051 (kch thch l s chuyn trng thi t 1 xung 0).
ng dng to tc baud cho port ni tip: xem thm trong chng Chng 5: Hot ng
port ni tip..
Gio trnh Vi x l.
120
II. THANH GHI CH NH THI (TMOD):

Thanh ghi TMOD (Timer Mode Register) cha cc bit dng thit lp ch hot ng cho b
nh thi 0 v b nh thi 1.
Thanh ghi TMOD c np gi tr mt ln ti thi im bt u ca chng trnh qui nh
ch hot ng ca cc b nh thi.
Cu trc thanh ghi TMOD:
Bit
7
TMOD: Timer Mode Register

M0: Bit chon che o hoat ong cho bo nh thi.
C/T: Bit chon chc nang em hoac nh thi.

C/T=1: Bo nh thi la bo em (Counter).
C/T=0: Bo nh thi la bo nh khoang thi gian (Timer).
GATE: Bit ieu khien cong.

GATE=0: Bo nh thi hoat ong khi bit TR0=1 (ieu khien
bang phan mem).
GATE=1: Bo nh thi hoat ong khi chan INT0\=1 (ieu
khien bang phan cng).
C/T: Bit chon chc nang em hoac nh thi.

C/T=1: Bo nh thi la bo em (Counter).
C/T=0: Bo nh thi la bo nh khoang thi gian (Timer).
Hnh 4.2.1:
Thanh ghi chon
che o nh thi.
GATE: Bit ieu khien cong.

GATE=0: Bo nh thi hoat ong khi bit TR1=1 (ieu khien
bang phan mem).
GATE=1: Bo nh thi hoat ong khi chan INT1\=1 (ieu
khien bang phan cng).
Cc ch hot ng ca b nh thi:
Gio trnh Vi x l.
121
V d 1: Cho bit gi tr cn np cho thanh ghi TMOD

o Timer 0: l b nh thi gian 16 bit, c iu khin bng phn mm (bit TR0).
o Timer 1: l b m xung 13 bit, c iu khin bng phn cng (chn INT 1 ).
Gii
Phn tch:
(1): Ch 16 bit.
(2): B nh thi gian.
(3): iu khin bng phn mm.
(4): Ch 13 bit.
(5): B m xung.
(6): iu khin bng phn cng.

M1 = 0, M0 = 1.
C / T = 0.
GATE = 0.
M1 = 0, M0 = 0.
C / T = 1.
GATE = 1.
T ta c: (TMOD) = 11000001B = C1H.

V d 2: Cho bit gi tr cn np cho thanh ghi TMOD
o Timer 0: khng s dng.
o Timer 1: l b nh thi gian 8 bit t np li, c iu khin bng phn mm (bit TR1).
Gii
Phn tch:
(1): Khng s dng.

M1 = 0, M0 = 0.
(2): Khng s dng.

C / T = 0.
(3): Khng s dng.

GATE = 0.
Do Timer 0 khng s dng, nn ta c thit lp n bt c ch no. Thng thng
d dng ta nn cho: GATE=0, C / T = 0, M1 = 0 v M0 = 0.
(4): Ch 8 bit t ng np li.

M1 = 1, M0 = 0.
(5): B nh thi gian.

C / T = 0.

GATE = 0.
T ta c: (TMOD) = 00100000B = 20H.
Gio trnh Vi x l.
122
V d 3: Cho bit (TMOD) = A5H. Hy cho bit ch hot ng ca cc Timer 0 v Timer 1.

Gii
Ta c: (TMOD) = A5H = 10100101B.
Gii thch:
M1 = 1, M0 = 0.
C / T = 0.
GATE = 1.
M1 = 0, M0 = 1.
C / T = 1.
GATE = 0.


(5): B nh thi gian.
(6): iu khin bng phn cng.
(1): Ch 16 bit.
(2): B m xung.
T ta c:
o Timer 0: l b m xung 16 bit, c iu khin bng phn mm (bit TR0).
o Timer 1: l b nh thi gian 8 bit t np li, c iu khin bng phn cng (chn INT 1 ).
V d 4: Cho bit (TMOD) = 21H. Hy cho bit ch hot ng ca cc Timer 0 v Timer 1.
Gii
Ta c: (TMOD) = 21H = 00100001B.
Gii thch:
M1 = 1, M0 = 0.
C / T = 0.
GATE = 0.
M1 = 0, M0 = 1.
C / T = 0.
GATE = 0.


(5): B nh thi gian.
(1): Ch 16 bit.
(2): B nh thi gian.
T ta c:
o Timer 0: l b nh thi gian 16 bit, c iu khin bng phn mm (bit TR0).
o Timer 1: l b nh thi gian 8 bit t np li, c iu khin bng phn mm (bit TR1).
Gio trnh Vi x l.
123
III. THANH GHI IU KHIN NH THI (TCON):

Thanh ghi TCON (Timer Control Register) cha cc bit dng iu khin v bo trng thi
ca b nh thi 0 v b nh thi 1.
Cu trc thanh ghi TCON:
Lu : Cc bit IT0, IT1, IE0, IE1 khng dng iu khin cc b nh thi. Cc bit ny c
dng pht hin v khi ng cc ngt ngoi. Vic tho lun cc bit ny s c trnh by
trong Chng 6: Hot ng ngt..
Gio trnh Vi x l.
124
IV. CC CH NH THI V C TRN:

1. Ch nh thi 13 bit (Ch 0):
Ch 0 (Mode 0):
Ch nh thi 13 bit.
S dng 8 bit ca thanh ghi THx v 5 bit thp ca thanh ghi TLx to ra b nh thi.
S m: 0000H 1FFFH ngha l t 0 8191. Thi gian nh thi: t 1.TTimer 213.TTimer
ngha l t 1.TTimer 8192.TTimer.
Thanh ghi THx v TLx cha gi tr ca b nh thi.
Khi c xung clock, b nh thi bt u m ln t gi tr cha trong THx/TLx.
Xy ra trn (c trn TFx=1) khi s m chuyn t 1FFFH sang 0000H v vic m s tip tc
m ln t gi tr 0000H.
Kin trc ca Timer 0 ch 0 (Mode 0).
Gio trnh Vi x l.
125
2. Ch nh thi 16 bit (Ch 1):
Ch 1 (Mode 1):
Ch nh thi 16 bit.
S dng thanh ghi THx v TLx to ra b nh thi.
S m: 0000H FFFFH ngha l t 0 65535. Thi gian nh thi: t 1.TTimer 216.TTimer
ngha l t 1.TTimer 65536.TTimer.
Thanh ghi THx v TLx cha gi tr ca b nh thi.
Khi c xung clock, b nh thi bt u m ln t gi tr cha trong THx/TLx.
Xy ra trn (c trn TFx=1) khi s m chuyn t FFFFH sang 0000H v vic m s tip tc
m ln t gi tr 0000H.
Gio trnh Vi x l.
126
3. Ch nh thi 8 bit t np li (Ch 2):
Ch 2 (Mode 2):
Ch nh thi 8 bit t np li.
S dng thanh ghi TLx to ra b nh thi.
S m: 00H FFH ngha l t 0 255. Thi gian nh thi: t 1.TTimer 28.TTimer ngha l
t 1.TTimer 256.TTimer.
Thanh ghi TLx cha gi tr ca b nh thi v thanh ghi THx cha gi tr s c dng np
li cho b nh thi.
Khi c xung clock, b nh thi bt u m ln t gi tr cha trong TLx (THx khng thay i
gi tr).
Xy ra trn (c trn TFx=1) khi s m chuyn t FFH sang 00H, ng thi gi tr trong THx
s c np vo TLx v vic m s tip tc m ln t gi tr cha trong thanh ghi TLx (gi tr
ny bng vi gi tr ca THx).
Gio trnh Vi x l.
127
4. Ch nh thi chia x (Ch 3):

TH1
TL1
Timer
clock
TF0
TL0
Timer
clock
TF1
TH0
/12FOSC
Overflow
flag
x = 0, 1: Bo nh thi 0, 1.
Timer clock: Xung clock cho bo nh thi.
Overflow flag: C tran.
Ch 3 (Mode 3) l:
Ch nh thi chia x.
B nh thi 0 c chia ra:
o B nh thi 8 bit th I:
S dng thanh ghi TL0 to ra b nh thi.
S m: 00H FFH ngha l t 0 255. Thi gian nh thi: t 1.TTimer
28.TTimer ngha l t 1.TTimer 256.TTimer.
Thanh ghi TL0 cha gi tr ca b nh thi.
Khi c xung clock, b nh thi bt u m ln t gi tr cha trong TL0.
Xy ra trn (c trn TF0=1) khi s m chuyn t FFH sang 00H v vic m s
tip tc m ln t gi tr 00H.
o B nh thi 8 bit th II:
S dng thanh ghi TH0 to ra b nh thi.
S m: 00H FFH ngha l t 0 255. Thi gian nh thi: t 1.TTimer
28.TTimer ngha l t 1.TTimer 256.TTimer.
Thanh ghi TH0 cha gi tr ca b nh thi.
Khi c xung clock, b nh thi bt u m ln t gi tr cha trong TH0.
Xy ra trn (c trn TF1=1) khi s m chuyn t FFH sang 00H v vic m s
tip tc m ln t gi tr 00H.
B nh thi 1:
o L b nh thi 16 bit.
o Khng hot ng ch 3 nhng c th hot ng cc ch khc (ch 0, 1, 2).
o Khng c c bo trn nh cc b nh thi khc.
Gio trnh Vi x l.
128

V. NGUN XUNG CLOCK CHO B NH THI:
Ngun xung cho b nh thi c to ra t:
Mch dao ng trn chip dng cho tnh nng nh thi gian.
Xung kch thch bn ngoi dng cho tnh nng m s kin.
1. Trng hp nh thi gian:
Nu C/T=0 th:
B nh thi c dng nh thi gian (Timer).
Ngun xung clock nh thi c ly t mch dao ng trn chip.
Lu :
o Tn s xung clock cung cp cho b nh thi bng 1/12 tn s ca mch dao ng trn
chip 8051.
o Thi gian nh thi l khong thi gian c tnh t lc b nh thi bt u m ln (t
gi tr cha trong cc thanh ghi THx/TLx) cho n lc b nh thi bt u trn (thi
gian ny ph thuc vo gi tr ban u c np cho cc thanh ghi THx v TLx).
Gio trnh Vi x l.
129
V d: Tm tn s xung clock v chu k ca b nh thi i vi trng hp cc h thng vi iu

khin xy dng trn chip 8051 vi tn s thch anh nh sau: 11,0592 MHz, 12 MHz v 16 MHz.
Gii
Gi fTIMER l tn s xung clock ca b nh thi, fOSC l tn s xung clock ca thch anh. Theo nh
trn trnh by, ta c:
f
f
11,0592(MHz )
= 11,0592(MHz ) f
= OSC =
= 921,6(KHz )
TIMER
OSC
12
12
1
1
T
=
=
= 1,085(s )
TIMER f
921,6(KHz )
TIMER
f
12(MHz )
= 12(MHz ) f
= OSC =
= 1(MHz )
TIMER
OSC
12
12
1
1
T
=
=
= 1(s )
TIMER f
1(MHz )
TIMER
f
16(MHz )
= 16(MHz ) f
= OSC =
= 1,333(MHz )
TIMER
OSC
12
12
1
1
T
=
=
= 0,75(s )
TIMER f
1,333(MHz )
TIMER
2. Trng hp m s kin:
Nu C/T=1 th:
B nh thi c dng m s kin (Counter).
Ngun xung clock nh thi c ly t xung kch thch bn ngoi ti hai chn T0 v T1 ca
chip 8051.
Lu :
o Tn s kch thch ti a cho php ti chn T0 v T1:
f
= TIMER
T 0,T 1( MAX )
2
fTIMER: tn s xung clock nh thi.

fT0,T1(MAX): tn s kch thch ti a cho php ti T0 v T1.
Gio trnh Vi x l.
130
V d: Tnh tn s kch thch ti a cho php ti chn T0 v T1 i vi trng hp cc h thng

vi iu khin xy dng trn chip 8051 vi tn s thch anh nh sau: 11,0592 MHz, 12 MHz v
16 MHz.
Gii
OSC
= 11,0592(MHz ) f
f
921,6(KHz )
= TIMER =
= 460,8(KHz )
T 0,T 1( MAX )
2
2
f
1(MHz )
= 12(MHz ) f
= TIMER =
= 500(KHz )
OSC
T 0,T 1( MAX )
2
2
f
1,333(MHz )
= 16(MHz ) f
= TIMER =
= 666,5(KHz )
OSC
T 0,T 1( MAX )
2
2
o S lng s kin (s xung) m b nh thi m c s c cha trong cc thanh ghi

THx/TLx, gi tr trong cc thanh ghi ny s tng theo mi xung kch thch bn ngoi ti T0 v T1 ca
chip 8051.
o Mt kch thch c gi l mt s kin (mt xung) khi xy ra s chuyn trng thi t 1
xung 0 chn T0 hoc T1.
VI. KHI NG, DNG V IU KHIN CC B NH THI:
Cch 1: (thng c dng nh thi gian).

iu kin s dng: bit GATE = 0
(Phng php iu khin bng phn mm)
B nh thi x chy khi bit TRx = 1.

B nh thi x dng khi bit TRx = 0.
V d:
khi ng b nh thi 0 ta dng lnh:

dng b nh thi 0 ta dng lnh:
SETB TR0
CLR TR0
Cch 2: (thng c dng o rng xung ti chn INTx\ ).

iu kin s dng: bit GATE = 1 v bit /TRx = 1
(Phng php iu khin bng phn cng)
B nh thi x chy khi chn INTx\ = 1.

B nh thi x dng khi chn INTx\ = 0.
V d: o rng xung (tnh bng s) ti chn INT0, vi fOSC = 12MHz.
INT0\
t ( s)
Gio trnh Vi x l.
131
Gii
Ta khi ng b nh thi 0 nh sau:
Ch nh thi 16 bit (ch 1).
Gi tr trong TH0/TL0 l 0000H.
GATE = 1 v TR0 = 1 (iu khin hot ng ca Timer 0 bng phn cng, tc iu khin bng
tn hiu ti chn INT0\).
rng xung (tnh bng s) = S m cha trong TH0/TL0.

Hnh minh ha Timer 1 hot ng ch 1 (Timer 16 bit):
12 MHz
On-chip
Osc.
12
8051
TL1 TH1
T1
(P3.5)
0 = Up
1 = Down
C/T
TF1
0 = Up
1 = Down
TR1
GATE
INT1
(P3.3)
Hoat ong che o 1 cua Timer 1

VII. KHI NG V TRUY XUT THANH GHI NH THI:
Trc khi cc b nh thi hot ng cn phi:

Qui nh ch ca b nh thi thanh ghi TMOD.
Qui nh im bt u m ca b nh thi (khong thi gian nh thi) thanh ghi
THx/TLx.
o V d 1: Khi ng b nh thi 1 hot ng ch 16 bit, xung clock c ly t mch
dao ng trn chip (ngha l b nh c dng nh thi mt khong thi gian), c khi ng
bng bit TR1 (iu khin bng phn mm).
Gii
Ta dng lnh:
MOV TMOD, #10H
hoc
MOV TMOD, #00010000B
Gio trnh Vi x l.
132
Gii thch:
GATE = 0 iu khin bng phn mm (bit TR1).

C/T = 0 s dng mch dao ng trn chip (dng nh mt khong thi gian).
M1 = 0, M1 = 1 TIMER1 hot ng ch 1 (ch nh thi 16 bit).
o V d 2: Dng b nh thi 1 v d trn nh mt khong thi gian l 100 s. Gi s vi
iu khin s dng thch anh 12 MHz.
Gii
Ta dng lnh:
MOV TL1, #9CH
MOV TH1, #0FFH
hoc
MOV TL1, #LOW(-100)
MOV TH1, #HIGH(-100)
Gii thch:
f
12
= 12(MHz ) f
= OSC = = 1(MHz )
f
TIMER
OSC
12
12
1
1
T
=
=
= 1(s )
TIMER f
1(MHz )
TIMER
fOSC: tn s thch anh.

fTIMER: tn s xung clock nh thi.
TTIMER: chu k xung clock nh thi.
Vy c mi 1s (tc l sau mi chu k ca xung clock nh thi) th b nh thi s tng gi tr
mt ln.
Trong :
M ta bit: thi gian nh thi l khong thi gian c tnh t lc b nh thi bt u m ln

cho n lc b nh thi bt u trn.
Vy b nh thi trn s trn sau khong thi gian 100s th ta phi khi ng b nh thi ti
thi im cch im trn (theo chiu m v b nh thi ch m ln) 100 chu k xung clock nh
thi.
V im trn c gi tr l 0 cho nn gi tr cn np cho cc thanh ghi TH1/TL1 l -100 (hay
FF9CH).
Gio trnh Vi x l.
133
Tng qut, ta c cng thc tnh gi tr cn np cho b nh thi c thi gian nh thi nh
mong mun l:
f
N = OSC t
12 DELAY
Trong :
N: gi tr cn np cho b nh thi.
tDELAY (s): thi gian cn nh thi.
2. Truy xut gi tr ca b nh thi ang hot ng:
Trong cc ng dng thc t, ta cn phi c gi tr (ni dung) cha trong cc thanh ghi nh thi
THx/TLx trong khi b nh thi vn ang hot ng. Do gi tr ca b nh thi c cha trong c hai
thanh ghi THx/TLx. Cho nn ta phi c hai thanh ghi ny bng hai dng lnh lin tip nhau (do khng
c lnh no c th c ng thi c hai thanh ghi nh thi ny). Mt s sai pha (phase error) c th
xut hin nu c s trn t byte thp chuyn sang byte cao gia hai ln c v do vy ta khng th c
ng c gi tr cn c.
V d: Minh ha v s sai pha (phase error) c th xut hin nu c s trn t byte thp chuyn
sang byte cao gia hai ln c gi tr lm cho ta khng th c ng c gi tr cn c ca THx/TLx
trong khi b nh thi ang hot ng.
Gii
Gii php a ra l trc tin ta phi c byte cao, k n c byte thp v ri c byte thp ln
na. Nu byte cao thay i gi tr, ta lp li thao tc c va nu. Lu gii thut dng c chnh
xc gi tr (ni dung) cha trong cc thanh ghi nh thi THx/TLx ca b nh thi ang hot ng:
Gio trnh Vi x l.
134
V d: c ni dung ca cc thanh ghi TH1/TL1 trong khi b nh thi 1 ang hot ng. Ni
dung sau khi c ca thanh ghi TH1 cha trong R7, ca thanh ghi TL1 cha trong R6.
AGAIN:
MOV A, TH1
MOV R6, TL1
CJNE A, TH1, AGAIN
MOV R7, A
VIII. CC KHONG THI GIAN NH THI:
Kho st trng hp 8051 dng thch anh 12 MHz:

Khong thi gian nh thi ngn nht (s): 1
Khong thi gian nh thi di nht (s):
o 10
Dng cc lnh.
Dng b nh thi 8 bit t ng np li.

o 256
o 65536
Dng b nh thi 16 bit.

Dng b nh thi 16 bit + cc vng lp.
o Khng gii hn
Kho st trng hp tng qut:
Khong thi gian nh thi ngn nht: 1.TTIMER
Khong thi gian nh thi di nht:
o 10.TTIMER
Dng cc lnh.
o 256.TTIMER
Dng b nh thi 8 bit t ng np li.

Dng b nh thi 16 bit.
o 65536.TTIMER
o Khng gii hn
Dng b nh thi 16 bit + cc vng lp.
vi TTIMER =
f
12
TTIMER(s): chu k xung clock nh thi.
OSC
Gio trnh Vi x l.
135
IX. CC BC C BN KHI NG TIMER V COUNTER:

1. Cc bc c bn khi ng Timer:
Chn ch hot ng cho Timer, cho bit GATE=0 v C/T=0:
MOV TMOD, #...(1)
Chn gi tr thch hp (khong thi gian nh thi) cho Timer:
MOV THx, #...(2)
MOV TLx, #...(3)
Cho Timer chy:
SETB TRx
Kim tra c bo trn (kim tra thi gian nh thi):
JNB TFx, $
hoc
WAIT: JNB TFx, WAIT
Xa c bo trn (chun b cho ln nh thi tip theo):
CLR TFx
Dng Timer (sau khi hon tt qu trnh nh thi):
CLR TRx
Lu :
x: S th t ca Timer s dng.
(1): Gi tr ny ph thuc vo Timer c chn v ch hot ng ca Timer .
(2), (3): Gi tr ny ph thuc vo khong thi gian cn nh thi. Cng cn lu thm, vic
chn gi tr cho khng phi lc no ta cng phi chn gi tr cho c hai thanh ghi ny m n ty thuc
vo tng ch hot ng ca Timer (Mode 0: THx/TLx, Mode 1: THx/TLx, Mode 2: THx, Mode 3: THx
hoc TLx).
Cc gi tr trn phi tho mn iu kin sau:
o Ch 8 bit: gi tr trong khong t -255 n -1 (tng ng t 255.TTIMER n 1.TTIMER).
V d:
MOV TH1, #(-255) nh thi 255.TTIMER
V d:
MOV TL1, #LOW(-8000) nh thi 8000.TTIMER

V d:
MOV TL1, #LOW(-10000) nh thi 10000.TTIMER

Trng hp c bit nu gi tr (N) np vo thanh ghi THx/TLx l gi tr 0 th thi gian nh

thi s l ln nht cho tng ch .
Ch 8 bit: N = 0 tDELAY = 256.TTIMER.
Gio trnh Vi x l.
136
2. Cc bc c bn khi ng Counter:
Chn ch hot ng cho Counter, cho bit GATE=0 v C/T=1:
MOV TMOD, #...(1)
Xo cc gi tr cha trong thanh ghi THx v TLx (ngha l cho s xung ban u bng 0):
MOV THx, #00H
MOV TLx, #00H
Cho Counter chy:
SETB TRx
Kim tra c bo trn (kim tra s m b trn) x l trng hp s m b trn.
Xa c bo trn (sau khi x l cho trng hp s m b trn):
CLR TFx
Dng Counter (sau khi hon tt qu trnh m xung):
CLR TRx
c s xung m c trong thanh ghi THx v TLx.
Lu :
x: S th t ca Counter s dng.
(1): Gi tr ny ph thuc vo Counter c chn v ch hot ng ca Counter. Gi tr ny
phi tho mn iu kin sau:
o
Ch 8 bit: s lng xung ti a m Counter m c t 0 n 255.
Trong qu trnh c s xung m c cha trong cc thanh ghi THx/TLx ta phi ch n

trng hp Counter b trn. V khi gi tr trong thanh ghi THx/TLx (ni cha s xung m c) s
tr v 0. Cho nn nu ta khng c bin php x l cho trng hp ny th kt qu l s xung m ta
nhn c s b sai. V th, nu ta gi s ban u Counter c khi ng vi gi tr l 0 th c mi ln
Counter b trn th ta phi cng thm vo s xung c v 256 xung (trng hp 8 bit) hoc 8192 xung
(trng hp 13 bit) hoc 65536 xung (trng hp 16 bit).
X. CC V D MINH HA:
1. V d 1: (To dng xung)
Vit chng trnh to dng xung tun hon trn chn P1.0 c tn s cao nht c th c. Tn s
v chu k nhim v ca dng xung ny l bao nhiu?
Gii
LOOP:
Gio trnh Vi x l.
ORG 8100H
SETB P1.0
CLR P1.0
SJMP LOOP
END
;1 chu k my
;1 chu k my
;2 chu k my
137
Chu k xung: 4 s Tn s xung: 250 KHz.

Thi gian mc cao: 1 s.
Thi gian mc thp: 3 s.
Chu k nhim v: 25%.
2. V d 2: (To thi gian tr)

Vit chng trnh con to thi gian tr tDelay, s dng phng php dng cc lnh (khng dng
Timer). Bit rng tn s thch anh l 12 MHz.
a. Thi gian tr tDelay = 100 s.
b. Thi gian tr tDelay = 10 ms.
c. Thi gian tr tDelay = 1 s.
Gii
Phng php:
Phng php thc hin l s dng lnh vng lp DJNZ to thi gia tr tDelay nh mong mun. V
d mu:
DELAY:
;tDelay = 10 x 20 x 30 x 2.TTimer
MOV R0, #10
BBB:
MOV R1, #20
AAA:
MOV R2, #30
DJNZ R2, $
;lnh 2.TTimer
DJNZ R1, AAA
DJNZ R0, BBB
RET
Tng qut, ta c cng thc tnh thi gian tr tDelay nh sau:
t
Trong :
Delay
= [Rn ] [Rm] ... [Rv ] 2.
12
f
(1)
Osc
tDelay (s): thi gian tr.

fOsc (MHz): tn s thch anh.
12
=
TTimer (s): chu k Timer T
.
Timer f
Osc
[Rn], [Rm], , [Rv]: gi tr ca cc vng lp (s ln lp li lnh
DJNZ).
Lu : Gi tr ca cc vng lp phi tha iu kin 0 [Rn] 255. c bit nu chn [Rn] = 0
th iu ny s tng ng vi trng hp ta chn [Rn] = 256 (tng t cho cc [Rm], , [Rv] khc).
Tnh ton: Tm gi tr cn np cho cc thanh ghi vng lp:
12
= [Rn ] [Rm ] ... [Rv ] 2.
Ta c: t
Delay
f
Osc
Vi tDelay = 100 s, fOsc = 12 MHz th ta chn:
[Rn] = 50
12
t
= 50 2. = 100 s
Delay
12
Gio trnh Vi x l.
138
Vi tDelay = 10 ms, fOsc = 12 MHz th ta chn:

[Rn] = 20 v [Rm] = 250
12
= 20 250 2. = 10000 s
t
Delay
12
Vi tDelay = 1 s, fOsc = 12 MHz th ta chn:
[Rn] = 10, [Rm] = 200 v [Ro] = 250
12
= 10 200 250 2. = 1000000 s
t
Delay
12
Chng trnh: Da vo nhng tnh ton trn, ta c:
Vi tDelay = 100 s:
DELAY:
MOV R0, #50
DJNZ R0, $
RET
;tDelay = 50 x 2.TTimer
;lnh 1.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
Vi tDelay = 10 ms:
DELAY:
MOV R0, #20
AAA:
MOV R1, #250
DJNZ R1, $
DJNZ R0, AAA
RET
;tDelay = 20 x 250 x 2.TTimer

;lnh 1.TTimer
;lnh 1.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
Vi tDelay = 1 s:
DELAY:
MOV R0, #10
BBB:
MOV R1, #200
AAA:
MOV R2, #250
DJNZ R2, $
DJNZ R1, AAA
DJNZ R0, BBB
RET
;tDelay = 10 x 200 x 250 x 2.TTimer

;lnh 1.TTimer
;lnh 1.TTimer
;lnh 1.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
;lnh 2.TTimer
Lu v chnh xc ca tDelay: Khi s dng phng php to thi gian tr nh trn (phng
php dng lnh, khng dng Timer) th vic nh thi gian thng c mt sai s nht nh. V y,
n gin trong vic tnh ton m ta b qua khng tnh n thi gian cn thit thc hin tng lnh
trong chng trnh, ch quan tm n thi gian thc hin ca lnh DJNZ (2TTimer) v s ln thc hin
ca n. Cng thc trnh by trn (1) ch l cng thc tnh thi gian tDelay c chnh xc tng i,
mun tnh thi gian tDelay chnh xc th ta cn phi tnh tng thi gian thc hin (ngha l tnh s chu k
my hay s chu k Timer) ca tt c cc lnh c trong chng trnh. chnh xc ca chng trnh to
thi gian tr theo phng php tnh tng i ny ph thuc vo s ln lp li v s vng lp.
Vi tDelay = 100 s, fOsc = 12 MHz th tDelay chnh xc l:
Gio trnh Vi x l.
Delay (cx)
= 1.T
+ 2.T
50 + 2.T
= 103.T
Timer
Timer
Timer
Timer
139
Vi tDelay = 10 ms, fOsc = 12 MHz th tDelay chnh xc l:

t
Delay ( cx )
= 1.T
+ 1.T
+ 2.T
250 + 2.T
Timer Timer
Timer
Timer
20 + 2.T
= 10065 .T
Timer
Timer
Vi tDelay = 1 s, fOsc = 12 MHz th tDelay chnh xc l:

t
Delay (cx )
200 + 2.T
= 1.T
+ 1.T
+ 1.T
+ 2.T
250 + 2.T
Timer Timer Timer
Timer
Timer
Timer
= 1006033 .T
Timer
10 + 2.T
Timer

Vit chng trnh con to thi gian tr 100 s dng Timer 0. Bit rng tn s thch anh l 12
MHz.
Gii
Tnh ton: Tm gi tr cn np cho b nh thi v ch hot ng ca b nh thi ny:
= 12 (MHz )
Theo bi ta c: t
= 100 (s ) v f
Osc
Delay
Gi tr cn np cho b nh thi c tnh theo cng thc:
f
12.106
=
100.10 6 = 100
N = Osc t
Delay
12
12
Vy: N = -100 hoc N = 9CH.
t
= 100 (s )
Ta c:
Delay
1
12
12
TTimer =
=
=
=106 (s )=1 (s )
fTimer fOsc 12.106
256.T
(hay N nm trong khong t -255 n -1) nn ta c th chn Timer
V t
Timer
Delay
ch 1 (ch 16 bit) hoc ch 2 (ch 8 bit t ng np li).
Chng trnh con hon chnh khi s dng Timer 0 ch 2:
DELAY:
MOV TMOD, #02H
MOV TH0, #(-100) hoc MOV TH0, #9CH
SETB TR0
JNB TF0, $
CLR TF0
CLR TR0
RET
DELAY:
MOV TMOD, #01H
MOV TH0, #HIGH(-100) hoc MOV TH0, #0FFH
MOV TL0, #LOW(-100)
hoc MOV TL0, #9CH
SETB TR0
JNB TF0, $
CLR TF0
CLR TR0
RET
Gio trnh Vi x l.
140
chnh xc (xt v mt thi gian) ca chng trnh: Khi s dng phng php to thi gian
tr nh trn (phng php dng Timer) th vic nh thi gian cng xut hin mt sai s. V y,
n gin trong vic tnh ton m ta b qua khng tnh n thi gian cn thit thc hin tng lnh
trong chng trnh, ch quan tm n gi tr cn phi np cho b nh thi sao cho Timer nh c
khong thi gian m ta yu cu. chnh xc ca chng trnh nh thi khi s dng phng php ny
khng ph thuc vo gi tr cn np cho Timer (N) m n ch ph thuc vo s lng lnh s dng
trong chng trnh.
Vi dng th nht (ch 2) th tDelay chnh xc l: t
Vi dng th hai (ch 1) th tDelay chnh xc l: t
Delay(cx)
Delay(cx)
= 11.T
+t
= 111(s )
Timer Delay
= 13.T
+t
= 113(s )
Timer Delay

Vit chng trnh con to thi gian tr 10 ms dng Timer 1. Bit rng tn s thch anh l 12
MHz.
Gii
= 10 (ms) v f
= 12 (MHz )
Theo bi ta c: t
Osc
Delay
f
12.106
=
10.103 = 10000
N = Osc t
Delay
12
12
Vy: N = -10000 hoc N = D8F0H.
t
= 10 (ms ) = 10000 (s )
Ta c:
Delay
1
12
12
=
=
=
= 106 (s ) = 1(s )
T
Timer f
6
f
Timer
Osc 12.10
V t
65536.T
(hay N nm trong khong t -65535 n -1) nn ta chn Timer
Timer
Delay
ch 1 (ch 16 bit).

DELAY:
MOV TMOD, #10H
MOV TH1, #HIGH(-10000) hoc MOV TH1, #0D8H
MOV TL1, #LOW(-10000) hoc MOV TL1, #0F0H
SETB TR1
JNB TF1, $
CLR TF1
CLR TR1
RET
chnh xc (xt v mt thi gian) ca chng trnh:
Vi v d trn (ch 1) th tDelay chnh xc l: t
Gio trnh Vi x l.
Delay (cx)
141
= 13.T
+t
= 10013(s )
Timer Delay

Vit chng trnh con to thi gian tr 1s dng Timer 1. Bit rng tn s thch anh l 12 MHz.
Gii

Theo bi ta c:
t
= 1 (s ) v f
= 12 (MHz )
Osc
Delay
f
12.10 6
=
1 = 1000000
N = Osc t
Delay
12
12
Vy: N = -1000000 (gi tr qu ln khng th np trc tip vo cc thanh ghi THx/TLx).
Ta c:
t
= 1(s ) = 1000000 (s )
Delay
1
12
12
=
=
=106 (s )=1(s )
TTimer =
6
fTimer fOsc 12.10
nn ta chn phi Timer ch 1 (ch 16 bit) kt hp vi cc
V t
> 65536.T
Timer
Delay
thanh ghi to vng lp.
Gi:
N l gi tr cn np cho cc thanh ghi nh thi.
[Rn] l gi tr cn np cho thanh ghi kt hp (vng lp).
N = [Rn] x N
Ta t chn: N = -10000 [Rn] = 100

o Lu :
N' c chn sao cho ph hp vi qui nh chn gi tr cn np cho cc thanh ghi
nh thi ch 1.
[Rn] 255, c bit nu chn [Rn] = 0 th iu ny s tng ng vi trng
hp ta chn [Rn] = 256.
Gi tr cn np cho cc thanh ghi nh thi l -10000 v gi tr cn np cho thanh ghi kt hp

l 100.
DELAY:
PUSH 00H
MOV TMOD, #10H
MOV R0, #100
AAA:
SETB TR1
JNB TF1, $
CLR TF1
CLR TR1
DJNZ R0, AAA
POP 00H
RET
Gio trnh Vi x l.
142
chnh xc (xt v mt thi gian) ca chng trnh: Trng hp ny cng tng t nh cc

trng hp nh thi s dng Timer nu cc v d trn. Tuy nhin y, chnh xc ca chng
trnh nh thi khi s dng phng php ny khng ph thuc vo gi tr cn np cho Timer (N) m n
ph thuc vo s lng lnh s dng trong chng trnh, s ln lp li v s vng lp .
Vi v d trn (ch 1 + vng lp) th tDelay chnh xc l:
= 5.T
+ 11.T
+t
100 + 4.T
Delay (cx)
Timer
Timer
Timer Delay (Timer )
= 1001109(s ) = 1,001109(s )
Vi tDelay(Timer): thi gian nh thi ca Timer (10000 s).

Vit chng trnh con to thi gian tr 60s dng Timer 0. Bit rng tn s thch anh l 12 MHz.
Gii

Theo bi ta c:
= 12 (MHz )
t
= 60 (s ) v f
Osc
Delay
f
12.106
Osc
t
=
60 = 60000000
N =
Delay
12
12
Vy: N = -60000000 (gi tr qu ln khng th np trc tip vo cc thanh ghi THx/TLx).
Ta c:
t
= 60 (s ) = 60000000 (s )
Delay
1
12
12
T
=
=
=
= 106 (s ) = 1(s )
Timer f
6
f
Timer
Osc 12.10
nn ta chn phi Timer ch 1 (ch 16 bit) kt hp vi cc
V t
> 65536.T
Timer
Delay
thanh ghi to vng lp.
Gi:
N l gi tr cn np cho cc thanh ghi nh thi.
[Rn] l gi tr cn np cho thanh ghi kt hp (vng lp 1).
[Rm] l gi tr cn np cho thanh ghi kt hp (vng lp 2).
N = [Rn] x [Rm] x N
Ta t chn: N = -10000 [Rm] = 100 [Rn] = 60

o Lu :
N' c chn sao cho ph hp vi qui nh chn gi tr cn np cho cc thanh ghi
nh thi ch 1.
[Rn], [Rm] 255, c bit nu chn [Rn], [Rm] = 0 th iu ny s tng ng
vi trng hp ta chn [Rn], [Rm] = 256.
Gi tr cn np cho cc thanh ghi nh thi l -10000 v gi tr cn np cho cc thanh ghi kt

hp l 60 (cho vng lp 1), 100 (cho vng lp 2).
Gio trnh Vi x l.
143

DELAY:
PUSH 00H
PUSH 01H
MOV TMOD, #01H
MOV R0, #60
AAA:
MOV R1, #100
BBB:
SETB TR0
JNB TF0, $
CLR TF0
CLR TR0
DJNZ R1, BBB
DJNZ R0, AAA
POP 01H
POP 00H
RET
chnh xc (xt v mt thi gian) ca chng trnh: Trng hp ny cng tng t nh cc
trng hp nh thi s dng Timer nu cc v d trn. Tuy nhin y, chnh xc ca chng
trnh nh thi khi s dng phng php ny khng ph thuc vo gi tr cn np cho Timer (N) m n
ph thuc vo s lng lnh s dng trong chng trnh, s ln lp li v s vng lp .
Vi v d trn (ch 1 + vng lp) th tDelay chnh xc l:
100 + 2.T
= 7.T
+ 1.T
+ 11.T
+t
60 + 6.T
Delay(cx)
Timer Timer
Timer Delay(Timer )
Timer
Timer
= 60066193(s ) = 60,066193(s )
Vi tDelay(Timer): thi gian nh thi ca Timer (10000 s).
7. V d 7: (To sng vung)

Vit chng trnh to sng vung c tn s 10 KHz ng ra P1.0 v c chu k lm vic
D=50%. Bit rng tn s thch anh l 12 MHz v s dng b nh thi 0.
Gii
Tnh ton:
Gio trnh Vi x l.
144
Theo bi, ta c chu k lm vic D=50% cho nn:

1
1
= 5.10 5 (s ) = 50(s )
t = 50% T = 50% = 0,5
H
3
f
10.10
tH = 50 (s) v tL = 50 (s).
Vy y ta phi dng Timer 0 to thi gian tr 50(s) cho thi gian sng mc cao v
50(s) cho thi gian sng mc thp.
Theo nh trn, ta c:
t
= 50 (s ) v f
= 12 (MHz )
Osc
Delay
f
12.106
=
50.106 = 50
N = Osc t
Delay
12
12
Vy: N = -50 hoc N = CEH.
Ta c:
t
= 50(s )
Delay
1
12
12
T
=
=
=
= 106 (s ) = 1(s )
Timer f
6
f
Timer
Osc 12.10
(hay N nm trong khong t -255 n -1) nn ta c th chn Timer
V t
256.T
Timer
Delay
ch 1 (ch 16 bit) hoc ch 2 (ch 8 bit t ng np li).
MAIN:
SETB P1.0
ACALL DELAY50US
CLR P1.0
ACALL DELAY50US
SJMP MAIN
DELAY50US:
MOV TMOD , #02H
MOV TH0, #(-50) hoc MOV TH0, #0CEH
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
END
Gio trnh Vi x l.
145

Vit chng trnh to sng vung c tn s 1 KHz ng ra P1.0 v c chu k lm vic D=50%.
Bit rng tn s thch anh l 12 MHz v s dng b nh thi 0.
Gii
Tnh ton:
8051
f = 1 KHz
P1.0
50% 50%
fOSC=12 MHz
tH
tL
T

1
1
t = 50% T = 50% = 0,5
= 5.10 4 (s ) = 500(s )
H
3
f
1.10
tH = 500 (s) v tL = 500 (s).
Theo nh trn, ta c:
t
= 500 (s ) v f
= 12 (MHz )
Osc
Delay
f
12.106
=
500.106 = 500
N = Osc t
Delay
12
12
Vy: N = -500 hoc N = FE0CH.
t
= 500 (s )
Ta c:
Delay
1
12
12
T
=
=
=
= 106 (s ) = 1(s )
Timer f
6
f
Timer
Osc 12.10
V t
65536.T
(hay N nm trong khong t -65535 n -1) nn ta chn Timer ch
Timer
Delay
1 (ch 16 bit).
MAIN:
SETB P1.0
ACALL DELAY500US
CLR P1.0
ACALL DELAY500US
SJMP MAIN
DELAY500US:
MOV TMOD , #01H
MOV TH0, #HIGH(-500) hoc MOV TH0, #0FEH
MOV TL0, #LOW(-500) hoc MOV TL0, #0CH
Gio trnh Vi x l.
146
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
END
Vit chng trnh to sng vung c tn s 100 Hz ng ra P1.0 v c chu k lm vic D=30%.
Bit rng tn s thch anh l 12 MHz v s dng b nh thi 0.
Gii
Tnh ton:
8051
f = 100 Hz
P1.0
30% 70%
fOSC=12 MHz
tH
tL
T

1
1
t = 30% T = 30% = 0,3
= 3.10 3 (s ) = 3000(s )
H
f
100
tH = 3000 (s) v tL = 7000 (s).
Theo nh trn, ta c (xt trng hp tH):
t
= 3000 (s ) v f
= 12 (MHz )
Osc
Delay
f
12.106
=
3000.106 = 3000
N = Osc t
Delay
12
12
Vy: N = -3000 hoc N = F448H.
Ta c:
t
= 3000 (s )
Delay
1
12
12
T
=
=
=
= 106 (s ) = 1(s )
Timer f
6
f
Timer
Osc 12.10
V t
65536.T
Timer
Delay
1 (ch 16 bit).
Tng t nh trn, ta c (xt trng hp tL):
= 12 (MHz )
t
= 7000 (s ) v f
Osc
Delay
Gio trnh Vi x l.
147

f
12.106
Osc
t
=
7000.106 = 7000
N =
Delay
12
12
Vy: N = -7000 hoc N = E4A8H.
Ta c:
t
= 7000 (s )
Delay
1
12
12
T
=
=
=
= 106 (s ) = 1(s )
Timer f
6
f
Timer
Osc 12.10
65536.T
V t
Timer
Delay
1 (ch 16 bit).
MAIN:
SETB P1.0
ACALL DELAY3000US
CLR P1.0
ACALL DELAY7000US
SJMP MAIN
DELAY3000US:
MOV TMOD , #01H
MOV TH0, #HIGH(-3000) hoc
MOV TL0, #LOW(-3000) hoc
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
DELAY7000US:
MOV TMOD , #01H
MOV TH0, #HIGH(-7000) hoc
MOV TL0, #LOW(-7000) hoc
SETB TR0
JNB TF0, $
CLR TR0
CLR TF0
RET
END
Gio trnh Vi x l.
148
MOV TH0, #0F4H

MOV TL0, #48H
MOV TH0, #0E4H

MOV TL0, #0A8H
10. V d 10: (Giao tip vi thit b ngoi vi)

Mt ci c ni vi chn P1.7 v mt chuyn mch (c chng di) c ni vi chn P1.6 ca
chip 8051 (xem trong hnh v). Vit chng trnh iu khin c mc logic cung cp bi chuyn mch
(khi chuyn mch thay i t v tr trn xung v tr di th mt xung mc thp c to ra ti chn
P1.6) v h ci trong thi gian 1sec sau mi ln pht hin s chuyn trng thi t 1 xung 0 ti chn
P1.6.
Vcc
Vcc
8051
10K
SW
Vcc
P1.6
P1.7
P1.7=0 Hu coi.
P1.7=1 Im lang.
10K
fOSC=12 MHz
Gii
HUNDRED
EQU 100
;Khai bo bin
COUNT
EQU -10000
ORG 0000H
MAIN:
;Ch logic 1 ng vo P1.6.
JNB P1.6, $
JB P1.6, $
;Ch logic 0 ng vo P1.6
SETB P1.7
;Ci h.
ACALL DELAY
;Thi gian 1 giy.
CLR P1.7
;Tt ci.
SJMP MAIN
DELAY:
PUSH 00H
MOV TMOD, #10H
MOV R0, # HUNDRED
AAA:
MOV TH1, #HIGH(COUNT)
MOV TL1, #LOW(COUNT)
SETB TR1
JNB TF1, $
CLR TF1
CLR TR1
DJNZ R0, AAA
POP 00H
RET
END
Gio trnh Vi x l.
149
11. V d 11: (m xung)

Mt chuyn mch (c chng di) c ni vi chn T0 (P3.4) ca chip 8051. Vit chng trnh
iu khin m s lng xung c to ra bi chuyn mch (khi chuyn mch thay i t v tr (1)
sang v tr (2) th mt xung mc thp c to ra ti chn T0). S xung m c s cha trong RAM
ni (dng s HEX) ti cc nh c a ch bt u ti 40H. Bit rng s lng xung to ra c
khng ch nm trong khong 0 255 xung.
Gii
Tnh ton:
Theo yu cu ca bi:
o Vit chng trnh m xung Cu hnh cho Timer 0 l mt b m xung (Counter).
o S xung nm trong khong 0 255 xung Chn ch 8 bit (ch 2).
MAIN:
;Ch Counter 8 bit (ch 2).
MOV
TMOD, #06H
MOV
TH0, #00H
;Gi tr ban u ca b m.
SETB
P3.4
;Cu hnh P3.4 l ng vo.
SETB
TR0
;Khi ng b m.
LOOP:
;c s xung t b m.
MOV
A, TL0
MOV
40H, A
;Ct s xung m c vo 40H.
JNB
TF0, LOOP
;Tip tc qu trnh m xung nu
;b m cha b trn.
CLR
TF0
;Xo c trn.
CLR
TR0
;Dng b m.
END
;Kt thc chng trnh.
Gio trnh Vi x l.
150
12. V d 12: (m xung)

Mt chuyn mch (c chng di) c ni vi chn T0 (P3.4) ca chip 8051. Vit chng trnh
iu khin m s lng xung c to ra bi chuyn mch (khi chuyn mch thay i t v tr (1)
sang v tr (2) th mt xung mc thp c to ra ti chn T0). S xung m c s cha trong RAM
ni (dng s HEX) ti cc nh c a ch bt u ti 50H. Bit rng s lng xung to ra c
khng ch nm trong khong 0 65535 xung.
Gii
Tnh ton:
Theo yu cu ca bi:
o Vit chng trnh m xung Cu hnh cho Timer 0 l mt b m xung (Counter).
o S xung nm trong khong 0 65535 xung Chn ch 16 bit (ch 1).
MAIN:
MOV
TMOD, #05H
;Ch Counter 16 bit (ch 1).
MOV
TH0, #00H
;Gi tr ban u ca b m (cao).
MOV
TL0, #00H
;Gi tr ban u ca b m (thp).
SETB
P3.4
;Cu hnh P3.4 l ng vo.
SETB
TR0
;Khi ng b m.
LOOP:
;c gi tr ca b m ang hot ng.
MOV
A, TH0
;c s xung m c (phn cao).
MOV
50H, TL0
;Ct s xung m c (phn thp).
;c s xung m c (phn cao)
CJNE
A, TH0, LOOP
;ln na kim tra.
MOV
51H, A
;Ct s xung m c (phn cao).
JNB
TF0, LOOP
;Tip tc qu trnh m xung nu
;b m cha b trn.
CLR
TF0
;Xo c trn.
CLR
TR0
;Dng b m.
END
;Kt thc chng trnh.
Gio trnh Vi x l.
151
XI. PHN BI TP:
To tr:
Bi 1: Vit chng trnh con mang tn DELAY500US c nhim v to tr 0,5ms dng Timer.
(fOSC=6MHz).
Bi 2: Vit chng trnh con mang tn DELAY10MS c nhim v to tr 10ms dng Timer.
(fOSC=12MHz).
Bi 3: Vit chng trnh con mang tn DELAY10S c nhim v to tr 10s dng Timer.
(fOSC=12MHz).
Bi 4: Vit chng trnh con mang tn DELAY1S c nhim v to tr 1s dng Timer.
(fOSC=11,0592MHz).
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
Bi 6: Vit chng trnh con delay 100ms, bit rng fOSC dng trong h thng l:
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
a. 6 MHz.
b. 11,0592 MHz.
c. 12 MHz.
d. 24 MHz
Bi 8: Vit on lnh to mt xung dng (
rng fOSC =12 MHz.
) ti chn P1.0 vi rng xung 1ms, bit
To xung:
Bi 1: Dng chng trnh con DELAY500US (Bi 1 phn to tr) vit on lnh to sng
vung f=1KHz ti P1.0.
Bi 2: Dng chng trnh con DELAY10MS (Bi 2 phn to tr) vit on lnh to sng
vung f=50Hz ti P1.1.
Bi 3: Dng chng trnh con DELAY500US (Bi 1 phn to tr) vit on lnh to sng
vung f=500Hz (D=25%) ti P1.2.
Bi 4: Dng chng trnh con DELAY10MS (Bi 2 phn to tr) vit on lnh to sng
vung f=20Hz (D=20%) ti P1.3.
Gio trnh Vi x l.
152

Bi 9: Vit on lnh to chui xung vung c f = 10 Hz ti chn P1.4 (fOSC =12 MHz).
Bi 10: Vit on lnh to chui xung vung c f = 10 Hz v c chu k lm vic D = 25% ti
chn P1.5 (fOSC =11,0592 MHz).
Bi 11: Vit on lnh dng Timer to sng vung f=500Hz ti P1.4. (fOSC=12MHz).
Bi 12: Vit on lnh dng Timer to sng vung f=20KHz ti P1.5. (fOSC=24MHz).
Bi 13: Vit on lnh dng Timer to 2 sng vung c cng f=1KHz ti P1.6 v P1.7. Bit
rng sng vung ti P1.7 chm pha hn sng vung ti P1.6 l 100s. (fOSC=12MHz).
Bi 14: Vit on lnh dng Timer iu khin n giao thng ti mt giao l. Cho bit rng:
n
Bit iu khin
Thi gian
Xanh 1
P1.0
25s
Vng 1
P1.1
3s
P1.2
Xanh 2
P1.3
33s
Vng 2
P1.4
3s
P1.5
n sng khi bit iu khin bng 0 (fOSC=12MHz).
Gio trnh Vi x l.
153
Chng 5: Hot ng ca port ni tip (Serial Port).
CHNG 5
HOT NG CA PORT NI TIP
(SERIAL PORT)
I. M U:
My tnh truyn d liu theo hai phng php: truyn d liu song song v truyn d liu ni
tip.
Truyn song song: S dng nhiu dy dn truyn d liu gia cc thit b c khong cch
gn nhau (khong vi mt). Phng php ny cho php truyn d liu vi tc cao nh s dng
nhiu dy dn truyn d liu ng thi nn ti mt thi im c th truyn c nhiu bit thng tin
nhng khong cch truyn th c nhiu hn ch.
Truyn ni tip: S dng mt dy dn truyn d liu (mt dy pht i v mt dy thu v)
gia cc thit b c khong cch xa nhau (khong vi trm mt tr ln). Phng php ny s truyn d
liu vi tc chm hn (so vi phng php truyn song song) v ch s dng mt dy dn truyn
d liu nn ti mt thi im ch c th truyn c mt bit thng tin nhng khong cch truyn th
khng b hn ch nh phng php song song.
Chip 8051 c mt port ni tip (serial port) vi cc tnh nng nh sau:
Lu : trng hp c trng th hai th d liu th nht s khng b mt nu CPU c xong

d liu th nht trc khi d liu th hai c nhn y .
Cc thanh ghi chc nng c bit ca port ni tip:
i lng c trng cho tc truyn d liu nhanh hay chm l tc baud (baud rate) hay
cn gi l tn s hot ng ca port ni tip c th l gi tr c nh hay thay i ty theo yu cu ca
ngi lp trnh. Khi ch tc baud thay i c s dng, b nh thi 1 cung cp xung clock tc
baud v ta phi lp trnh sao cho ph hp. phin bn chip 8031/8052, b nh thi 2 cng c th
c lp trnh cung cp xung clock tc baud.
Gio trnh Vi x l.
154
II. THANH GHI M PORT NI TIP (SBUF):

Thanh ghi SBUF (Serial Buffer Register): c dng lu gi d liu cn pht i v d liu
nhn c. Vic ghi d liu vo thanh ghi SBUF s np d liu pht i v vic c d liu t thanh
ghi SBUF s truy xut d liu thu c.
Thanh ghi SBUF bao gm 2 thanh ghi:
Thanh ghi pht (b m pht): dng lu gi d liu cn pht i.
Thanh ghi thu (b m thu): dng lu gi d liu nhn c.
Cu trc ca thanh ghi SBUF:
V d: Cc lnh ghi d liu vo SBUF v c d liu t SBUF.

MOV
SBUF, #45H
;Pht gi tr 45H qua port ni tip.
MOV
SBUF, #D
;Pht gi tr 44H qua port ni tip.
MOV
SBUF, A
;Pht ni dung ca A qua port ni tip.
MOV
A, SBUF
;c d liu thu c t port ni tip.
Gio trnh Vi x l.
155
III. THANH GHI IU KHIN PORT NI TIP (SCON):

Thanh ghi SCON (Serial Control Register): cha cc bit dng iu khin ch hot ng
v bo trng thi ca port ni tip.
Cu trc ca thanh ghi SCON:
Bit
7
SCON: Serial Control Register

9F 9E 9D 9C 9B 9A 99 98
SM1
REN
RB8
RI
SM0
SM2
TB8
TI
a ch bit (HEX)
Ky hieu
RI: Receive Interrupt C ngat thu. RI = 1 ngay khi ket

thuc viec thu mot d lieu, RI c xoa bi phan mem.
TI: Transmit Interrupt C ngat phat. TI = 1 ngay khi ket
thuc viec phat mot d lieu, TI c xoa bi phan mem.
RB8: Receive bit 8
Bit th 9 nhan c (che o 2 va 3).
TB8: Transmit bit 8

Bit th 9 c phat (che o 2 va 3).
Bit nay c set (1) hoac xoa (0) bi phan mem.
REN: Receive Enable
e nhan cac d lieu.
Cho phep thu. Bit nay phai c set
SM2: Serial Mode 2 Bit 2 chon che o cua port noi tiep.
Bit nay cho phep truyen thong a x ly che o 2 va 3; bit
RI se khong c tch cc neu bit th 9 nhan c la 0.
SM1: Serial Mode 1
Bit 1 chon che o cua port noi tiep.
SM0: Serial Mode 0
Bit 0 chon che o cua port noi tiep.
Cc ch ca port ni tip:
Trc khi s dng port ni tip cn phi:
Gio trnh Vi x l.
156
V d: Khi ng port ni tip ch 1, cho php port thu d liu t chn RxD v sn sng pht d
liu t chn TxD.
Gii
Ta dng lnh:
MOV SCON, #52H
Gii thch:
SM0 = 0, SM1 = 1 cho php port hot ng ch 1.

REN = 1 cho php port ni tip c php thu d liu.
TI = 1 chun b port ni tip sn sng pht d liu qua chn TxD.
RI = 0 chun b port ni tip sn sng thu d liu qua chn RxD.
IV. CC CH HOT NG CA PORT NI TIP:
1. Ch 0 Thanh ghi dch 8 bit:
Qu trnh pht d liu:

Qu trnh khi ng: Ghi d liu cn pht vo SBUF Vic pht d liu bt u: D liu t
SBUF c dch ra chn RxD ng thi vi cc xung clock dch bit c gi ra chn TxD (mi
bit c truyn i trn chn RxD trong 1 chu k my).
Gio trnh Vi x l.
ri t
e
157
Gin thi gian pht d liu:
Qu trnh thu d liu:

Qu trnh khi ng: Set bit cho php thu (REN=1) Xa c ngt thu (RI=0) Vic thu d
liu bt u: Cc xung clock dch bit c gi ra chn TxD v d liu t thit b bn ngoi
c dch vo chn RxD bi cc xung clock dch bit ny (vic dch d liu vo chn RxD xy ra
cnh ln ca xung clock dch bit).
Gin thi gian thu d liu:
ng dng: Mt ng dng kh thi ca ch 0 (ch thanh ghi dch bit) l m rng thm cc ng ra
cho chip 8051. Mt vi mch thanh ghi dch ni tip song song c th c ni vi cc chn TxD v
RxD ca chip 8051 cung cp thm 8 ng xut (xem hnh v bn di). Cc thanh ghi dch bit
khc c th ghp cascade vi thanh ghi dch bit u tin m rng thm na.
Gio trnh Vi x l.
158

8051
Data
A1H
W
Shift register: Thanh ghi dch bit.

8 extra outputs: 8 ngo ra m rong.
8 Extra outputs
ri t
e
D7
SBUF 10100001B
RxD
Serial port
D0
Shift Register
Data
DATA
10100001
SHIFT CLOCK
Clock
TxD
Che o thanh ghi dch bit cua port noi tiep.
2. Ch 1 UART 8 bit c tc baud thay i:

Trong ch 1, port ni tip ca 8051 hot ng nh mt b thu pht khng ng b 8 bit c
tc baud thay i (UART - Universal Asynchronous Receiver Transmitter).
UART l mt b thu pht d liu ni tip vi mi k t d liu c ng trc bi mt bit

START (logic 0) v c ng sau bi mt bit STOP (logic 1). Thnh thong, mt bit chn l (Parity
bit) c chn vo gia bit d liu sau cng v bit stop. Hot ng ch yu ca UART l bin i d
liu pht t song song thnh ni tip v bin i d liu thu t ni tip thnh song song.
Hnh v khung dng d liu khi c s dng ch UART:
[1]
[0]
D0
START
BIT
(Mc 0)
D1
D2
D3
D4
DATA BIT
D5
D6
D7
Bit nay co the

co hoac khong
co tuy theo yeu
cau s dung
PARITY STOP
BIT
BIT
(Mc 1)
Khung dng ca mt d liu khi s dng ch UART 8 bit:
Gio trnh Vi x l.
159
Qu trnh pht d liu:

Qu trnh khi ng: Ghi d liu cn pht vo SBUF Vic pht d liu bt u: D liu t
SBUF c dch ra chn TxD (theo th t: Start bit 8 bit data (D0 .. D7) Stop bit) c
TI=1.
rit
e
Tc baud: do ngi lp trnh thit lp v c qui nh bi tc trn ca Timer 1.

Thi gian ca 1 bit trn ng truyn: bng nghch o ca tc baud (1 / Baud rate).
C ngt pht TI = 1: khi bit stop c xut hin trn chn TxD.
Qa trnh thu d liu:
Qu trnh khi ng: Mt s chuyn trng thi t mc 1 xung mc 0 ti chn RxD (tc xut
hin bit Start) Vic thu d liu bt u: 8 bit d liu c dch vo trong SBUF (theo th t:
D0D1D7) Stop bit (bit th 9) c a vo bit RB8 (thuc thanh ghi SCON) c
RI=1.
Tc baud: do ngi lp trnh thit lp v c qui nh bi tc trn ca Timer 1.

Hai iu kin bt buc thc hin qu trnh thu d liu nh trn:
o RI = 0 Yu cu ny c ngha l chip 8051 c xong d liu trc v xo c RI..
o (SM2 = 1 v Stop bit = 1) hoc SM2 = 0 ch p dng trong ch truyn thng a x
l. Yu cu ny c ngha l khng set c RI bng 1 trong ch truyn thng a x l
khi bit d liu th 9 l 0.
C ngt thu RI = 1: khi 8 bit d liu c np vo SBUF.
Lu : Trng hp cc tn hiu nhiu xut hin trn ng truyn (lm cho ng truyn xut hin
mc thp) dn n lm cho b thu nhn dng sai, cho l s xut hin ca START bit (logic 0) v
tin hnh thc hin qu trnh thu d liu, t dn n kt qu nhn vo s khng ng. trnh iu
ny xy ra th khi ng truyn c s chuyn trng thi t 1 xung 0, b thu yu cu mc 0 ny phi
Gio trnh Vi x l.
160
c duy tr trn ng truyn trong mt khong thi gian xc nh. Nu khng m bo c nh

th, b thu c gi s rng nhn c nhiu thay v nhn c START bit hp l. Lc b thu s
c thit lp li, quay v trng thi ngh v ch s chuyn trng thi t 1 xung 0 k tip trn ng
truyn.
3. Ch 2 UART 9 bit c tc baud c nh:
(Tng t nh UART 8 bit, ch khc s bit d liu l 9 bit)
4. Ch 3 UART 9 bit c tc baud thay i:

(Tng t nh UART 9 bit, ch khc tc baud c th thay i)
Gio trnh Vi x l.
161
Recei
Trans
Receive
Transmit
V. KHI NG V TRUY XUT CC THANH GHI:

1. Bit cho php thu (nhn) d liu (REN: Receive Enable):
Cng dng: dng cho php (hoc khng cho php) nhn cc k t d liu.
REN = 1: Cho php nhn d liu lnh thc hin: SETB REN
REN = 0: Khng cho php d liu lnh thc hin: CLR REN
2. Bit d liu th 9:
Cng dng: ty thuc vo c tnh k thut ca thit b ni tip m c th yu cu hoc khng
yu cu bit d liu th 9.
Khi pht d liu: bit d liu th 9 phi c np vo bit TB8 ca SCON trc khi pht i.
Khi thu d liu: bit d liu th 9 s c np vo bit RB8 ca SCON sau khi thu xong.
3. Bit kim tra chn / l (P: Parity):
Cng dng: Trong chip 8051 th bit Parity c dng thit lp vic kim tra chn cho 8 bit
d liu cha trong thanh ghi A (thng dng kim tra li khi truyn d liu).
P = 1 S lng bit 1 trong thanh ghi A l s l.
P = 0 S lng bit 1 trong thanh ghi A l s chn.
hoc
S lng bit 1 trong thanh ghi A v bit P l mt s chn.
ch 1 (UART 8 bit) th bit chn/l do chip 8051 to ra c th c thm vo ti bit th 8
(v tr D7) v khi ta ch c th truyn d liu ch c 7 bit.
Gio trnh Vi x l.
162
ch 2, 3 (UART 9 bit) th bit chn/l do chip 8051 to ra c th c thm vo ti bit th 9

(ngha l thm vo bit TB8 ca SCON) v khi ta c th truyn d liu c 8 bit.
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY
STOP
Bit th 9
DATA (8 bit)
V d: Truyn d liu (ch 2, 3 UART 9 bit) cha trong thanh ghi A thng qua port ni tip vi
yu cu truyn 8 bit d liu + 1 bit kim tra chn (bit P).
Chui lnh thc hin:
MOV
C, P
;Chuyn bit kim tra chn (bit P) vo TB8 v
MOV
TB8, C
;bit ny tr thnh bit th 9.
MOV
SBUF, A
;Truyn 8 bit d liu trong A thng qua port.
V d: Truyn d liu (ch 2, 3 UART 9 bit) cha trong thanh ghi A thng qua port ni tip vi
yu cu truyn 8 bit d liu + 1 bit kim tra l (ly b bit P).
Chui lnh thc hin:
MOV
C, P
;Bin i bit kim tra chn (bit P) thnh bit
CPL
C
;kim tra l, chuyn bit kim tra l vo TB8 v
MOV
TB8, C
;bit ny tr thnh bit th 9.
MOV
SBUF, A
;Truyn 8 bit d liu trong A thng qua port.
V d: Truyn d liu (ch 1 UART 8 bit) cha trong thanh ghi A thng qua port ni tip vi yu
cu truyn 7 bit d liu + 1 bit kim tra chn (bit P).
Chui lnh thc hin:
CLR
ACC.7
MOV
C, P
MOV
ACC.7, C
MOV
SBUF, A
;Xo bit th 8 (D7) trong thanh ghi A.

;Sao chp bit kim tra chn vo C.
;t bit kim tra chn vo bit th 8 trong A.
;Truyn 7 bit d liu cng bit kim tra chn.
4. Cc c ngt ca port ni tip:
T phn trnh by trn y, ta c th thy rng:
Thng qua vic kim tra c ngt TI c th bit c chip 8051 sn sng truyn mt
byte d liu hay cha. Cn ch rng, y c TI c t (TI = 1) khi 8051 hon tt vic truyn
mt byte d liu, cn c xo (TI=0) th phi do ngi lp trnh thc hin bng lnh (CLR TI). Cng
nn nh rng, nu ghi mt byte vo thanh ghi SBUF trc khi c TI c t (TI = 1) th s c nguy
c b mt phn d liu trc do cha kp truyn i. C TI c th c kim tra bng lnh (JNB
TI,) hoc s dng phng php ngt (s c trnh by trong chng tip theo).
Gio trnh Vi x l.
163
Thng qua vic kim tra c ngt RI c th bit c chip 8051 nhn xong mt byte d
liu hay cha. Cn ch rng, y c RI c t (RI = 1) khi 8051 hon tt vic nhn mt byte
d liu, cn c xo (RI=0) th phi do ngi lp trnh thc hin bng lnh (CLR RI). Cng nn nh
rng, nu khng tin hnh ct ni dung ca thanh ghi SBUF vo ni an ton th s c nguy c b mt
d liu va nhn c do d liu tip theo c chuyn vo. C RI c th c kim tra bng lnh
(JNB RI,) hoc s dng phng php ngt (s c trnh by trong chng tip theo).
Lu v on lnh kim tra v thu mt d liu ni tip t thit b bn ngoi vo chip 8051
(cha vo A):
Lu v on lnh kim tra v pht mt d liu ni tip t chip 8051 (cha trong A) ra thit b
bn ngoi:
VI. TRUYN THNG A X L:

Cc ch 2 v 3 l cc ch d phng cho vic truyn thng a x l. Trong cc ch ny, 9
bit d liu c thu v bit th 9 a n RB8. Port c th c lp trnh sao cho khi bit stop c
nhn, ngt do port ni tip ch c tch cc nu RB8=1. c trng ny c th c bng cch set bit
SM2 trong thanh ghi SCON bng 1. Mt ng dng cho iu ny l mt mi trng mng s dng
nhiu 8051 c sp xp theo m hnh ch/t (master/slave) nh hnh di y.
Gio trnh Vi x l.
164
Khi b vi x l ch (master) mun truyn mt khi d liu n mt trong nhiu b x l t (slave),

trc tin b vi x l ch pht i mt byte a ch nhn dng b vi x l t ch. Mt byte a ch khc
vi mt byte d liu ch bit th 9 l 1 (i vi byte a ch) v l 0 (i vi byte d liu). Mt byte
a ch ngt tt c cc b vi x l t cho mi mt b vi x l t c th kho st byte nhn c
kim tra xem c phi l b vi x l t ang c nh a ch khng. B vi x l t c nh a ch
s xo bit SM2 ca mnh v chun b nhn cc byte d liu theo sau. Cc b vi x l t khng c
nh a ch c cc bit SM2 ca chng c set bng 1 v thc thi cc cng vic ca ring chng, b
qua khng nhn cc byte d liu. Cc b vi x l ny s c ngt ln na khi b vi x l ch pht tip
byte a ch k. Cc s c th c th c nu ra sao cho mt khi lin kt ch t c thit lp,
b vi x l t cng c th pht n b vi x l ch. Mu mo y l khng s dng bit d liu th 9
sau khi lin kt va c thit lp (ngc li cc b vi x l t khc c th c chn mt cch khng
c ).
SM2 khng nh hng n ch 0, v trong ch 1 th bit ny c th c dng kim tra s
hp l ca bit stop. ch 1 thu, nu SM2 = 1, ngt thu s khng c tch cc tr khi bit stop thu
c l hp l.
VII. TC BAUD CA PORT NI TIP:
1. Tc baud cho ch 0:
Baud rate =
f OSC
12
2. Tc baud cho ch 1, 3:
Baud rate =
Timer I overflow rate

16
Baud rate =
Timer I overflow rate

32
3. Tc baud cho ch 2:
Baud rate =
f OSC
32
Baud rate =
f OSC
64
Lu :
o Sau khi h thng reset th bit SMOD = 0 (ch mc nh).
o V thanh ghi PCON khng c nh a ch tng bit, nn tng gp i tc baud
(tc lm cho SMOD=1) ta phi thc hin bng nhng dng lnh sau:
MOV A, PCON
;Ly gi tr t thanh ghi PCON.
SETB ACC.7
;SMOD = 1.
MOV PCON, A
;Chuyn gi tr mi vo PCON.
Gio trnh Vi x l.
165
4. S dng Timer 1 lm xung clock tc baud cho port ni tip:

K thut to xung clock tc baud bng Timer 1:
V chn ch : thng dng Timer 1 ch 8 bit t ng np li (Mode 2). Cc tc baud rt

chm c th nhn c bng cch s dng ch 16 bit (Mode 1).
V d: Khi ng thanh ghi TMOD dng T1 lm b to xung tc baud (cho T1 hot ng
ch 2):
MOV TMOD, #2xH
x: dnh cho Timer 0
V chn tc baud:
Gi M l gi tr cn np cho thanh ghi TH1 c tc baud nh yu cu, ta c:
f
Timer
M=
Timer 1 overflow rate
f
f
= Timer
Timer
12
M:
Baud rate =
Timer 1 overflow rate

16 (hoac 32)
f
1
M = Osc
12
Baud rate 16 (hoac 32)
Vy ta c:
f
Osc
M=
, ( SMOD = 1) hoc M =
f
Osc
, ( SMOD = 0)
384 Baud rate
MHz.
192 Baud rate

Trong :
fOsc (Hz): tn s thch anh.
Baud rate (bps): tc baud ca port ni tip.
V d: To tc baud l 1200 vi trng hp SMOD = 0 v chip 8051 dng thch anh 12
M=
f
Osc
, ( SMOD = 0)
384 Baud rate

M=
12.10
6
= 26,0416 -26 (lm trn s).
384 1200
Gio trnh Vi x l.
166

Chuyn gi tr ny vo thanh ghi TH1:
MOV TH1, #(-26)
hoc

MOV TH1, #E6H
Ch : Do vic lm trn cho nn s c mt sai s nh trong vic xc nh chnh xc tc baud. Cho

nn c tc baud chnh xc trong vic truyn d liu thng qua port ni tip th ngi ta thng
dng thch anh dao ng c tn s 11,0592 MHz (thay v l 12 MHz).
V d:
6
11,0592.10
M=
= 24 (khng cn phi lm trn s)
384 1200
Bng tnh tc baud cho port ni tip:
VIII. CC BC C BN LP TRNH PORT NI TIP:

Trong cc ch truyn d liu ni tip ca 8051 nu trn th trn thc t s dng, thc hin
vic thu v pht d liu ni tip gia chip 8051 vi cc thit b khc (8051, my tnh, cc thit b
SPI,) thng ngi lp trnh ch s dng hai ch sau : Mode 1 (UART 8 bit c tc baud thay
i) hoc Mode 3 (UART 9 bit c tc baud thay i). Cn hai ch cn li th rt t s dng khi
cn truyn d liu ni tip. Cho nn y chng ta ch xem xt n trnh t thc hin vic lp trnh
(bao gm thao tc khi ng v iu khin thu/pht d liu) 8051 c th truyn (pht) v nhn (thu)
d liu thng qua port ni tip theo hai ch UART nu trn.
1. Lp trnh 8051 truyn (pht) d liu ni tip:

Chn ch hot ng cho port ni tip:
MOV SCON, #...(1)
Chn ch hot ng Timer 1, cho bit GATE=0 v C/T=0:
MOV TMOD, #...(2)
Chn gi tr thch hp (cn c vo tc baud) cho Timer 1:
MOV TH1, #...(3)
Cho Timer 1 chy:
SETB TR1
Kim tra xem pht xong ton b d liu trc hay cha?
JNB TI, $
hoc
WAIT: JNB TI, WAIT
Xo c ngt pht TI (chun b cho ln pht d liu tip theo):
CLR TI
Gio trnh Vi x l.
167
Ghi d liu cn pht vo port ni tip pht i:

MOV SBUF, ...(4)
Quay tr li bc 5 pht mt d liu tip theo.
Lu :
(1): Gi tr dng qui nh ch hot ng ca port ni tip. n gin trong vic lp

trnh, ta c th khi ng thanh ghi SCON theo nh trnh by di y:
Mode 1:
...(1) = 52H
Mode 3:
...(1) = D2H
(2): Gi tr dng qui nh ch hot ng ca Timer 1 (dng to tc baud cho vic

truyn d liu ni tip). n gin trong vic lp trnh, ta c th khi ng thanh ghi TMOD theo
nh trnh by di y (ch yu y ta ch cn s dng Timer 1 Mode 2 Ch 8 bit t ng np
li):
...(2) = 20H
Mode 2:
(3): Gi tr dng qui nh tc baud cho port ni tip. Gi tr ny ph thuc vo tn s

thch anh, bit SMOD v tc baud m ngi lp trnh mong mun (xem thm Bng tnh tc
baud cho port ni tip nh trn trnh by).
...(3) = M
f
Osc
M=
, ( SMOD = 1) hoc M =
f
Osc
, ( SMOD = 0)
384 Baud rate
192 Baud rate
fOsc (Hz): tn s thch anh.

Baud rate (bps): tc baud ca port ni tip.
(4): D liu cn pht i thng qua port ni tip. D liu ny c th l ni dung ca mt nh,
thanh ghi hoc mt gi tr tc thi.
Trong :
Nn nh rng, nu c yu cu th bit gi km theo (v d nh bit Parity) cn phi thm vo

trc khi tin hnh qu trnh pht d liu (Mode 1: km thm vo v tr ca bit D7, Mode 3: km thm
vo v tr ca bit TB8).
Gio trnh Vi x l.
168
2. Lp trnh 8051 nhn (thu) d liu ni tip:

Chn ch hot ng cho port ni tip:
MOV SCON, #...(1)
Chn ch hot ng Timer 1, cho bit GATE=0 v C/T=0:
MOV TMOD, #...(2)
Chn gi tr thch hp (cn c vo tc baud) cho Timer 1:
MOV TH1, #...(3)
Cho Timer 1 chy:
SETB TR1
Kim tra xem thu ton b d liu hay cha?
JNB RI, $
hoc
WAIT: JNB RI, WAIT
Xo c ngt thu RI (chun b cho ln thu d liu tip theo):
CLR RI
Ct d liu va thu c vo ni an ton (trnh b mt d liu):
MOV ...(4), SBUF
Quay tr li bc 5 nhn mt d liu tip theo.
Lu :
(1): Xem thm Lp trnh 8051 truyn (pht) d liu ni tip.
(4): a ch ca mt nh, thanh ghi m d liu thu c t port ni tip s lu gi vo trong
.
Nn nh rng, nu c yu cu th bit gi km theo (v d nh bit Parity) cn phi c x l
trc khi tin hnh vic ct d liu thu c (Mode 1: nm ti v tr ca bit D7, Mode 3: nm ti v tr
ca bit RB8).
IX. CC V D MINH HA:

1. V d 1: (Chn tc baud)
Chip 8051 s dng thch anh 11,0592MHz. Hy xc nh gi tr cn np cho thanh ghi TH1 c
c cc tc baud: 9600, 2400, 1200 (nu SMOD=0) v 19200 (nu SMOD=1).
Gii
Xt trng hp SMOD=0:
M=
f
Osc
384 Baud rate
Baud rate = 9600

M=
11,0592 10
6
= 3 (TH1) = -3 hay (TH1) = FDH.
384 9600
Gio trnh Vi x l.
169
Baud rate = 2400

M=
11,0592 10
6
= 12 (TH1) = -12 hay (TH1) = F4H.
384 2400
Baud rate = 1200
M=
11,0592 10
6
= 24 (TH1) = -24 hay (TH1) = F8H.
384 1200
Xt trng hp SMOD=1:
M=
f
Osc
192 Baud rate
Baud rate = 19200

M=
11,0592 10
6
= 3 (TH1) = -3 hay (TH1) = FDH.
19219200
2. V d 2: (Khi ng port ni tip)

Vit mt chui lnh khi ng port ni tip sao cho port ny hot ng nh mt UART 8 bit vi
tc baud l 2400, s dng Timer1 cung cp xung clock tc baud. Chip 8051 s dng thch
anh 12MHz.
Gii
khi ng port ni tip c cu hnh nh trn ta cn tc ng n cc thanh ghi: SCON, TMOD,
TCON v TH1.
SM0 = 0, SM1 = 1, SM2 = 0 ch UART 8 bit.

REN = 1 cho php port ni tip thu d liu.
TI = 1 cho php port sn sng pht d liu (b m pht rng).
RI = 0 cho php port sn sng thu d liu (b m thu rng).
GATE = 0, C/T = 0, M1 = 1, M0 = 0 Timer 1 ch nh thi 8 bit t np li.
Gio trnh Vi x l.
170
TR1 = 1 cho php Timer 1 hot ng.

f
Osc
M=
( SMOD = 0)
384 Baud rate
M=
12.10
6
= 13,02 -13 (lm trn s).
384 2400
Chuyn gi tr ny vo thanh ghi TH1:

MOV TH1, #(-13)
hoc
MOV TH1, #F3H
Chui lnh khi ng port ni tip c vit nh sau:

MOV SCON, #52H
MOV TMOD, #20H
MOV TH1, #-13
SETB TR1
3. V d 3: (Chng trnh con pht (xut) d liu)

Gi s port ni tip c khi ng (nh v d 1). Hy vit mt chng trnh con pht d
liu (dng 7 bit) cha trong thanh ghi A ra port ni tip vi bit kim tra l l bit th 8. Ch rng, vic
tr v t chng trnh con ny khng c lm thay i ni dung thanh ghi A.
Gii
Ba lnh u tin t bit kim tra l vo bit 7 ca thanh ghi A (ACC.7). Do bit P trong thanh ghi
PSW c thit lp kim tra chn cho gi tr trong thanh ghi A, cho nn bit ny phi c ly b
tr thnh bit kim tra l trc khi t vo ACC.7. Lnh JNB to ra mt vng lp ch kim tra c
ngt pht TI cho n khi c ny c set bng 1. Khi TI=1 (do vic pht k t trc va kt thc),
bit ny s c xa v sau k t trong thanh ghi A c ghi vo b m ca port ni tip SBUF v
Gio trnh Vi x l.
171
vic pht k t c bt u ln trn k ca b m to xung clock cho port ni tip. Sau cng bit
ACC.7 s c xa gi tr tr v ging nh khi m 7 bit c chuyn n chng trnh con.
4. V d 4: (Chng trnh con thu (nhn) d liu)

Gi s port ni tip c khi ng (nh v d 1). Hy vit mt chng trnh con thu d
liu t port ni tip v np gi tr thu c vo thanh ghi A (d liu thu c c dng 7 bit d liu + 1
bit kim tra l, tng t d liu t v d 2). S dng bit th 8 thu c lm bit kim tra l v set c nh
C nu c li chn l.
Gii
Chng trnh con ny bt u bng vic ch c ngt thu RI c set bng 1 ch ra rng k t
sn sng trong b m thu SBUF ( c c). Khi RI=1, lnh JNB chuyn iu khin n lnh tip
theo sau lnh ny. C RI c xa v m trong SBUF c cha vo thanh ghi A. Do bit P trong thanh
ghi PSW c thit lp kim tra chn cho gi tr trong thanh ghi A. Cho nn bit ny s c set
bng 1 nu ni dung thanh ghi A (tc d liu va thu c) c cha bit kim tra l bit th 7 ca
thanh ghi ny v ngc li th bit ny s c xo bng 0 thng qua lnh CPL. Vic di chuyn bit P vo
trong c nh CY s lm cho CY=0 nu khng c li hoc CY=1 nu c mt li chn l . Sau cng bit
ACC.7 s c xa m bo rng ch c m 7 bit c tr v cho chng trnh gi.
5. V d 5: (Truyn d liu)
Vit chng trnh cho 8051 (fOsc=11,0592MHz) truyn lin tc mt k t A thng qua port ni
tip vi tc 4800 baud (Mode 1).
Gii
Tnh ton: Da vo nhng cng thc hc, ta c:
(SCON) = 52H
Port ni tip (Mode 1)
Timer 1 (Mode 2)
(TMOD) = 20H
(TH1) = -6 vi (SMOD) = 0
Baud rate = 4800 v fOsc=11,0592MHz
Gio trnh Vi x l.
172

MOV
SCON, #52H
;UART 8 bit, tc baud thay i.
MOV
TMOD, #20H
;Ch 8 bit t np li.
MOV
TH1, #(-6)
;Baud rate = 4800.
SETB
TR1
;Khi ng Timer 1.
LOOP:
JNB
TI, $
;Kim tra pht d liu trc hon tt?
CLR
TI
;Xo c TI, chun b cho ln pht k tip.
MOV
SBUF, #A
;Pht k t A.
SJMP
LOOP
;Lp li qu trnh pht.
END
;Kt thc chng trnh.
6. V d 6: (Truyn d liu)
Vit chng trnh cho 8051 (fOsc=11,0592MHz) truyn lin tc chui k t TTCNDT thng
qua port ni tip vi tc 19200 baud (Mode 1).
Gii
Tnh ton:
Timer 1 (Mode 2)
(SCON) = 52H
(TMOD) = 20H
(TH1) = -3 vi (SMOD) = 1

MOV
SCON, #52H
MOV
TMOD, #20H
;Ch 8 bit t np li.
MOV
TH1, #(-3)
;Baud rate = 19200.
MOV
A, PCON
;Ly gi tr t thanh ghi PCON.
SETB
ACC.7
;SMOD = 1.
MOV
PCON, A
;Chuyn gi tr mi vo PCON.
SETB
TR1
;Khi ng Timer 1.
LOOP:
MOV
NEXT:
CLR
A
;Xo ACC, A = 0
MOVC
A, @A+DPTR
JZ
EXIT
;Thot nu l k t Null.
JNB
TI, $
CLR
TI
;Xo c TI, chun b pht tip.
MOV
SBUF, A
;Pht d liu ra port ni tip.
INC
DPTR
;Tng con tr d liu.
SJMP
NEXT
;Lp li qu trnh pht k t k tip.
EXIT:
SJMP
LOOP
;Lp li t u.
MYDATA:
DB
TTCNDT,0
;D liu cn truyn i, c k t Null.
END
;Kt thc chng trnh.
Gio trnh Vi x l.
173
8. V d 8: (Nhn d liu)
Vit chng trnh cho 8051 (fOsc=11,0592MHz) nhn lin tc cc d liu thng qua port ni tip
vi tc 4800 baud (Mode 1) v gi cc d liu nhn c n P1.
Gii
Tnh ton:
Timer 1 (Mode 2)
(SCON) = 52H
(TMOD) = 20H
(TH1) = -6 vi (SMOD) = 0

MOV
SCON, #52H
MOV
TMOD, #20H
;Ch 8 bit t np li.
MOV
TH1, #(-6)
;Baud rate = 4800.
SETB
TR1
;Khi ng Timer 1.
LOOP:
JNB
RI, $
;Kim tra thu d liu hon tt?
CLR
RI
;Xo c RI, chun b cho ln thu k tip.
MOV
A, SBUF
;Thu v ct d liu vo ACC.
MOV
P1, A
;Gi d liu thu c ra P1.
SJMP
LOOP
;Lp li qu trnh pht.
END
;Kt thc chng trnh.
9. V d 9: (Thu v pht d liu)

Cho port ni tip ca 8051 (fOsc=11,0592MHz) c ni vi cng COM ca my tnh PC (gi s
rng trn my tnh c sn chng trnh gi v nhn d liu ni tip thng qua cng COM). Hy
vit chng trnh cho 8051 thc hin cc cng vic sau:
Gi cu thng bo READY n my tnh.
Lin tc nhn cc d liu ni tip t my tnh gi n v chuyn cc d liu ny ra P1 ca
8051.
Lin tc ly cc d liu t P2 ca 8051 v pht cc d liu ny n my tnh thng qua port
ni tip.
Bit rng 8051 truyn d liu ni tip Mode 1 vi tc baud l 9600.
Gii
Tnh ton:
Timer 1 (Mode 2)
(SCON) = 52H
(TMOD) = 20H
(TH1) = -3 vi (SMOD) = 0

MOV
P2, #0FFH
;Cu hnh P2 l cng vo.
MOV
SCON, #52H
MOV
TMOD, #20H
;Ch 8 bit t np li.
MOV
TH1, #(-3)
;Baud rate = 4800.
SETB
TR1
;Khi ng Timer 1.
MOV
NEXT:
;Phn pht cu thng bo
CLR
A
;Xo ACC, A = 0
MOVC
A, @A+DPTR
Gio trnh Vi x l.
174

JZ
ACALL
INC
SJMP
EXIT:
ACALL
MOV
MOV
ACALL
SJMP
INDATA:
JNB
CLR
MOV
RET
OUTDATA:
JNB
CLR
MOV
RET
MYDATA:
DB
END
EXIT
OUTDATA
DPTR
NEXT
INDATA
P1, A
A, P2
OUTDATA
EXIT
RI, $
RI
A, SBUF
;Thot nu l k t Null.
;Pht d liu, cu thng bo.
;Tng con tr d liu.
;Lp li qu trnh pht k t k tip.
;Phn pht/thu d liu gia 8051 v PC.
;Thu d liu t PC.
;Chuyn d liu ny n P1.
;Ly d liu t P2.
;Pht d liu ny n PC.
;Lp li chu trnh lm vic.
;Chng trnh con thu d liu.
;Kim tra thu d liu hon tt?
;Xo c RI, chun b cho ln thu tip.
;Thu v ct d liu vo ACC.
;Chng trnh con pht d liu.

TI, $
TI
;Xo c TI, chun b cho ln pht tip.
SBUF, A
;Pht d liu cha trong ACC.
READY,0
;Cu thng bo, c k t Null.

;Kt thc chng trnh.
X. PHN BI TP:
Bi 1: Vit on lnh c mt chui data cha trong RAM ni t a ch 30H n 50H v xut
ra mt thit b (v d nh mn hnh tinh th lng LCD) c ni vi port ni tip ca 8051 (ch
UART 8 bit, 2400 baud). Cho fOSC=11,0592 MHz.
Bi 2: Vit on lnh nhn mt chui data t mt thit b ngoi (v d nh my c m vch)
ni vi 8051 qua port ni tip (ch UART 8 bit, 4800 baud) v ghi data vo RAM ni t a ch
40H. Bit rng chui data gm 20 byte v fOSC=11,0592 MHz.
Bi 3: Vit on lnh ly mt chui data cha trong RAM ngoi bt u t a ch 2000H v
xut ra mt thit b c ni vi port ni tip ca 8051 (ch UART 8 bit, 1200 baud). Chui kt
thc bi k t EOT (c m ASCII l 04H) v k t ny cng c xut ra (fOSC=11,0592 MHz).
Bi 4: Lm li bi 3 nhng khng xut k t EOT.
Bi 5: Vit on lnh nhn mt chui data t mt thit b ngoi ni vi 8051 qua port ni tip
(ch UART 8 bit, 9600 baud) v ghi data vo RAM ngoi bt u t a ch 4000H. Chui data bt
u bng k t STX (02H) v kt thc bng k t ETX (03H). Khng ghi hai k t ny vo RAM.
Cho fOSC=11,0592 MHz.
Bi 6: Vit chng trnh con mang tn XUAT c nhim v ly mt chui data cha trong
RAM ngoi xut ra port ni tip ch UART 9 bit. Bit th 9 l bit parity chn. Chui data kt thc
bng k t NULL (00H). on lnh gi chng trnh con XUAT s t a ch bt u ca chui vo
DPTR trc khi gi chng trnh con XUAT. Gi s port ni tip c khi ng.
Bi 7: Vit chng trnh con mang tn NHAP c nhim v nhp mt chui data gm 30 byte
t port ni tip ch UART 9 bit, bit th 9 l bit parity l. Nu data nhn c khng b li th ghi
Gio trnh Vi x l.
175
vo mt vng nh ca RAM ni, nu b li th khng ghi. on lnh gi chng trnh con NHAP s
t a ch u ca vng nh vo thanh ghi R0 trc khi gi chng trnh con NHAP. Gi s port ni
tip c khi ng.
Gio trnh Vi x l.
176
Chng 6: Hot ng ngt (Interrupt).
CHNG 6
HOT NG NGT
(INTERRUPT)
I. M U:
1 CPU CH THC THI C 1 LNH TI MT THI IM.
Ngt (Interrupt) l vic xy ra mt iu kin (mt s kin) lm cho chng trnh ang thc thi
(chng trnh chnh) b tm dng quay sang thc thi mt chng trnh khc (chng trnh x l
ngt) ri sau quay tr v thc thi tip chng trnh ang b tm dng. Cc ngt ng vai tr quan
trng trong vic thit k v hin thc cc ng dng ca b vi iu khin. Cc ngt cho php h thng
p ng mt s kin theo cch khng ng b v x l s kin trong khi mt chng trnh khc ang
thc thi. Mt h thng c iu khin bi ngt cho ta o tng nhiu cng vic ang c vi x l
thc hin ng thi.
CPU d nhin khng th thc thi nhiu hn mt lnh mt thi im nhng CPU c th tm
ngng vic thc thi mt chng trnh thc thi mt chng trnh khc ri sau quay v thc thi
tip tc chng trnh ang b tm ngng, iu ny th tng t nh vic CPU ri khi chng trnh gi
thc thi chng trnh con b gi ri sau quay tr v chng trnh gi.
Cn phi phn bit s ging v khc nhau gia ngt v gi chng trnh con:
Ging nhau:
Khi xy ra iu kin tng ng th CPU s tm dng chng trnh chnh ang thc thi
thc thi mt chng trnh khc (chng trnh con / chng trnh x l ngt) ri sau (sau khi x l
xong chng trnh con / chng trnh x l ngt) th CPU s quay v thc thi tip tc chng trnh
chnh ang b tm dng.
Khc nhau:
Ngt
Chng trnh con
Thi im xy ra s
kin
Khng bit trc (hay xy ra khng Bit trc (hay xy ra ng b vi

ng b vi chng trnh chnh).
chng trnh chnh).
Nguyn nhn dn n
s kin
Do cc tn hiu iu khin t Timer, Do lnh gi chng trnh con

Serial port v bn ngoi chip.
(ACALL, LCALL).
Chng trnh x l ngt (tc l chng trnh m CPU phi thc hin khi c mt ngt xy n)
c gi l trnh phc v ngt ISR (ISR: Interrupt Service Routine) hay trnh qun l ngt (Interrupt
Handler). ISR c thc thi nhm p ng mt ngt v trong trng hp tng qut thc hin vic xut
nhp i vi mt thit b. Khi mt ngt xut hin, vic thc thi chng trnh chnh tm thi b dng li
v CPU thc thi vic r nhnh n trnh phc v ngt ISR. CPU s thc thi ISR thc hin mt cng
vic v kt thc vic thc hin cng vic ny khi gp lnh quay v t trnh phc v ngt (lnh
RETI), sau chng trnh chnh tip tc c thc thi ti ni b tm dng. Ta c th ni chng trnh
Gio trnh Vi x l.
177
chnh c thc thi mc nn (Base level), cn ISR c thc thi mc ngt (Interrupt level).
Biu din vic thc thi chng trnh c ngt v khng c ngt:
Mt v d v ngt in hnh l nhp thng s iu khin s dng bn phm. Ta hy kho st mt

ng dng ca l viba. Chng trnh chnh c th iu khin thnh phn cng sut ca l thc hin
vic nu nng. Tuy nhin trong khi ang nu, h thng phi p ng vic nhp s liu bng tay trn
ca l (chng hn nh ta mun yu cu rt ngn bt hay ko di thm thi gian nu), iu ny c th
xy ra ti bt c thi im no trong qu trnh nu.
Trng hp ta khng s dng ngt: Nh ta bit, mt h thng ch c th thc thi mt cng
vic ti mt thi im. Cho nn khi h thng ang thc thi vic nu nng th n khng th thc thi
vic p ng nhp s liu khi n xy ra v ngc li. V th trong trng hp ny h thng phi thc
hin cho xong vic nu nng ri mi thc hin tip vic p ng nhp s liu (iu ny v l v khi
nu nng xong th cn g phi iu chnh thi gian na) hoc ngc li h thng phi thc hin cho
xong vic p ng nhp s liu ri mi thc hin tip vic nu nng (iu ny cng v l v khng th
bit trc c vic nhp s liu xy ra lc no, cho nn qu trnh h thng ch i vic nhp s liu
s tr nn v ngha).
Trng hp ta s dng ngt: Ta nhn thy rng vic nu nng l vic din ra lin tc t u
n cui, cn vic p ng nhp s liu ch xy ra khi ta nhn bn phm (khng xc nh c thi
im xy ra). V th, ta phn cp cho chng trnh chnh (mc nn) s iu khin thnh phn cng sut
ca l thc hin vic nu nng, cn vic p ng nhp s liu s do ngt iu khin (mc ngt).
Bnh thng th l thc hin vic nu nng nh xc nh, khi ngi s dng nhn bn phm th
mt tn hiu ngt c to ra v chng trnh chnh s b tm thi dng li. ISR c thc thi c
m phm v thay i cc iu kin nu tng ng, sau kt thc bng cch chuyn iu khin tr v
chng trnh chnh. Chng trnh chnh c thc thi tip t ni tm dng.
iu quan trng trong v d nu trn l vic nhp bn phm xut hin khng ng b ngha l
xut hin cc khong thi khng bo trc hoc c iu khin bi phn mm ang c thc thi
trong h thng. l mt ngt.
Gio trnh Vi x l.
178
II. PHNG PHP PHC V THIT B:

Mt b vi iu khin c th phc v mt hoc nhiu thit b. C hai phng php phc v thit
b l: phng php ngt (Interrupt) v phng php thm d (Polling).
phng php ngt, mi khi c mt thit b cn c phc v th thit b s bo cho b vi iu
khin bng cch gi n mt tn hiu ngt. Khi nhn c tn hiu ny, b vi iu khin s ngng
mi cng vic ang thc hin chuyn sang phc v cho thit b ny.
phng php thm d, b vi iu khin lin tc kim tra tnh trng ca mt thit b v khi
iu kin c p ng th n s tin hnh phc v cho thit b ny. Sau , b vi iu khin chuyn
sang kim tra trng thi ca thit b k tip cho n khi tt c thit b u c phc v.
im mnh ca phng php ngt l mt b vi iu khin c th phc v c nhiu thit b,
nhng d nhin l khng cng mt thi im. Mi thit b c th c b vi iu khin phc v da
theo mc u tin c gn. phng php thm d, th khng th gn mc u tin cho thit b c
v b vi iu khin tin hnh kim tra cc thit b theo kiu hi vng mt cch ln lt qua tng thit
b. Ngoi ra, phng php ngt cho php b vi iu khin che hoc b qua mt yu cu phc v ca
thit b, iu m phng php thm d khng th thc hin. Tuy nhin, l do chnh m phng php
ngt c a chung hn l v phng php thm d lng ph ng k thi gian ca b vi iu khin
do phi hi d tng thit b, ngay c khi chng khng cn c phc v.
lm r hn vn ny, chng ta cn xem li cc v d v lp trnh b nh thi c trnh
by trong chng 4. Trong c lnh JNB TF1, $ c s dng ch i cho n khi b nh thi
trn (TF=1). cc v d ny, trong khi ch i c TF=1 th b vi iu khin khng th lm c cng
vic g khc, iu ny dn n vic lng ph thi gian. Cng vi b nh thi ny, nu ta dng phng
php ngt th b vi iu khin c th thc hin mt s cng vic no trong khi ang ch i c
TF=1. Khi c TF=1 th b vi iu khin s b ngt cho d n ang lm vic g i chng na, iu ny
s khng lm cho b vi iu khin b lng ph thi gian mt cch v ngha.
III. T CHC NGT CA 8051:
1. Cc ngun ngt:
Lu :
Khi ta reset h thng th tt c cc ngt u b cm hot ng.
Cc ngun ngt ny c cho php hoc cm hot ng bng lnh do ngi lp trnh thit lp
cho tng ngt.
Vic x l cc ngt c thc hin qua 2 s :
o S u tin ngt c th thay i c v do ngi lp trnh thit lp.
o S chui vng c nh, khng thay i c.
Hai s ny gip CPU gii quyt cc vn lin quan n ngt nh: hai hay nhiu ngt xy ra
ng thi hoc mt ngt xy ra trong khi mt ngt khc ang c thc thi.
Gio trnh Vi x l.
179
Cc c ngt ca chip 8051:
Lu :
Mt ngt xy ra th c ngt tng ng s c set bng 1.
Khi ISR ca ngt c thc thi th c ngt tng ng s t ng b xa v 0 bng phn cng
(ngoi tr c ngt RI v TI phi c xa v 0 bng phn mm).
i vi ngt ngoi s c hai cch kch hot to ra mt tn hiu ngt: ngt ngoi kch hot khi
c mc thp v ngt ngoi kch hot khi c cnh m ti chn INT0\ hoc INT1\.
2. Qui nh vic chn loi kch hot cho ngt ngoi:
Vic chn la loi kch hot cho cc ngt ngoi, thuc loi kch hot cnh hay thuc loi kch
hot mc, th c lp trnh thng qua cc bit IT0 v IT1 ca thanh ghi TCON.
IT0 = 0 Ngt ngoi 0 c kch khi bi vic pht hin mc thp ti chn INT0\.
IT0 = 1 Ngt ngoi 0 c kch khi bi vic pht hin cnh m ti chn INT0\.
IT1 = 0 Ngt ngoi 1 c kch khi bi vic pht hin mc thp ti chn INT1\.
IT1 = 1 Ngt ngoi 1 c kch khi bi vic pht hin cnh m ti chn INT1\.
Lu : Khi to tn hiu ngt ti chn INT0\ hoc INT1\ ta cn phi ch n thi gian duy tr
tc ng ca tn hiu ngt.
i vi loi ngt kch hot cnh m (thi gian ti thiu):
8051
INTx
(1)
fOSC (MHz): tan so thach anh.

Tm ( s): chu ky may.
Tm =
(0)
x = 0, 1
12
f OSC
Tm Tm
i vi loi ngt kch hot mc thp (thi gian ti a):
8051
INTx
(1)
(0)
(*) (**)
Gio trnh Vi x l.
x = 0, 1
(*): Duy tr trang thai (0) cho en

khi ISR tng ng c thc
hien.
(*) = 4 Tm
(**):Tr ve trang thai (1) trc khi
ISR tng ng c thc hien
xong hoac trc khi co mot
ngat khac c tao ra.
180
3. Thanh ghi cho php ngt (IE):

Thanh ghi cho php ngt (IE: Interrupt Enable): cha cc bit dng cho php hoc cm cc
ngt hot ng.
Cu trc ca thanh ghi IE:
Hai iu kin mt ngt c php hot ng l:

Bit EA = 1.
Bit ngt tng ng = 1.
V d: ngt ca Timer 1 c php hot ng ta dng lnh:
SETB ET1
SETB EA
hoc
MOV IE, #10001000B
Mc d c cch trn u cho ta mt kt qu nh nhau sau khi h thng c thit lp li trng
thi ban u (reset h thng). Tuy nhin trong khi chng trnh ang hot ng th nh hng ca hai
cch ny c khc nhau v cch th hai ghi ln thanh ghi IE.
Cch th nht, s dng hai lnh SETB nn ch nh hng n 2 bit cn tc ng m khng gy
nh hng n 5 bit cn li ca thanh ghi IE. Trong khi , cch th hai ch s dng lnh MOV nn s
lm cho 5 bit cn li ny bit xa mt. Tt nht ta nn khi ng thanh ghi IE bng lnh MOV u
chng trnh ngay sau khi h thng c thit lp li. Vic cho php hoc khng cho php cc ngt
trong chng trnh nn s dng cc lnh SETB hoc CLR trnh nh hng n cc bit khc trong
thanh ghi IE.
4. Thanh ghi u tin ngt (IP):
Khi nim u tin ngt gip 8051 gii quyt vn hai tn hiu ngt xut hin ng thi v
vn mt tn hiu ngt xut hin trong khi mt ngt khc ang c thc thi.
Ngt u tin mc cao Ngt u tin mc thp
Thanh ghi u tin ngt (IP: Interrupt Priority): cha cc bit dng thit lp mc u tin
(mc cao hay mc thp) cho tng ngt ring r.
Gio trnh Vi x l.
181
Cu trc ca thanh ghi IP:
Khi h thng c thit lp li trng thi ban u th tt c cc ngt u s c mc nh mc

u tin thp. tng cc mc u tin cho php mt trnh phc v ngt c tm dng bi mt ngt
khc nu ngt mi ny c mc u tin cao hn mc u tin ca ngt hin ang c phc v. iu ny
hon ton hp l i vi 8051 v ta ch c hai mc u tin. Nu c ngt c mc u tin cao xut hin,
trnh phc v ngt cho ngt c mc u tin thp phi tm dng (ngha l b ngt). Ta khng th tm
dng mt chng trnh phuc v ngt c mc u tin cao.
Chng trnh chnh do c thc thi mc nn v khng c kt hp vi mt ngt no nn
lun lun b ngt bi cc ngt cho d cc ngt c mc u tin thp hay mc u tin cao. Nu c hai
ngt vi mc u tin ngt khc nhau xut hin ng thi, ngt c mc u tin cao s c phc v
trc.
5. Th t chui vng ngt (Interrupt Polling Sequence):
Khi nim chui vng gip 8051 gii quyt vn hai hay nhiu tn hiu ngt c mc u tin
ging nhau xut hin ng thi.
Chui vng ny s l (c sp xp theo th t t thp n cao):
Ngt ngoi 0 Ngt Timer 0 Ngt ngoi 1
Ngt Timer 1 Ngt port ni tip Ngt Timer 2 (ch c 8052)
Hnh di y minh ha 5 nguyn nhn ngt, c ch cho php ring r v ton cc, chui vng
v cc mc u tin. Trng thi ca tt c cc nguyn nhn ngt c th hin thng qua cc bit c
tng ng trong cc thanh ghi chc nng c bit c lin quan. D nhin nu mt ngt no khng
c php, nguyn nhn ngt tng ng khng th to ra mt ngt nhng phn mm vn c th kim
tra c ngt . Ly th d b nh thi v port ni tip trong hai chng trc s dng cc c ngt mt
cch rng ri d khng c ngt tng ng xy ra, ngha l khng s dng cc ngt.
Ngt do port ni tip l kt qu OR ca c ngt khi thu RI (c ngt thu) v c ngt khi pht TI
(c ngt pht).
Gio trnh Vi x l.
182
Cu trc ngt ca 8051:
IV. X L NGT V CC VECT NGT:

1. Qui trnh x l ngt:
Cc thao tc s xy ra khi c mt ngt xut hin v n c CPU chp nhn:
Hon tt thc thi lnh ti thi im v dng chng trnh chnh.
Gi tr ca thanh ghi PC c ct vo stack.
Trng thi ca ngt ti thi im c lu gi li.
Cc ngt c gi li mc ngt.
a ch ca ISR ca ngt tng ng c np vo thanh ghi PC.
ISR ca ngt tng ng c thc thi.
(ISR thc thi xong khi gp lnh RETI).
Gi tr trong stack (ca PC c) c phc hi li vo thanh ghi PC.
Trng thi cc ngt c phc hi li.
Chng trnh chnh tip tc c thc thi ti ch b tm dng.
ISR c thc thi p ng cng vic ca ngt. Vic thc thi ISR kt thc khi gp lnh RET
(tr v t mt trnh phc v ngt). Lnh ny ly li gi tr c ca b m chng trnh PC t stack v
phc hi trng thi ca ngt c. Vic thc thi chng trnh chnh c tip tc ni b tm ngng.
Gio trnh Vi x l.
183
2. Cc vect ngt:
Khi mt ngt c chp nhn, gi tr c np cho b m chng trnh PC c gi l vect
ngt. Vect ngt l a ch bt u ca chng trnh phc v ngt (ISR) ca ngt tng ng.
Vect reset h thng cng c xem nh l mt ngt: chng trnh chnh b ngt v b m
chng trnh PC c np gi tr mi.
Khi mt trnh phc v ngt c tr n, c gy ra ngt s t ng b xa v 0 bi phn cng.
Cc ngoi l bao gm cc c RI v TI i vi cc ngt do port ni tip, cc nguyn nhn ngt thuc
loi ny do c hai kh nng to ra ngt nn trong thc t CPU khng xa c ngt.
Bng qui nh a ch bt u ca cc ISR (bng vect ngt):
V. THIT K CC CHNG TRNH S DNG NGT:

1. Tng quan:
Khi thit k cc chng trnh khng s dng ngt th ta s gp phi nhng trng hp CPU
hon ton tiu ph thi gian vo vic ch i cc tc nhn cn thit xy ra (V d: s trn ca c TF0,
TF1; vic thu xong mt d liu v c RI=1; vic pht xong mt k t v c TI=1; v.v) sau mi
tip tc thc hin cng vic.
iu ny khng thch hp cho cc ng dng iu khin i hi phi tc ng qua li vi
nhiu thit b cng lc.
gii quyt vn trn ta cn thit k cc chng trnh c s dng n ngt.
V n gip cho CPU khng tn thi gian ch i tc nhn m ch khi no tc nhn xy
n th CPU mi thc hin vic x l tc nhn , khong thi gian tc nhn khng xy ra th CPU s
lm vic khc.
Gio trnh Vi x l.
184
T chc b nh khi s dng ngt:
Khung mu cho mt chng trnh c s dng ngt:

ORG 0000H
;im nhp ca reset h thng.
LJMP MAIN
;Lnh nhy vt qua cc ISR.
;im nhp ca cc ISR.
ORG 0030H
;im nhp ca chng trnh chnh.
MAIN:
;Chng trnh chnh bt u.
END
2. Thit k cc chng trnh ISR kch thc nh:
iu kin: Khi ISR c kch thc khng qu 8 byte (k c lnh RETI).
ISR phi c vit trong phm vi im nhp tng ng ca n trong b nh chng trnh (xem
phn t chc b nh khi s dng ngt).
Lu :
Nu ch c mt nguyn nhn ngt c s dng th ISR ca n c th c vit trn
sang im nhp ca cc ISR khc (ngha l ISR c kch thc ln hn 8 byte, nhng phi nh hn 46
byte). V khi vng nh ca cc ISR khc khng c dng n nn ta c th tn dng s dng
cho ISR ny.
Nu c nhiu nguyn nhn ngt c s dng th ta phi cn thn m bo cho cc
ISR c bt u ng v tr m khng trn sang ISR k (ngha l ISR c kch thc khng qu 8 byte).
Gio trnh Vi x l.
185
Khung mu chng trnh: (V d: dng ngt Timer0 v ngt ngoi 1)

ORG 0000H
LJMP MAIN
ORG 000BH
;im nhp cho ISR ca Timer 0.
;ISR ca Timer 0.
RETI
;Kt thc ISR ca Timer 0.
ORG 0013H
;im nhp cho ISR ca ngt ngoi 1.
;ISR ca ngt ngoi 1.
RETI
;Kt thc ISR ca ngt ngoi 1.
ORG 0030H
MAIN:
END
3. Thit k cc chng trnh ISR kch thc ln:
iu kin: Khi ISR c kch thc vt qu 8 byte.
ISR khng th vit vo im nhp tng ng ca n trong b nh chng trnh (v kch thc
im nhp ch c 8 byte) ta phi chuyn ISR ny n mt ni khc trong b nh chng trnh hoc
c th vit ln qua im nhp ca ISR k tip (nu ISR khng s dng).
Khung mu chng trnh: (V d: dng ngt Timer0 v ngt ngoi 1)
ORG 0000H
LJMP MAIN
ORG 000BH
;im nhp cho ISR ca Timer 0.
LJMP T0ISR
;Lnh nhy n ISR ca Timer 0.
ORG 0013H
;im nhp cho ISR ca ngt ngoi 1.
LJMP EX1ISR ;Lnh nhy n ISR ca ngt ngoi 1.
ORG 0030H
MAIN:
SJMP $
;Lnh cch ly chng trnh.
T0ISR:
;ISR ca ngt Timer 0.
RETI
EX1ISR:
;ISR ca ngt ngoi 1.
RETI
END
Gio trnh Vi x l.
186
Nhn xt tng qut:

o n gin, cc chng trnh ca chng ta ch lm vic thi im bt u. Chng
trnh chnh khi ng port ni tip, b nh thi v cc thanh ghi ngt sao cho thch hp vi yu cu
t ra v ri khng lm g c. Cng vic hon ton c thc hin bn trong cc ISR. Sau cc lnh
khi ng, chng trnh chnh cha v thc hin lnh sau y (lnh nhy ti ch khng lm g c):
SJMP $
o Khi c mt tn hiu ngt xut hin, chng trnh chnh tm thi b dng li trong khi ISR
c thc thi. Lnh RETI cui ca cc ISR s tr iu khin v cho chng trnh chnh v chng
trnh chnh tip tc khng lm g c (lnh nhy ti ch ). iu ny khng c g l khng t nhin i
vi chng ta. Trong nhiu ng dng hng iu khin, phn ln cng vic c thc hin trong trnh
phc v ngt. Cc v d minh ha di y s cho ta thy iu ny.
VI. CC V D MINH HA:
1. V d minh ha x l ngt Timer:
V d 1: Vit chng trnh s dng Timer 0 v cc ngt to ra mt sng vung c tn s 10
KHz trn chn P1.0, fOsc = 12MHz.
Gii
ORG
LJMP
ORG
0000H
MAIN
000BH
CPL
RETI
ORG
P1.0
MOV
MOV
SETB
MOV
SJMP
END
TMOD, #02H
TH0, #(-50)
TR0
IE, #82H
$
T0ISR:
0030H
MAIN:
;im nhp reset.

;Nhy qua khi cc vect ngt.
;im nhp ISR ca Timer 0.
;ISR ca Timer 0.
;Ly b.
;im nhp chng trnh chnh.
;Chn ch 2 cho Timer 0.
;nh thi 50s.
;Cho Timer 0 hot ng.
;Cho php ngt Timer 0 .
;Khng lm g (nhy ti ch).
;Kt thc chng trnh.
Lu : Lnh SJMP$ c th c thay th bng mt on lnh thc thi nhng cng

vic khc. Vic thay th ny khng nh hng g n vic to sng vung f=10KHz ti chn P1.0. V
c sau mi 50s th nhng cng vic s b tm dng (ngt Timer 0 xut hin) CPU thc hin vic
to sng vung ri quay v thc hin tip nhng cng vic .
Ngay sau khi reset h thng, b m chng trnh PC c np 0000H. Lnh u tin c
thc thi l LJMP MAIN, lnh ny r nhnh n chng trnh chnh a ch 0030H trong b nh
chng trnh. Ba lnh u tin ca chng trnh chnh s khi ng Timer 0 ch 8 bit t ng np
li (Mode 2), sao cho Timer 0 s trn sau mi 50s. Lnh MOV IE, #82H cho php cc ngt do Timer0
to ra. Mi mt ln trn, Timer s to ra mt ngt. D nhin l ln trn u tin s khng xut hin sau
Gio trnh Vi x l.
187
50s do chng trnh chnh ang trong vng lp khng lm g. Khi ngt xut hin sau mi 50s,
chng trnh chnh b ngt v ISR cho Timer0 c thc thi. v d trn ISR ny ch n gin ly b
bit ca port v quay tr v chng trnh chnh ni vng lp khng lm g c thc thi ch mt
ngt mi sau mi 50s.
Lu l c trn TF0 khng cn c xa bi phn mm do khi cc ngt c cho php th c
ny t ng c xa bi phn cng khi CPU tr n trnh phc v ngt.
V d 2: Vit chng trnh s dng cc ngt to ng thi cc dng sng vung c tn s 7
KHz v 500 Hz ti cc chn P1.7 v P1.6 (khng quan tm n lch pha ca hai sng ny), fOsc =
12MHz.
Gii
ORG
LJMP
ORG
LJMP
ORG
LJMP
ORG
MAIN:
MOV
MOV
SETB
SETB
MOV
SJMP
T0ISR:
CPL
RETI
T1ISR:
CLR
MOV
MOV
SETB
CPL
RETI
END
0000H
MAIN
000BH
T0ISR
001BH
T1ISR
0030H
;im nhp reset.

;Lnh nhy n ISR Timer 0.
TMOD, #12H
TH0, #-71
;nh thi 71s.
TR0
TF1
;Buc Timer 1 ngt.
IE, #8AH
;Cho php cc ngt hot ng.
$
P1.7
;Ly b.
TR1
;Dng Timer 1.
TH1, #HIGH(-1000) ;nh thi 1ms.
TL1, #LOW(-1000)
TR1
P1.6
;Ly b.
;Kt thc chng trnh.
Gio trnh Vi x l.
188

vic khc. Vic thay th ny khng nh hng g n vic to sng vung f = 7KHz v f = 500Hz ti
chn P1.7 v chn P1.6. V c sau mi 71s v 1ms th nhng cng vic s b tm dng (ngt Timer
0 v ngt Timer 1 xut hin) CPU thc hin vic to sng vung ri quay v thc hin tip nhng
cng vic .
Vic t hp cc ng ra ny rt kh to ra c trn mt h thng khng s dng iu khin
ngt. Timer 0 hot ng ch 2, c s dng to ra dng sng 7 KHz trn chn P1.7. Timer 1
hot ng ch 1, c s dng to ra dng sng 500 Hz trn chn P1.6. S d trong trng hp
ny, Timer 1 phi c thit lp hot ng ch 1 l do dng sng 500Hz yu cu thi gian mc
cao v thi gian mc thp l 1ms, ch 2 khng s dng c trong trng hp ny.
Cng cn ch l cc thanh ghi TH1/TL1 khng c khi ng u chng trnh chnh nh
trng hp ca thanh ghi TH0. Do TH1/TL1 phi c np li sau mi ln b nh thi trn, TF1 c
set bng 1 trong chng trnh chnh bi phn mm (lnh SETB TF1) c s dng buc phi c
mt ngt ban u ngay trc khi cc ngt c cho php. iu ny c hiu qu cho vic bt u dng
sng 500Hz.
V d 3: Vit chng trnh lin tc nhn d liu 8 bit cng P0 v sau gi d liu ny n
cng P1. Trong thi gian ny cn to ra trn chn P2.1 mt sng vung c chu k l 200s. S dng
Timer 0 to sng vung, fOsc = 11,0592MHz.
Gii
ORG
LJMP
ORG
CPL
RETI
ORG
MAIN:
MOV
MOV
MOV
MOV
SETB
BACK:
MOV
MOV
SJMP
END
0000H
MAIN
000BH
P2.1
0030H
TMOD, #02H
P0, #0FFH
TH0, #(-92)
IE, #82H
TR0
A, P0
P1, A
BACK
Gio trnh Vi x l.
;im nhp reset.

;o trng thi chn P2.1, to xung.
;Cu hnh Port 0 l cng vo.
;nh thi 100s (na chu k).
;Cho php ngt Timer 0 hot ng.
;Nhn d liu t P0.
;Xut d liu va nhn c ra P1.
;Kt thc chng trnh.
189
V d 4: Vit chng trnh lin tc nhn d liu 8 bit cng P0 v sau gi d liu ny n
cng P1. Trong thi gian ny cn to ra trn chn P2.1 mt sng vung vi yu cu: thi gian sng
mc cao l 1085s v thi gian sng mc thp l 15s. S dng Timer 1 to sng vung,
fOsc=11,0592MHz.
T
tH
1085s
tL
15s
8051
11,0592MHz
P2.1
T = 200s
P0.0
P1.0
DATA 8 BIT
DATA 8 BIT
P0.7
P1.7
Gii
ORG
LJMP
ORG
LJMP
ORG
MAIN:
MOV
MOV
MOV
MOV
MOV
SETB
BACK:
MOV
MOV
SJMP
T1ISR:
CLR
CLR
MOV
DJNZ
MOV
MOV
SETB
SETB
RETI
END
0000H
MAIN
001BH
T1ISR
0030H
TMOD, #10H
P0, #0FFH
TL1, #18H
TH1, #0FCH
IE, #88H
TR1
A, P0
P1, A
BACK
TR1
P2.1
R2, #4
R2, $
TL1, #18H
TH1, #0FCH
TR1
P2.1
Gio trnh Vi x l.
;im nhp reset.

;nh thi 1085s (cho na chu k u).
;
;Cho php ngt Timer 1 hot ng.
;Nhn d liu t P0.
;Xut d liu va nhn c ra P1.
;Lp li lin tc hai thao tc trn.
;Dng Timer 1.
;nh thi 8TMachine (tng thi gian: 15s),
;to thi gian tr (cho na chu k sau).
;nh thi 1085s (cho na chu k u).
;
;Kt thc chng trnh.
190
2. V d minh ha x l ngt port ni tip:

Cc ngt do port ni tip xut hin khi c ngt pht TI hoc c ngt thu RI c set bng 1. Mt
ngt pht xut hin khi vic pht mt k t ghi vo SBUF hon tt. Mt ngt thu xut hin khi mt
k t c thu nhn y v ang trong SBUF ch c c. Nh vy, ngt pht xy ra khi b
m pht SBUF rng, ngt thu xy ra khi b m thu SBUF y.
Cc ngt do port ni tip c khc vi cc ngt do b nh thi. C gy ra ngt port ni tip
khng c xa bi phn cng khi CPU tr ti trnh phc v ngt. L do l v y ta c hai ngyn
nhn to ra ngt port ni tip, c th l hai ngt to ra bi hai c TI v RI. Nguyn nhn ngt phi
c xc nh trong trnh phc v ngt v c to ra ngt c xa bi phn mm. Cn nhc li l vi
cc ngt do b nh thi, c to ra ngt c xa bi phn cng khi CPU tr ti trnh phc v ngt.
V d 1: Vit chng trnh s dng cc ngt lin tc pht i m ASCII (c gi tr t 20H n
7EH) n mt thit b u cui ni vi 8051 qua port ni tip. Bit rng fOsc=11,0592MHz.
Gii
ORG
LJMP
ORG
LJMP
ORG
0000H
MAIN
0023H
SPISR
0030H
MOV
SCON, #42H
MOV
MOV
SETB
MOV
MOV
SJMP
TMOD, #20H
TH1, #(-24)
TR1
A, #20H
IE, #90H
$
CJNE
MOV
A, #7FH, SKIP
A, #20H
MOV
INC
CLR
RETI
END
SBUF, A
A
TI
MAIN:
SPISR:
;im nhp reset.

;im nhp ISR port ni tip.
;Lnh nhy n ISR port ni tip.
;Chn ch 1 cho port ni
;tip, TI=1 buc c ngt
;v gi k t u tin.
;Tc baud = 1200.
;Np m cho k t u tin.
;Cho php ngt port ni tip.
;ISR ca ngt port ni tip.
;Kim tra kt thc bng m.
;Tr li k t u tin.
SKIP:
;Truyn k t ra port ni tip.
;Ly m ca k t k tip.
;Xa c ngt pht.
;Kt thc ISR ca port ni tip.
;Kt thc chng trnh.

vic khc. Vic thay th ny khng nh hng g n vic pht m ASCII thng qua port ni tip. V c
sau mi ln port ni tip truyn xong mt k t th nhng cng vic s b tm dng (ngt port ni
tip xut hin) CPU thc hin vic kim tra k t kt thc bng m v ly m ca k t k tip
tip tc pht i ri quay v thc hin tip nhng cng vic .
Bng m ASCII bao gm 128 m 7 bit (xem thm trong phn ph lc Ph lc 4 Bng m
ASCII). Sau khi nhy n nhn MAIN a ch 0030H, ba lnh u tin dng khi ng Timer 1
cung cp xung clock 1200 baud cho port ni tip, lnh MOV SCON,#42H khi ng port ni tip
Gio trnh Vi x l.
191
ch 1 (UART 8 bit c tc baud thay i) v cho TI=1 buc to ra mt ngt trc khi cc ngt
c cho php hot ng. Sau m ASCII u tin (20H) c np cho thanh ghi A v cc ngt do
port ni tip c cho php. Cui cng phn chnh ca chng trnh i vo vng lp khng lm g
(tc l lnh SJMP $).
Trnh phc v ngt ca port ni tip lm tt c cng vic mt khi chng trnh chnh thit lp
cc iu kin ban u. Hai lnh u tin kim tra thanh ghi A v nu m ASCII t n 7FH (ngha l
m va mi c pht i l 7EH) th thanh ghi A s c thit lp li vi ni dung l 20H. Sau m
ASCII c gi n b m ca port ni tip (lnh MOV SBUF,A) c pht i. Thc hin vic
tng gi tr trong thanh ghi A c m k tip, c pht c xa (lnh CLR TI) v trnh phc v ngt
kt thc (lnh RETI). iu khin s tr v chng trnh chnh v lnh SJMP $ c thc thi cho n
khi TI li c set bng 1 cho ln pht d liu k tip.
Nu ta so snh tc ca CPU vi tc truyn d liu, ta nhn thy rng lnh SJMP $ c
thc thi vi phn trm t l thi gian rt ln trong chng trnh ny. Phn trm t l ny l bao nhiu?
tc 1200 baud, mi mt bit c truyn i trong mt khong thi gian l 0,8333ms. Nh vy 8 bit
d liu cng vi 1 bit start, 1 bit stop (mt ln truyn mt d liu gm 10 bit) chim 8,333ms. Thi
gian thc thi t nht ca trnh phc v ngt SPISR l tng ca s chu k cho mi lnh nhn vi
1,085s (tc 1TMachine), thi gian ny tnh c l 8 x 1,085s = 8,68s. Do vy, vi 8333s dng
truyn mt d liu m ch c 8,68s dnh cho trnh phc vu ngt SPISR. Lnh SJMP $ thc thi trong
khong thi gian 8333s - 8,68s = 8324,32s tc l khong 99,9% thi gian. Do vy ngt cn c
s dng c th loi b c khong thi gian khng lm g ny (chim n 99,9% thi gian hot
ng ca chng trnh truyn d liu ny. Mun vy th lnh SJMP $ c th c thay bi cc lnh
khc thc hin nhng cng vic khc theo yu cu ca ng dng. Cc ngt vn xut hin v cc k
t vn c pht t port ni tip sau mi 8,333ms.
V d 2: Vit chng trnh iu khin 8051 c d liu t cng P1 v ghi lin tc ti cng P2.
ng thi a mt bn sao d liu ti port ni tip thc hin vic truyn d liu ni tip. Bit rng
tc truyn l 9600 baud v fOsc = 11,0592MHz
Gii
ORG
LJMP
ORG
LJMP
ORG
MAIN:
MOV
MOV
MOV
MOV
MOV
SETB
BACK:
MOV
MOV
SJMP
SPISR:
CLR
MOV
0000H
MAIN
0023H
SPISR
0030H
P1, #0FFH
SCON, #42H
TMOD, #20H
TH1, #(-3)
IE, #90H
TR1
A, P1
P2, A
BACK
TI
SBUF, A
Gio trnh Vi x l.
;im nhp reset.

;Chn ch 1 cho port ni tip, cm thu.
;Tc baud = 9600.
;c d liu t P1.
;Xut d liu nhn c ra P2.
;Lp li cc thao tc trn.
;Xa c ngt pht TI.
;Xut d liu nhn c ra port ni tip.
192

RETI
END

;Kt thc chng trnh.
V d 3: Vit chng trnh iu khin 8051 c d liu t cng P1 v ghi lin tc ti cng P2.
Trong khi d liu nhn c t port ni tip th c gi n cng P0. Bit rng tc truyn l
9600 baud v fOsc = 11,0592MHz
Gii
ORG
LJMP
ORG
LJMP
ORG
MAIN:
MOV
MOV
MOV
MOV
MOV
SETB
BACK:
MOV
MOV
SJMP
SPISR:
CLR
MOV
MOV
RETI
END
0000H
MAIN
0023H
SPISR
0030H
P1, #0FFH
SCON, #52H
TMOD, #20H
TH1, #(-3)
IE, #90H
TR1
A, P1
P2, A
BACK
RI
A, SBUF
P0, A
;im nhp reset.

;Chn ch 1 cho port ni tip.
;Tc baud = 9600.
;c d liu t P1.
;Xa c ngt thu RI.
;Nhn d liu t port ni tip.
;Kt thc chng trnh.
V d 4: Vit chng trnh c s dng cc ngt thc hin cc cng vic sau:
Nhn d liu t port ni tip, sau th gi d liu ny n cng P0.
Nhn d liu t cng P1, sau th gi d liu ny n port ni tip v cng P2.
S dng Timer 0 to sng vung c tn s 5KHz ti P0.1.
Bit rng tc truyn l 4800 baud v fOsc = 11,0592MHz

Gii
ORG
LJMP
ORG
CPL
RETI
ORG
LJMP
ORG
MAIN:
MOV
0000H
MAIN
000BH
P0.1
0023H
SPISR
0030H
P1, #0FFH
Gio trnh Vi x l.
;im nhp reset.

;im nhp ISR Timer 0.
;Ly b chn P1.0, to xung.
193
MOV
MOV
MOV
MOV
MOV
SETB
SETB
BACK:
MOV
MOV
SJMP
SPISR:
JB
SCON, #52H
TMOD, #22H
TH1, #(-6)
TH0, #(-92)
IE, #92H
TR1
TR0
;Chn ch 1 cho port ni tip.

;Chn ch 2 cho Timer 0, Timer 1.
;Tc baud = 4800.
;nh thi 100s (na chu k), f = 5KHz.
;Cho php ngt port ni tip v Timer 0.
A, P1
P2, A
BACK
;c d liu t P1.
TI, TRANS
CLR
MOV
MOV
RETI
TRANS:
CLR
MOV
RETI
END
RI
A, SBUF
P0, A
;Kim tra thu xong (RI) hay pht

;xong (TI), nu thu xong (RI = 1) th:
;Xa c ngt thu RI.
;Nhn d liu t port ni tip.
;Nu pht xong (TI = 1) th:
;Xa c ngt pht TI.
;Xut d liu nhn c ra port ni tip.
;Kt thc chng trnh.
TI
SBUF, A
3. V d minh ha x l ngt ngoi:

Ngt ngoi xy ra khi c mc thp hoc c cnh m tc ng ln chn INT0\ hoc chn INT1\
ca 8051. Khi mt ngt ngoi c to ra, c to ra ngt (IE0 v IE1) c xa bi phn cng khi
CPU tr n trnh phc v ngt nu ngt thuc loi tc ng cnh m, cn nu ngt thuc loi tc ng
mc thp th nguyn nhn ngt ngoi s iu khin mc ca c thay v l phn cng trn chip.
V d 1: Vit chng trnh s dng cc ngt thit k b iu khin l nung sao cho nhit
trong l duy tr mc 120OC 5OC.
Gii
Gi s ta dng mch giao tip nh hnh bn di. Cun dy iu khin tt/m l c ni vi
P1.7 sao cho:
P1.7 = 1 th m l v P1.7 = 0 th tt l
B cm bin nhit c ni vi INT0\ v INT1\, cung cp cc tn hiu HOT\ v COLD\ nh
sau:
HOT\ = 0 nu T > 125OC v COLD\ = 0 nu T < 115OC
Chng trnh s cho l hot ng (m l) khi T < 115OC v cho l ngng hot ng (tt l) khi
T > 125OC.
Gio trnh Vi x l.
194
ORG
LJMP
ORG
EX0ISR:
CLR
RETI
ORG
EX1ISR:
SETB
RETI
ORG
MAIN:
MOV
SETB
SETB
SETB
JB
CLR
SKIP: SJMP
END
0000H
MAIN
0003H
;im nhp reset.

;im nhp ISR ngt ngoi 0.
P1.7
;Tt l.
0013H
P1.7
0030H
IE, #85H
IT0
IT1
P1.7
P3.2, SKIP
P1.7
$
;M l.
;Cho php ngt ngoi 0 v 1.
;Ngt ngoi kch khi cnh m.
iu khin tt/m l ty
;M l.
thuc trng thi nhit
hin ti ca l.
;Nu t > 125OC.
;Tt l.
;Kt thc chng trnh.

vic khc. Vic thay th ny khng nh hng g n vic iu khin hot ng tt m l theo nhit .
V c sau mi ln c tn hiu tc ng t cm bin th nhng cng vic s b tm dng (ngt ngoi 0
v 1 xut hin) CPU thc hin vic iu khin tt m l theo nhit qui nh ri quay v thc hin
tip nhng cng vic .
Ba lnh u tin trong chng trnh chnh cho php cc ngt ngoi v xc nh cc ngt ngoi
thuc loi tc ng cnh m. Do trng thi hin ti ca cc ng vo HOT\ v COLD\ cha bit c
nn ba lnh tip theo s iu khin l tt/m ty thuc vo trng thi nhit hin ti ca l. Trc
tin, l c m (lnh SETB P1.7) v ng vo HOT c ly mu (lnh JB P3.2, SKIP). Nu ng vo
HOT mc cao, ngha l T < 125OC, th lnh k c b qua v l vn tip tc c m. Ngc li,
nu ng vo HOT mc thp, ngha l T > 125OC, th lnh k tip CLR P1.7 c thc thi tt l
tr khi i vo vng lp khng lm g.
Gio trnh Vi x l.
195
V d 2: Vit chng trnh s dng cc ngt thit k mt h thng bo ng to m thanh

400 Hz trong vng 1 giy (s dng mt loa c ni vi chn P1.7) mi khi b cm bin t ca (ni
vi chn INT0\) to ra mt s chuyn trng thi t mc cao xung mc thp.
Cam bien
1s
8051
INT0
Ca ong
Ca m
Cam bien = 0
P1.7
Cam bien =
LOA
440 Hz
P1.7
2,5 ms
7404
Ca ra vao
Gii
ORG
ORG
LJMP
ORG
LJMP
000BH
LJMP
ORG
LJMP
ORG
0000H
MAIN
0003H
EX0ISR
T0ISR
001BH
T1ISR
0030H
MAIN:
SETB
MOV
MOV
SJMP
EX0ISR:
MOV
SETB
SETB
SETB
SETB
RETI
T0ISR:
CLR
DJNZ
CLR
CLR
LJMP
SKIP:
MOV
MOV
SETB
EXIT:
RETI
IT0
TMOD, #11H
IE, #81H
$
R7, #20
TF0
TF1
ET0
ET1
TR0
R7, SKIP
ET0
ET1
EXIT
;im nhp reset.

;Lnh nhy n ISR ngt ngoi 0
;Ngt ngoi kch khi cnh m.
;Chn ch 1 cho Timer 0, 1.
;Cho php ngt ngoi 0.
;ISR ca ngt ngoi 0.
;20 ln x 50000 s = 1s.
;Buc Timer 0 ngt.
;Buc Timer 1 ngt.
;Cho php ngt Timer 0.
;Cho php ngt Timer 1.
;Dng Timer 0.
;Kim tra 20 ln (1 giy).
;Kt thc pht m nu .
TH0, #HIGH(-50000) ;nh thi 0,05 s.

TL0, #LOW(-50000)
TR0
Gio trnh Vi x l.
;Kt thc ISR ca ngt Timer 0.

196

T1ISR:
CLR
MOV
MOV
SETB
RETI
END

TR1
;Dng Timer 1.
TH1, #HIGH(-1250) ;nh thi 1,25 ms.
TL1, #LOW(-1250)
TR0
;Kt thc ISR ca ngt Timer 1.
;Kt thc chng trnh.

vic khc. Vic thay th ny khng nh hng g n vic iu khin hot ng ca loa pht ra m
thanh theo tn hiu t b cm bin ca m. V c sau mi ln c tn hiu tc ng t cm bin th
nhng cng vic s b tm dng (ngt ngoi 0 xut hin) CPU thc hin vic iu khin pht ra
m thanh ti loa trong mt khong thi gian xc nh ri quay v thc hin tip nhng cng vic .
Gii php cho v d ny l s dng ba ngt: ngt ngoi 0 (b cm bin ca), ngt Timer 0 (m
hiu 400Hz) v ngt Timer 1 (nh thi 1s).
Chng trnh gm nm phn phn bit: v tr cc vect ngt, chng trnh chnh v ba trnh
phc v ngt. Cc v tr vect ngt cha cc lnh LJMP chuyn iu khin n cc trnh phc v
ngt tng ng. Chng trnh chnh bt u a ch 0030H ch cha bn lnh. Lnh SETB IT0 cho
php ng vo ngt ghp vi b cm bin ca c kch khi cnh m.
Lnh MOV TMOD,#11H xc nh ch hot ng ca c hai b nh thi l ch nh thi
16 bit. Ch c ngt ngoi 0 c php bt u (lnh MOV IE,#81H) do iu kin ca m l iu kin
cn phi c trc khi mt ngt no c chp thun. Cui cng lnh SJMP $ t chng trnh vo
vng lp khng lm g. Khi iu kin ca m c pht hin (bng s chuyn trng ti t mc cao
xung mc thp chn INT0\), ngt ngoi 0 c to ra.
Trnh phc v cho ngt ngoi 0, EX0ISR, bt u bng vic np hng s 20 cho R7, ri set c
trn ca c hai b nh thi bng 1 buc cc ngt do b nh thi xut hin. Tuy nhin cc ngt do
b nh thi s ch xut hin khi cc bit tng ng trong thanh ghi IE c cho php. Hai lnh k tip
SETB ET0 v SETB ET1 cho php cc ngt do b nh thi. Cui cng trnh phc v cho ngt ngoi
0, EX0ISR, kt thc bng lnh RETI tr v chng trnh chnh.
B nh thi 0 dng to ra khong thi gian nh thi 1s v b nh thi 1 dng to ra m
hiu 400Hz. Sau khi trnh phc v cho ngt ngoi 0, EX0ISR, kt thc th cc ngt do b nh thi lp
tc c to ra (v c chp nhn sau khi thc thi mt lnh SJMP $). Da vo th t trong chui
vng nn ngt do b nh thi 0 s c phc v trc tin. Khong thi gian nh thi 1s c to ra
bng cch lp trnh lp li 20 ln thi gian nh thi 50000s (20 x 50000s = 1s). Thanh ghi R7
hot ng nh l mt b m.
Trnh phc v ngt T0ISR hot ng nh sau: trc tin b nh thi 0 c iu khin ngng
hot ng v R7 c gim i mt n v. K n TH0/TL0 c np li bi gi tr (-50000), sau
b nh thi 0 c iu khin hot ng tr li v trnh phc v ngt c kt thc. ln ngt th 20,
R7 c gim xung 0 (1s tri qua). Cc ngt do c hai b nh thi c v hiu (lnh CLR ET0
v CLR ET1) v trnh phc v ngt kt thc. Khng cn ngt do b nh thi to ra na cho n khi
iu kin ca m xut hin mt ln na. m hiu 400Hz c lp trnh bng cch s dng ngt do b
nh thi 1. Tn s 400Hz yu cu chu k l 2500s, trong c 1250s mc cao v 1250s mc
thp. Trnh phc v ngt cho b nh thi 1 ch n gin np gi tr (-1250) cho TH1/TL1, sau ly
b bit ca port kch loa v ri kt thc trnh phc v ngt.
Gio trnh Vi x l.
197
V d 3: Ngt ngoi kch khi mc thp - Cho mch in nh hnh v. Chn INT0\ c ni vi
mt cng tc bnh thng mc cao, mi khi chn ny c mc thp (nhn cng tc) th iu khin bt
LED (bnh thng th LED tt). Khi LED c bt th phi sng trong mt khong thi gian (vi
trm s) trc khi tt, khi cng tc c nhn v gi th LED phi sng lin tc.
Gii
ORG
LJMP
ORG
CLR
MOV
DJNZ
SETB
RETI
ORG
MAIN:
CLR
MOV
SJMP
END
0000H
MAIN
0003H
P1.3
R3, #255
R3, $
P1.3
0030H
TCON.0
IE, #81H
$
Gio trnh Vi x l.
;im nhp reset.

;Bt LED.
;Thi gian LED duy tr trng thi sng l
;255.TMachine.
;Tt LED.
;Ngt ngoi 0 kch khi mc thp.
;Kt thc chng trnh
198
V d 4: Ngt ngoi kch khi cnh m - Cho mch in nh hnh v. Chn INT0\ c ni vi
mt cng tc bnh thng mc cao, mi khi chn ny c s chuyn trng thi t mc cao xung mc
thp (nhn cng tc) th iu khin bt LED (bnh thng th LED tt). Khi LED c bt th phi
sng trong mt khong thi gian (vi trm s) trc khi tt, khi cng tc c nhn v gi th LED
khng c sng lin tc.
Gii
ORG
LJMP
ORG
CLR
MOV
DJNZ
SETB
RETI
ORG
MAIN:
SETB
MOV
SJMP
END
0000H
MAIN
0003H
P1.3
R3, #255
R3, $
P1.3
0030H
TCON.0
IE, #81H
$
;im nhp reset.

;Bt LED.
;Thi gian LED duy tr trng thi sng l
;255.TMachine.
;Tt LED.
;Ngt ngoi 0 kch khi cnh m.
;Kt thc chng trnh
VII. PHN BI TP:

Bi 1: Vit on lnh dng ngt Timer to sng vung f=2KHz ti P1.7. (fOSC=12MHz).
Bi 2: Vit on lnh dng ngt Timer to sng vung f=200Hz ti P1.6. (fOSC=12MHz).
Bi 3: Vit on lnh dng ngt Timer to ng thi hai sng vung 1KHz v 50Hz ti P1.0
v P1.1. (fOSC=6MHz)
Bi 4: Vit on lnh ly mt chui data cha trong Ram ngoi bt u t a ch 6200H n
a ch 62FFH v xut ra Port 1, mi ln xut cch nhau 50ms. S dng ngt Timer. fOSC=12MHz.
Bi 5: Vit on lnh nhp data t thit b ngoi kt ni vi 8051 qua Port 1, mi ln nhp cch
nhau 5s, data nhp v c ghi vo vng Ram ni bt u t a ch 50H n a ch 5FH. Bit rng
sau khi ghi vo nh cui cng th tr li ghi vo nh u. S dng ngt Timer. fOSC=12MHz.
Bi 6: Vit on lnh pht lin tc chui s t 0 n 9 ra port ni tip theo ch UART 8 bit,
2400 baud. S dng ngt serial. fOSC=12MHz.
Gio trnh Vi x l.
199
Bi 7: Vit on lnh ch nhn data t mt thit b ngoi gi n 8051 qua port ni tip (ch
UART 8 bit, 19200 baud). Nu nhn c k t STX (02H) th bt sng LED, nu nhn c k t
ETX (03H) th tt LED, bit rng LED c iu khin bng ng P1.3 (LED sng khi bit iu khin
bng 1). S dng ngt serial. fOSC=11,059MHz.
Bi 8: Vit on lnh ch nhn 1 xung cnh xung a vo chn /INT0 (P3.2), khi c xung th
nhp data t Port 1 v pht ra port ni tip ch UART 9 bit 4800 baud, bit th 9 l bit parity l.
fOSC=6MHz.
Bi 9: Vit on lnh m s xung a vo chn /INT1 (P3.3) v iu khin relay thng qua
chn P3.0 (relay ng khi P3.0 bng 1), ct s m vo nh 40H ca Ram ni, nu s m cha n
100 th ng relay, nu s m t 100 th ngt relay.
Gio trnh Vi x l.
200

8051 - DH Cong Nghiep TP HCm-1

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8051 - DH Cong Nghiep TP HCm-1

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Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

Kh nng lu tr v phc hi d liu.

CPU (Central Processing Unit): n v x l trung tm.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

IR (Instruction Register): thanh ghi lnh.

Thao tc gii m thc hin lnh:

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

S lc v cu trc v phn loi ROM RAM:

Phn loi mt s loi ROM:

Phn loi mt s loi RAM:

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

V d: B nh c m s 27256, dung lng ca b nh l bao nhiu ?

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

Cu trc phn cng

Byte, Word, Double word,

VIII. MINH HA KIN TRC CA MT H VI IU KHIN:

WDT (Watch-Dog Timer): B nh thi Watch-Dog.

Bien soan: Pham Quang Tr

Chng 1: Gii thiu chung v b vi x l.

Trng H Cng nghip Tp.HCM.

Program Memory: B nh chng trnh.

Giao trnh Vi x ly.

Bien soan: Pham Quang Tr

Chng 2: Phn cng chip vi iu khin 8051.

Trng H Cng nghip Tp.HCM.

2. Cc phin bn ca chip vi iu khin 8051:

8052 l mt phin bn ca h 8051. 8052 c tt c cc thng s k thut ca 8051, ngoi ra cn

Bin son: Phm Quang Tr

Chng 2: Phn cng chip vi iu khin 8051.

Trng H Cng nghip Tp.HCM.

ROM trn chip (KB)

RAM trn chip (byte)

B vi iu khin AT8951 ca Atmel Corporation:

B vi iu khin DS5000 ca Dallas Semiconductor:

Mt phin bn ph bin khc na ca 8051 l DS5000 ca hng Dallas Semiconductor. B nh

Bin son: Phm Quang Tr

Chng 2: Phn cng chip vi iu khin 8051.

Trng H Cng nghip Tp.HCM.

ca my tnh PC. y l mt im mnh rt c a chung. Ngoi ra, NV-RAM cn c u vit l cho

im c bit l cc chip c ch T theo sau k hiu 5000 c ngha l chip c thit k

B vi iu khin P89V51xx ca Philips Corporation:

y l mt phin bn ci tin s dng CPU l b vi iu khin 80C51 vi nhiu tnh nng vt

Bin son: Phm Quang Tr

Chng 2: Phn cng chip vi iu khin 8051.

Trng H Cng nghip Tp.HCM.

- CPU (Central Processing Unit): n v x l trung tm tnh ton v iu khin qu

Bin son: Phm Quang Tr

Chng 2: Phn cng chip vi iu khin 8051.