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Introduction To SDH
Introduction To SDH
Introduction To SDH
Hierarchy (SDH)
z Multiplex levels:
2.048 Mbit/s
8.448 Mbit/s
34.368 Mbit/s
139.264 Mbit/s
Plesiochronous Multiplexing
North
America
Europe
274.176 M bit/s
139.264Mbit/s
397.2 M bit/s
x4
97.728 M bit/s
x3
x6
32.084 M bit/s
44.738 M bit/s
x5
x7
6.312 M bit/s
6.312 Mbit/s
x4
x 4
34.368 Mbit/s
x 4
8.448 M bit/s
x4
x 4
1.544 M bit/s
2.048 M bit/s
PDH Multiplexing
8 Mbi t/s
2
D
M
E
3 4 Mb it/s
3
D
M
E
4
D
M
E
64
2
D
M
E
3
D
M
E
PDH Add/Drop
What is SDH?
SDH Rates
155.52 Mbit/s
STM-4
622.08 Mbit/s
STM-16
2588.32 Mbit/s
STM-64
9953.28 Mbit/s
SDH Hierarchy
AUG
AU-4
139264 kb/s
VC-4
C-4
x3
xN
x1
x3
TU-3
TUG-3
AU-3
HOP
VC-3
C-3
VC-3
44736 kb/s
(DS3)
34368 kb/s
x7
x7
x1
TUG-2
TU-2
VC-2
C-2
TU-12
VC-12
C12
x3
6312 kb /s
(DS2)
LOP
204 8 kb/s
x4
TU-11
VC-11
C-11
154 4 kb/s
(DS1)
xN
STM-N
x3
AUG
AU-4
VC-4
x7
TUG-3
x3
TUG-2
TU-12
VC-12
C-12
Section overhead
Pointer processor
HO path overhead
Pointer processor
LO path overhead
PDH
SDH
VC-4 POH
AU-4 PTR
VC-4
VC-4
AU-4 PTR
SOH
Container-4
AUG
AU-4
VC-4
AUG
AUG
STM-N
Logical association
Physical association
T1517990-95
NOTE Unshaded areas are phase aligned. Phase alignment between the unshaded and shaded areas is defined by the
pointer (PTR) and is indicated by the arrow.
z
z
z
z
125 us
TS0 TS1
261 N
Section overhead
SOH
3
4
9 rows
Section overhead
SOH
9
T15180 00-9 5
z SDH will still work if there are two different clocks in the
network and the network becomes asynchronous.
z Pointers are used adjust for the new frequency.
Pointer
processing
ocurrs here
STM -N
S TM -N
NE #1
STM -N
N E #2
f +f
S T M -N
N 2 6 1 b yt e s
N 9
RS OH
V C -4 -X c
A U -n P T R s
J1
B3
M SO H
C2
G 1
F2
F ix e d
st u f f
C - 4 -X c
H4
F3
K3
N1
1
X- 1
X 260
X 2 6 1 b y te s
P TR
P o in t e r
T 1 5 18 2 3 0 - 95
86 Columns
TUG-2
TUG-2
TUG-3
(7 TUG-2)
TU-1
PTRs
TU-2
PTR
Fixed stuff
Fixed stuff
..
POH
..
POH
POH
..... ...
VC-2
VC-1
..
..
PTR Pointer
3 VC-12s or 4 VC-11s
in 1 TUG-2
T1518100-95
Tributary units
V5
RR R RR RR R
32 bytes
RR R RR RR R
J2
C1 C2 O O O O R R
32 bytes
R RR RR RR R
140
bytes
N2
C1 C2 O O O O R R
32 bytes
R RR RR RR R
K4
C 1 C2 R R R R R S 1
z V5 byte:
S2 D D D D D D D
31 bytes
R RR RR RR R
T1523020-96
Data bit
R
O
S
C
BIP-2
1
REI
3
RFI
4
Signal Label
6
7
RDI
8
9 Bytes
A1 A1 A1 A2 A2 A2 J0
B1
E1 E1
F1
D1
D2
D3
B2 B2 B2 K1
K2
D4
D5
D6
D7
D8
D9
D10
D11
D12
RSOH
9 rows
S1 Z1 Z1 Z2 Z2 M1 E2 E2
MSOH
J1
J1
B3
B3
C2
C2
G1
G1
F2
9 rows
F2
H4
H4
Z3
F3
Z4
K3
Z5
N1
VC-12 overhead
old VC-12 OH
new VC-12 OH
VC-12
VC-12
V5
V5
125 us
35 by tes
J2
125 us
35 by tes
J2
125 us
35 by tes
Z6
125 us
35 by tes
N2
125 us
35 by tes
Z7
125 us
35 by tes
K4
125 us
35 by tes
125 us
35 by tes
V5 Byte
BIP-2
1
REI
RFI
Signal Label
5
RDI
7
Byte
A1
comments
First framing byte A1:11110110
A2
comments
Synchronistion status marker byte
S1 Byte: bit 5 -8
0000
Quality unknown
0010
Traceable to PRC G.811
0100
Traceable to Transit G.812
1000
Traceable to Local G.812
1011
Derived from SETS
1111
Don't use for Synchronisation.
Other bytes are reserved.
Regen OH
Regen OH
AU-4
9 rows
AU-4
9 rows
Mux OH
Mux OH
9 column s
261 co lumns
9 columns
26 1 columns
AU-4
AU-4
Regen OH
Regen OH
VC-4
9 rows
Path
Mux OH
VC-4
Payload
9 rows
Path
T U-12
Mux OH
OH
Path OH
OH
Payload
9 column s
261 co lumns
9 columns
26 1 columns
VC-4
Payload
Byte
B1
B2
#1,2,3
B3
V5
comments
Bit interleaved parity - 8 bits for entire previous frame
before scrambling.
Three bytes of a 24 bit multiplex section bit interleaved
parity - Calculated over the previous STM-1 frame
excluding the first three rows of the SOH before
scrambling.
Bit interleaved parity - 8 bits for entire previous frame
before scrambling.
The BIP is calculated over the previous VC-4.
VC-12 path bit interleaved parity - 2 bits for previous frame
The BIP is calculated over the previous VC-12 frame
including VC-12 path overheads but excludes V1, V2, V3.
Byte
D1 to
D3
comments
Regenerator section data communications channel
(DCC)
The D1 to D3 bytes are a 192 kbit/s DCC channel.
D4 to
D12
comments
64 kbit/s user channel.
The FLX150/600 supports either G.703 co-directional or
contradirectional interface.
This user channel can be passed through at a
regenerator.
F2
Z3 (F3)
Z6 (N2)
Byte
J0
comments
Regenerator section trace use is not defined in ITU-T.
Trace value can be entered for section id between
national boundaries.
J1
J2
Byte
M1
comments
Multiplex section remote error indication (MS
REI)
com m en ts
Signal label: This byte indicates the composition of the
VC-4
.
z Path Status
Byte
G1
comments
Path status byte. This byte is sent from the receiver
back to the originator.
z Multiframe Pointer
Byte
H4
comments
VC-4 multiframe pointer.
Indicates the multiframe position indicator for the VC-12
Comments
Remote error indication (REI): set to one if one
or more error is detected at receiver in the BIP-2.
Standard implementation on FLX and FLM
Remote failure indication (RFI). Set to one if a
failure is declared .
VC-12 signal label.
VC-12 path remote defect indication (RDI) Set to
1 if an AIS or a signal failure condition is
received.
SDH layers
SDH
LPA
Low er O rder
Pat h
Lay er
Cr os s
Connec tion
LPT
LPC
HPA
Higher O rder
Pat h
Lay er
Cross
Connec tion
HPT
H PC
M SA
M ultiple xer
S ection
Lay er
M ST
RSA
Regenerator
S ection
Lay er
P hys ica l
M edia
Lay er
R ST
S PI
PPI
Termination points
A DM
1 40 Mb it/s
14 0 M bi t/s
A DM
S TM-1 ring
A DM
A DM
140 Mbit/ s in
Se ction O H out
Layers - Example
V C - 12 P at h r e m a in s u n in te r r u p te d b e tw e e n te r m in a tio n p o in ts
M u x s e ct io n
M ux
s e ct io n
M u x se ct io n
R egen
s e c tio n
R egen
s e c tio n
E1
E1
AD M
S T M -1
r in g
A DM
Te rm in a l
D X C 4 /4
ST M - 1
ST M-4
E1
L ow e r O rd e r
P a th
L a ye r
H ig h e r O rd e r
P a th
L a ye r
M u ltip le x
S e c tio n
L a ye r
R eg e ne r ato r
S e c tio n
L a ye r
P hy s ic a l
in ter fac e
L a ye r
V C - 12
te rm in atio n
V C -1 2
X -c o n ne c t
V C -4
X - c on n ec t
R e ge n
V C -1 2
T e rm in atio n
STM Physical
Media
Layer
R eg en er ator
Sectio n
Layer
Mu ltiplexer
Sectio n
Layer
H igher Order
Path
Layer
LO S
LOS
LO F
LOF
RS-BIP
RS-BIP
MS-AIS
MS-BIP
MS-AIS
MS-BIP
MS-RDI
AU-AIS
MS-RDI
AU-AIS
AU-LO P
AU-LOP
VC-4 BIP
VC-4 REI
VC-4 RDI
VC-4 BIP
VC-4 RE I
VC-4 RDI
VC-4 LOM
VC-4 LOM
E1
Lo wer Order
Path
Layer
PDH Physical
In terface
Layer
VC-12 AIS
VC-12 AIS
VC-12 LO P
VC-12 BIP
VC-12 LOP
VC-12 BIP
VC-12 REI
VC-12 RFI
VC-12 RDI
VC-12 REI
VC-12 RFI
VC-12 RDI
LO S
LOS
ADM
STM-1
ring
ADM
Signalling interactions
Re g e n
SPI
Se c tio n
RST
M u ltip le x Se c t io n
N o te 1
M ST
H ig h e r O rd e r P a t h
M SA
HPO M
H UG
H PC
Lo w e r O rd e r P a t h
HPT
HPA
LP O M
LU G
LO S
LP C
L PT
LP A
D e te c ti o n
"1 "
LO F
G e n e ra ti o n
R S- B IP E r ro r ( B 1 )
"1 "
R e g e n s ig n a l p a s se d
"1 "
th ro u g h
"1 "
M S- A I S
M S- Ex c
Er ro r (B 2 )
M S- B IP E rr o r ( B 2 )
A U - A IS
A l a rm In d i c a t o
i n Si g n a l
F a r e n d b l o c k e rr o r
F ER F
F a r e n d re c e i v e f a i l u r e
LO S
LO F
Lo s s of s ig na l
L o s s o f fr a m e
LO M
LO P
L o ss o f m u l t i fra m e
L o s s o f p o i n te r
T IM
SL M
U N EQ
M S- FE R F
In s e rti o n o f A IS s i g n a l
A IS
F EB E
T ra c e i d e n ti f i e r m i s m a tc h
Si g n a l l a b e l M i s m a tc h
Un e q u p
i p e d si g n a l p e r G 7 0 9
M S- FE R F
"1 "
A U - A IS
A U - LO P
H O P a t h s ig n a l p a s s e d
H O V C w it h
PO H a n d
H O u n e q u ip p e d
U n u se d
H PC
th r o u g h
u n s p e c if ie d
O u t p u t / HP- UN EQ
"1 "
p a y lo a d
s ig n a l
HP- UN EQ
"1 "
H P - TIM
H P - SL M
H P -B IP E rr o r ( B 3)
H P - FE B E
TU - A IS
H P - FE R F
H P - FE R F
H P - FE B E
"1 "
TU - A IS
U n u se d
H P - LO M / TU -L O P
LP C
O u t p u t / L P -U N EQ
L O P a t h s ig n a l p a s s e d t h r o u g h
L O VC
w it h P O H a n d
L O u n e q u ip p e d
u n s p e c if ie d
p a y lo a d
"1 "
sig n a l
LP - U N EQ
"1 "
LP - TIM
LP - SLM
L P -B IP Er ro r ( V 5 )
LP - FE B E
LP - FE R F
LP - FE R F
LP - FE B E
SD H M a in t e n a n c e
Sig n a l In t e r a c t io n
G .7 8 2 1 0 N o v e m b e r 1 9 92
Select
A
STM-N in
PDH in
Ext ref
Select
B
Select
C
Output clk
Sys clk
SETG
PRC
PRC
st
st
1 NE
1 NE
nd
nd
2 NE
2 NE
Timing
recovery
th
th
N NE
G.812
clock
N NE
G.812
clock