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Verilog HDL
Nguyn H Giang

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Ni dung
1

Gii thiu chung v Verilog

Mt s quy c

3
4

Module

Port

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Ni dung
1

Gii thiu chung v Verilog

Mt s quy c

3
4

Module

Port

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Gii thiu chung v Verilog

Verilog l mt ngn ng m t phn cng c dng

rng ri trong thit k mch s
Verilog thng c dng m t thit k 4 dng

Thut ton (cc lnh nh: if, case, for, while),

Chuyn i thanh ghi,

Cc cng kt ni

Chuyn mch.

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Ni dung
1

Gii thiu chung v Verilog

Mt s quy c

3
4

Module

Port

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Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Khong trng v ch thch

Blank space (\b), tabs (\t) v dng mi (\n).

Chng c b qua tr khi dng tch bit
cc ch thch, nh danh, s, chui, t kha,
Khong trng khng c b qua trong chui
Verilog cho php ch thch theo mt hng v
nhiu hng

// cho phep chu thich tren 1 hang

/* cho phep chu thich

tren nhieu hang */

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Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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nh danh v t kha

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nh danh l tn gn cho i tng c tham chiu

trong thit k. nh danh c th bao gm c cc k t s
v du gch di ( _ ), du $ nhng phi bt u bng
k t ch hoc du gch di
T kha: l dng c bit dnh ring nh ngha cc
cu trc ngn ng, c vit bng ch thng
V d

reg example; // reg la tu khoa, example la dinh danh

input a ;
// input la tu khoa, a la dinh danh

Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Cch biu din s

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S thc: trong khai bo dng t kha real ( VD : real a,b,c )

S nguyn: Nu chng cha nhng s m khng nh r kch
thc th kch thc mc nh l 32 bit, trong khai bo dng t kha
integer
V d :
module module_songuyen();
integer a, b, c;
initial
begin
a = 12h234; // a kich thuoc 12 bit
b = 342;
// b kich thuoc 32 bit
c = -39;
// c kich thuoc 32 bit
end
endmodule

S c c s

L nhng s nguyn nhng c khai bo dng nhng c s nht

nh, v d h 8 (octal), h 16 (hexadecimal), h 10 (decimal), h nh
phn (binary)
S c c s c khai bo nh sau:
<integer_name> = <bit_size><base_number><value>;
Trong :
<integer_name> l tn ca s nguyn m ta cn dng,

<bit_size> l s bit nh phn biu din s nguyn,

<base_number> l c s. Theo o l bt phn, h l h thp lc

phn, d la h thp phn, b l cho h nh phn.

<value> gi tr ca s nguyn
V d
a = 4b1001;
// biu din s nh phn 4b1001 = 4d9

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b = 5o24;
c = 5d24;

// biu din bt phn

// biu din h mi

S biu din thang thi gian

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Thi gian m phng trong verilog c khai bo vi t

kha time. n v cho thi gian c khai bo trong b
nh hng bin dch. Khai bo thang thi gian tuan th
c php sau:
timescale <ref_time>/<precision>
Trong : <ref_time> v <precision> phi l nhng gi tr
nguyn nh 1, 10, hay 100 tuy nhin n v thi gian
c php khai bo cng vi nhng gi tr nguyn ny
l fs, ps, ns, us, ms, s
V d:
timescale 100us/1ns;
C ngha l : nu khai bo #10 th thi gian tr
thc l 10*100 = 1000us

Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Kiu d liu

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D liu trong Verilog kiu ny c loi gi tr sau y:

0 biu din logic 0 hoc iu kin sai

1 biu din logic 1 hoc iu kin ng

x biu din logic cha bit

z biu din trng thi tng tr cao

Verilog cho php khai bo hai kiu d liu l reg v net.
Reg (register) l mt phn t lu tr, cho php gi tr lu
tr trong kiu d liu ny. Reg c dng cho cc cu
lnh cu khi always v initial

Kiu d liu

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Kiu d liu thuc nhm net (wire, wand, wor)c

dng nhiu nht l kiu wire thng dng biu din
kt ni, gi tr trn wire c cp nht lin tc,

wire net1;

wire [2:0] net2;

Reg [3:0] a1, a2;

Trong qu trnh m phng, nu khng c gi tr no
c gn vo nhng i tng c khai bo kiu reg
th gi tr mc nh l X (khng xc nh), tng t vi
kiu wire s l Z,

Wire

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Wire m t vt liu ng dy dn trong mt mch v

c dng kt ni cc cng hay cc module. Gi tr
cua wire c th c, nhng khng c gn trong hm
(function), hoc khi (block).
Wire khng lu tr gi tr ca n nhng vn phi c
thc thi bi mt lnh gn k tip hay bi s kt ni wire
vi ng ra ca mt cng hoc mt module
C php:
wire[msb:lsb] bien_wire;
V d:
wire temp;
wire [7:0]a,b;

Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Vector

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Net hoc reg c th c khai bo di dng vector (

rng nhiu bit). Nu rng bit khng c ch r, mc
nh l 1 bit
V d
Wire a;
//1 bit
Wire [7:0] test; //8 bit
Reg b;
// 1 bit

Vector c th c vit l [high#:low#] hoc [low#:high#]

nhng s bn tri lun l bit ln nht ca vector
V d:
a [4:0]; // ng
a [0:4];// sai

Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t

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Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t bit - wise

So snh tng bt hai ton hng

~(NOT), &(AND),^~ ( XNOR )

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Ton t bit - wise

V d :
// x = 4b1010 , y = 4b1101
// z = 4b10x1
~x
// = 4b0101
x&y
// = 4b1000
x|y
// = 4b1111
x^y
// = 4b0111
x~^ y
// = 4b1000
x&z
// = 4B10x0

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Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t logic

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Ton t tr v gi tr 0 hoc 1. Chng c th lm

vic trn biu thc, s nguyn, hoc nhm bit
!(NOT), &&(AND), ||(OR)
Ton hng l vector khc 0 c xem nh 1
Nu bt k bit no ca ton hng c gi tr x hay
z th ton hng c xem nh x

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Ton t logic

V d:

// a = 3 , b = 0;
// m= 2b0x , n = 2b10
a && b // ( logic 1 && logic 0 ) 0
a || b // ( logic 1 || logic 0 ) 1
!a
// ( !logic1 0 )
( a==2 ) && ( b==0 ) // ( logic 1 && logic 0 )
( m && n ) // ( x && logic 1 ) x

Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t kt ni / nhn bn

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Kt ni {a1, a2, , aN}

Nhng hng s khng bit kch thc khng th thc
hin kt
ni
Nhn bn {number {a1, a2, , aN}}
V d
assign d[7:4] = {d[0], d[1], d[2], d[3]};
assign d = {d[3:0], d[7:4]};
a = {3{4b1011}};
// 12b1011 1011 1011
{3{1b1}} // 111
{3{a}} // {a, a, a}

Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t dch

Dch tri <<, dch phi >>

V d :
// x = 4b1100
y = x >> 1; // y = 4b0110
y = x << 1 ; // y = 4b1000
y = x << 2 ; // y = 4b0000

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Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t iu kin

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Bt iu kin ? Bt ng : bt sai
Xt bt iu kin
Nu ng ( logic 1 ) bt ng c xt
Nu sai ( logic 0 ) bt sai c xt
Nu kt qu l x th xt c bt ng v bt sai. So snh
tng bit ca kt qu 2 biu thc, nu kt qu ging nhau
tr v kt qu ,nu c bit khc nhau th tr v x
V d :
wire [15:0]b = a? data : 16bz;
/* a = 1 th data c gn vo b
a = 0 th b tng tr cao
a = x th b l x */

Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t quan h

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So snh 2 ton hng v tr v 0 hoc 1

<, <=, >, >=
Nu 1 trong s cc ton hng c bit c gi tr x hoc z
th kt qu tr v l x
V d :
// a = 4 , b = 3
// x = 4b1010 , y = 4b1101 , z = 4b1xxx
a <= b
// = 0
a > b // = 1
y >= x
// = 1
y < z // = x

Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t bng

LOGO

== v !=
Gi tr x v z tng t nh ton t quan h
Kt qu c th l x
=== v !==
So snh tng bit
x === x, z === z, x !== z
Kt qu lun xc nh (0 hoc1)
Nu kch thc 2 ton hng khng bng nhau th cc bit
0 s c thm vo nhng bit trng s cao ca ton
hng c kch thcnh

Ton t bng

V d :
// a = 4 , b = 3
// x = 4b1010 , y = 4b1010
// z = 4b0xxz , m = 3bxxz , n = 4b0xxx
a == b // 0
x != y // 1
x == z // x
z === m // 1
z === n // 0
m !== n // 1

LOGO

Ton t

Ton t bit wise

Ton t logic
Ton t kt ni
Ton t nhn bn
Ton t dch
Ton t iu kin
Ton t quan h
Ton t bng
Ton t s hc

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Ton t s hc

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Thc hin cc php tnh s hc.

+, -, *, /, %.
Bt k bit no trong ton hng l x hoc z th kt qu l x
Kch thc kt qu :

Php nhn th kch thcktqubng tng kch thc

2 ton hng

Cc php ton khc bng chiu di ln nht ca ton

hng

Ton t s hc

V d
a = 4b0011 ; b = 4b0100;
d=6;e=4;
m = 4b101x ; n = 4b1010
a * b // = 4b1100
d / e // = 1
a + b // = 4b0111
a - b // = 4b0001
m + n // = 4bx
13 % 3 // = 1
16 % 4 // = 0

LOGO

Mt s quy c ca Verilog

Khong trng v ch thch

nh danh v t kha
Cch biu din s
Kiu d liu
Vector
Ton t
Php gn

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Php gn

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2kiuphpgn:
kiublocking:[tnbin]=[biuthc];
kiunon-blocking:[tnbin]<=[biuthc];
Kiublocking:cclnhthchintunt,thc
hinxonglnhgnnymithchinlnhgnk
tip
Kiunon-blocking:cclnhgncthchin
songsong

Php gn

V d 1:
initial begin
#10 a = 0 ; #11 a = 1 ; #12 a = 0 ; #13 a = 1;
end
initial begin
$monitor("TIME = %tA = %b ",$time, a);
#50 $finish ;
end

TIME = 0 A = x
TIME = 10 A = 0
TIME = 11 A = 0
TIME = 12 A = 0
TIME = 13 A = 0
TIME = 21 A = 1
TIME = 33 A = 0
TIME = 46 A = 1

LOGO

Php gn

V d 2 :
initial begin

#10 b <= 0 ; #11 b <= 1 ; #12 b <= 0 ; #13 b <= 1;

end
initial begin
$monitor("TIME = %t B = %b ",$time, b) ;
#50 $finish ;
end

TIME = 0 B = x
TIME = 10 B = 0
TIME = 11 B = 0
TIME = 12 B = 0
TIME = 13 B = 0
TIME = 21 B = 1
TIME = 33 B = 0
TIME = 46 B = 1

LOGO

Php gn

V d 3 :
initial begin
c = #10 0 ; c = #11 1 ; c = #12 0 ; c = #13 1 ;
end
initial begin
$monitor("TIME = %t C= %b ",$time, c);
#50 $finish ;
end

TIME = 0 C = x
TIME = 10 C = 0
TIME = 11 C = 0
TIME = 12 C = 0
TIME = 13 C = 0
TIME = 21 C = 1
TIME = 33 C = 0
TIME = 46 C = 1

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Php gn

V d 4 :
initial begin
d <= #10 0 ; d <= #11 1 ; d <= #12 0 ; d <= #13 1 ;
end
initial begin
$monitor("TIME = %t D= %b ",$time, d);
#50 $finish ;
end

TIME = 0 D = x
TIME = 10 D = 0
TIME = 11 D = 1
TIME = 12 D = 0
TIME = 13 D = 1
TIME = 21 D = 1
TIME = 33 D = 1
TIME = 46 D = 1

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Ni dung
1

Gii thiu chung v Verilog

Mt s quy c

3
4

Module

Port

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Cu trc chung mt chng trnh dng Verilog

//khai bo module
Module module_name(tn bin I/O); //module_name
trng tn file.v
Input [msb:lsb] bien;
Output [msb:lsb] bien;
Inout [msb:lsb] bien;
Reg [msb:lsb] bien reg;
Wire [msb:lsb] bien wire;
//khai bao khoi always hoac initial
cac lenh
endmodule

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Module

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Module lun bt u bng t kha module. Tn module, danh sch

port, khai bo port phi hin din trc tin trong nh ngha
module.
Danh sch port v khai bo port ch hin din khi module c port
tng tc vi mi trng bn ngoi
5 thnh phn trong module l:

Cc khai bo bin

Cc pht biu lung d liu

Th hin qua cc module thp hn

Cc khi hnh vi

Task hoc function

Cc thnh phn ny l ty chn,c th bt k ni u trong
module khng cn theo th t.
Kt thc bng t kha endmodule

Module
V d 1 :
// module co port
module nand_gate (c, a, b);
output c;
input a, b;
wire d;
and a1(d, a, b);
not n1(c, d);
endmodule

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Module
V d 2
//module ko co port
`timescale 1ns / 1ps
module test_bench;
reg A, B;
wire C;
nand_gate S (C, A, B);
initial
begin
$moniter("A = %b, B = %b, C = %b \n", A, B, C);
#10 A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
end
endmodule

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Ni dung
1

Gii thiu chung v Verilog

Mt s quy c

3
4

Module

Port

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Port

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Port cung cp giao din qua module c th giao tip

vi mi trng bn ngoi
Kiu ca port cng c khai bo mt cch c th:
c th l input, output hoc inout
V d:

module test1(a, b, c, d);

intput a, b;
output c;
inout d;
.

Port

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Nu mt cng no m nhiu hn 1 bit ta phi dng k

hiu [ ] ch ra rng ca bus
V d:

module example(a, b, c, d);

intput [7:0] a, b;
output c;
inout [4:0] d;

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Nguyn H Giang

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