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  • F. Lampiran 1. NAND-Latch Dan NOR-Latch

    Uploaded by

    MuhammadIkhsanRestiadi
    6 views2 pages
    The document describes 4 different types of flip-flops: 1. NAND-Latch and NOR-Latch which use NAND and NOR gates respectively to latch a value based on S and R inputs. 2. SR flip-flop with clock which uses a clock signal to latch the output based on S and R inputs. 3. D flip-flop with clock which uses SET, RESET and clock signals to latch the output based on the data input. 4. JK flip-flop with clock which uses J, K, reset and clock signals to toggle or maintain the output value.

    Original Description:

    PED3 - Lampiran

    Original Title

    Lampiran Ped 3

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    The document describes 4 different types of flip-flops: 1. NAND-Latch and NOR-Latch which use NAND and NOR gates respectively to latch a value based on S and R inputs. 2. SR flip-flop with clock which uses a clock signal to latch the output based on S and R inputs. 3. D flip-flop with clock which uses SET, RESET and clock signals to latch the output based on the data input. 4. JK flip-flop with clock which uses J, K, reset and clock signals to toggle or maintain the output value.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    6 views2 pages

    F. Lampiran 1. NAND-Latch Dan NOR-Latch

    Uploaded by

    MuhammadIkhsanRestiadi
    The document describes 4 different types of flip-flops: 1. NAND-Latch and NOR-Latch which use NAND and NOR gates respectively to latch a value based on S and R inputs. 2. SR flip-flop with clock which uses a clock signal to latch the output based on S and R inputs. 3. D flip-flop with clock which uses SET, RESET and clock signals to latch the output based on the data input. 4. JK flip-flop with clock which uses J, K, reset and clock signals to toggle or maintain the output value.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 2

    F.

    LAMPIRAN
    1. NAND-Latch dan NOR-Latch
    STEP
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10

    OUTPUT

    INPUT
    S
    0
    0
    1
    1
    0
    1
    0
    0
    1
    1

    R
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1

    NAND-Latch
    Q1
    Q2
    1
    1
    1
    0
    1
    0
    0
    1
    1
    1
    0
    1
    1
    0
    1
    1
    0
    1
    0
    1

    2. SRFF dengan Clock


    INPUT
    STEP
    CLOCK
    S
    1
    0
    0
    2
    1
    0
    3
    0
    1
    4
    1
    1
    5
    0
    1
    6
    1
    1
    7
    0
    0
    8
    1
    0
    9
    0
    1
    10
    1
    1

    R
    0
    1
    1
    1
    0
    0
    0
    0
    0
    1

    NOR-Latch
    Q1
    Q2
    0/1
    0/1
    1
    0
    0
    0
    0
    1
    0
    1
    0
    0
    1
    0
    1
    0
    0
    1
    0
    0

    OUTPUT
    Q1
    Q2
    0/1
    0/1
    0
    1
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0

    3. DFF dengan Clock


    STEP
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16

    SET
    0
    0
    0
    1
    1
    1
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1

    INPUT
    RESET CLOCK
    1
    0
    1
    1
    1
    0
    0
    1
    0
    0
    0
    1
    0
    0
    0
    1
    0
    0
    1
    1
    1
    0
    1
    1
    1
    0
    1
    1
    1
    0
    1
    1

    DATA
    1
    0
    1
    0
    0
    1
    1
    0
    1
    0
    0
    1
    1
    1
    0
    0

    OUTPUT
    Q1
    Q2
    1
    0
    1
    0
    1
    0
    0
    1
    0
    1
    0
    1
    0
    1
    1
    0
    1
    0
    0
    1
    0
    1
    0
    1
    1
    1
    1
    0
    1
    0
    0
    1

    4. JKFF dengan Clock


    STEP
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12

    RESET
    0
    0
    0
    0
    1
    1
    1
    1
    1
    0
    1
    1

    INPUT
    CLOCK
    0
    1
    1
    0
    0
    1
    0
    0
    0
    1
    1
    0

    J
    0
    0
    1
    1
    1
    1
    0
    1
    1
    1
    1
    1

    K
    0
    1
    0
    1
    0
    0
    1
    0
    1
    1
    1
    1

    OUTPUT
    Q1
    Q2
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    1
    0
    1
    0
    1
    0
    0
    1
    0
    1
    1
    0

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