C3181 B.EJB.Tech. DEGREE EXAMINATION, MAY/JUNE 2007. Fourth Semester (Regulation 2004) Eleetronies and Communication Engineering EC 1254— LINEAR INTEGRATED CIRCUITS (Common to B.E. (Part~Time) Third Semester Regulation 2008 ‘Time : Three hours Maxim: marks 4, St S$ 6 5 < OO Answer ALL questions, 2 PART A (19v9 = 9A marke) © Calculate the output current I of the current source 5e) ig. 1. Assume hee of transistor is very high and Ves = 0.6V. XS F Draw the cit ofa mage soures and-wsla fhe spcesion ara output current. ‘Two voltages +Viand +\bardJavailable. Using two operational amplifiers draw a circuit to compute (BSS Ve. Galeulate the earetth e circuit shown in Fig.2 > rae5. Explain how a frequency doubler can be realized using analog multiplier. 6. A PLL with a free running frequency of 1 KHz is connected to a variable frequeney oscillator. The frequency of oscillator is gradually increased_and when its frequency was 850 Hz the PLL got locked. The frequency of was decreased and it went out of lock for the oscillator frequency Caleulate the lock range and the capture range of the PLL. 7. The input to a sampling gate is a sine wave. Plot its ouput gl ‘without a hold capacitor. © 8. Sestethe reason for keeping the ntagraling ie Aen ere digital converter equal to that of mains supply vee) 16 V. Fora lad erent of 1 Ampere, altel) and output voltage is the power dissipated in the 10, Draw the internal diagram of @) @ : CS its equivalent circuit and derive an expression for its gain. (16) 2 csist12. (a) (i) In the cireuit given in Fig. 3, show that the input resistance = S Gi) Calculate the current through Ry Lp amr Fig, @) 1K WS & or iw the circuit diagram of a second order Butterworth active ) lowpass filter and derive an expression for its transfer function. (10) ti) Design the above mentioned filter for a cutoff frequency of 1 KHz GBP econ at4 3 C3181) u. @ ® 16. @) ® (Draw the bloc diagram ofa PLL and derive its transfer (10) Gi) Draw the cireut of FM demodulator using PLL. © 2 6) Draw the circuit of a ROR ladder ype digital 4x Sabo converter and explain. ®) Gi) Draw the circuit of a four bit R-2R D/A. er with feedback Feoistance af SH for the Op-Amp. Caleulgbe Weutput voltage for a digital input of 0100 if the reference volt a3. @) - & (0 Rxplain the working of fash or converter, (8) (ii) How many comparators gxe/feat, for a 4- bit flash ADC? For an Input sigtal in the range-Gf Oo 10 V. What are the roforence waltages needed? Shote how Woy can be generated using # 10 V yeference and several isons ® (Draw the inter gram of voltage regulator IC LM 723 ra exain ® (i Design a vol ator using LM. 728 with short circuit current protection aXe lowing spesfcaions. Ve = 12 V, Ik = 500 mA, Tee = 600, ® 2 SW C2 Draw it of an 10 tuned amplifer and explain how you will reahgalh amplifier with AGC and a video apie using this building “sp (16) 4 C3181