Digital Design: An Embedded Systems Approach Using Verilog: Sequential Basics

Digital Design:
An Embedded Systems
Approach Using Verilog
Chapter 4
Sequential Basics
Portions of this work are from the book, Digital Design: An

Embedded Systems Approach Using Verilog, by Peter J. Ashenden,
published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier
Inc. All rights reserved.
Verilog
Sequential Basics
Sequential circuits
Outputs depend on current inputs and

previous inputs
Store state: an abstraction of the
history of inputs
Usually governed by a periodic

clock signal
Digital Design Chapter 4 Sequential Basics
Verilog
D-Flipflops
1-bit storage element
We will treat it as a basic component
clk
clk
D
Q
Other kinds of flipflops
SR (set/reset), JK, T (toggle)

Verilog
Registers
Store a multi-bit encoded value
One D-flipflop per bit

Stores a new value on
each clock cycle
d(0)
q(0)
q(1)
q(n)
clk
d(1)
wire [n:0] d;
reg [n:0] q;
...
D
clk
event list
always @(posedge clk)

q <= d;
d(n)
clk
D
clk
nonblockin
g
asignment
clk
Verilog
Pipelines Using Registers

Total delay = Delay1 + Delay2 + Delay3
Interval between outputs > Total delay
combinational
circuit 1
d_in
d_in
combinational
circuit 1
D
clk
combinational
circuit 2
combinational
circuit 2
combinational
circuit 3
D
clk
combinational
circuit 3
d_out
clk
clk
Clock period = max(Delay1, Delay2, Delay3)

Total delay = 3 clock period
Interval between outputs = 1 clock period
Verilog
Pipeline Example
Compute the average of corresponding

numbers in three input streams
New values arrive on each clock edge
module average_pipeline ( output reg signed [5:-8] avg,

input
signed [5:-8] a, b, c,
input
clk );
wire signed [5:-8] a_plus_b, sum, sum_div_3;
reg signed [5:-8] saved_a_plus_b, saved_c, saved_sum;
...
Verilog
Pipeline Example
...
assign a_plus_b = a + b;
always @(posedge clk) begin // Pipeline register 1
saved_a_plus_b <= a_plus_b;
saved_c
<= c;
end
assign sum = saved_a_plus_b + saved_c;
saved_sum <= sum;
// Pipeline register 2
assign sum_div_3 = saved_sum * 14'b00000001010101;

avg <= sum_div_3;
// Pipeline register 3
endmodule
Verilog
D-Flipflop with Enable
Storage controlled by a clock-enable
stores only when CE = 1 on a rising

edge of the clock
clk
D
Q
CE
clk
CE
D
Q
CE is a synchronous control input

Verilog
Register with Enable
One flipflop per bit
clk and CE wired in common

wire [n:0] d;
wire
ce;
reg [n:0] q;
...
if (ce) q <= d;
Verilog
Register with Synchronous

Reset
Reset input forces stored value to 0
reset input must be stable around

rising edge of clk
1
clk
D
Q
CE
reset
clk
reset
CE
D
Q

if
(reset) q <= 0;
else if (ce)
q <= d;
10
Verilog
Register with Asynchronous

Reset
Reset input forces stored value to 0
reset can become 1 at any time, and

effect is immediate
reset should return to 0 synchronously
1
D
Q
CE
reset
clk
clk
reset
CE
D
Q
11
Verilog
Asynch Reset in Verilog

always @(posedge clk or posedge reset)
if
(reset) q <= 0;
else if (ce)
q <= d;
reset is an asynchronous control input

here
include it in the event list so that the

process responds to changes immediately
12
Verilog
Example: Accumulator
Sum a sequence of signed numbers
A new number arrives when data_en = 1

Clear sum to 0 on synch reset
module accumulator
( output reg signed [7:-12] data_out,
input
signed [3:-12] data_in,
input
data_en, clk, reset );
wire signed [7:-12] new_sum;
assign new_sum = data_out + data_in;
if
(reset)
data_out <= 20'b0;
else if (data_en) data_out <= new_sum;
endmodule
13
Verilog
Flipflop and Register

Variations
module flip_flop_n ( output reg Q,
output
Q_n,
input
pre_n, clr_n, D,
input
clk_n, CE );
pre
D
Q
CE
clk Q
clr
always @( negedge clk_n or

negedge pre_n or negedge clr_n ) begin
if ( !pre_n && !clr_n)
$display("Illegal inputs: pre_n and clr_n both 0");
if
(!pre_n) Q <= 1'b1;
else if (!clr_n) Q <= 1'b0;
else if (CE)
Q <= D;
end
assign Q_n = ~Q;
endmodule
14
Verilog
Shift Registers
Performs shift operation on stored data
Arithmetic scaling
Serial transfer
D(n1)
of data
0
1
D_in
D
Q
load_en
CE
clk
Q(n1)
Q(n2)
Q(0)
CE
clk
D(n2)
D
CE
clk
D(0)
load_en
CE
clk
D
CE
clk
15
Verilog
Example: Sequential
Multiplier
1616 multiply over 16 clock cycles,
using one adder
y(15...0)
y_load_en
y_ce
Shift register for multiplier bits

Shift register for lsbs of accumulated product
16-bit
shift reg
D_in
D
Q
load_en
CE
clk
16-bit
adder
x
c16
y
16-bit reg
x(15...0)
x_ce
15...0
31...16
15
P(31...15)
reset
CE
clk
CE
clk
P_reset
P_ce
clk
c0
16
17-bit reg
15-bit
shift reg
D_in Q
P(14...0)
CE
clk
16
Verilog
Latches
Level-sensitive storage
Data transmitted while enable is '1'
transparent latch
Data stored while enable is '0'

LE
D
LE
D
Q
17
Verilog
Feedback Latches
Feedback in gate circuits produces

latching behavior
Example: reset/set (RS) latch

+V
Q
R
Current RTL synthesis tools dont accept

Verilog models with unclocked feedback
18
Verilog
Latches in Verilog
Latching behavior is usually an error!
always @*
if (~sel) begin
z1 <= a1; z2 <= b1;
end
else begin
z1 <= a2; z3 <= b2;
end
Oops!
Should be
z2 <= ...
Values must be stored
for z2 while sel = 1

for z3 while sel = 0
19
Verilog
Counters
Stores an unsigned integer value
Used to count occurrences of
increments or decrements the value

events
repetitions of a processing step
Used as timers
count elapsed time intervals by

incrementing periodically
20
Verilog
Free-Running Counter
+1
clk
clk
Increments every rising edge of clk
up to 2n1, then wraps back to 0

i.e., counts modulo 2n
This counter is synchronous
all outputs governed by clock edge

21
Verilog
Example: Periodic Control

Signal
Count modulo 16 clock cycles
Control output = 1 every 8th and 12th cycle

decode count values 0111 and 1011
0
clk
1
+1
2
clk
D
ctrl
Q
clk
3
clk
clk
22
Verilog
Example: Periodic Control

Signal
module decoded_counter ( output ctrl,
input clk );
reg [3:0] count_value;
count_value <= count_value + 1;
assign ctrl = count_value == 4'b0111 ||
count_value == 4'b1011;
endmodule
23
Verilog
Count Enable and Reset
Use a register with control inputs

+1
D
CE
reset
clk
CE
reset
clk
Increments when CE = 1 on rising

clock edge
Reset: synch or asynch
24
Verilog
Terminal Count
Status signal indicating final count value

counter
Q0
Q1
TC
clk Qn
TC is 1 for one cycle in every 2n

cycles
frequency = clock frequency / 2n
Called a clock divider

25
Verilog
Divider Example
Alarm clock beep: 500Hz from 1MHz clock

10-bit
counter
Q
clk
count
tone2
TC
tone
CE
clk
clk
clk
count
0
1023
0
1023
1023
tone2
tone
26
Verilog
Divide by k
Decode k1 as terminal count and

reset counter register
Counter increments modulo k
Example: decade counter
Terminal count = 9
counter
clk
clk
Q0
Q1
Q2
reset Q3
Q0
Q1
Q2
Q3
27
Verilog
Decade Counter in Verilog

module decade_counter ( output reg [3:0] q,
input
clk );
q <= q == 9 ? 0 : q + 1;
endmodule
28
Verilog
Down Counter with Load
Load a starting value, then decrement
Terminal count = 0
Useful for interval timer
0
1
D
load
clk
clk
=0?
TC
29
Verilog
Loadable Counter in
Verilog
module interval_timer_rtl ( output
tc,
input [9:0] data,
input
load, clk );
reg [9:0] count_value;
if (load) count_value <= data;
else
count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule
30
Verilog
Reloading Counter in
Verilog
module interval_timer_repetitive ( output

tc,
input [9:0] data,
input
load, clk );
reg [9:0] load_value, count_value;
if (load) begin
load_value <= data;
count_value <= data;
end
else if (count_value == 0)
count_value <= load_value;
else
count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule
31
Verilog
Ripple Counter
clk
clk Q
D
Q1
clk Q
D
when previous bit changes from 1 to 0
clk Q
D
Q0
Each bit toggles between 0 and 1
clk
Q0
Q2
Q0
Q1
Q1
clk Q
D
Qn
Q2
Q2
32
Verilog
Ripple or Synch Counter?
Ripple counter is ok if
length is short
clock period long relative to flipflop
delay
transient wrong values can be tolerated
area must be minimal
E.g., alarm clock

Otherwise use a synchronous
counter
33
Verilog
Datapaths and Control
Digital systems perform sequences

of operations on encoded data
Datapath
Combinational circuits for operations

Registers for storing intermediate results
Control section: control sequencing
Generates control signals
Selecting operations to perform

Enabling registers at the right times
Uses status signals from datapath

34
Verilog
Example: Complex
Multiplier
Cartesian form, fixed-point
operands: 4 pre-, 12 post-binary-point bits

result: 8 pre-, 24 post-binary-point bits
Subject to tight area constraints
a ar jai
b br jbi
p ab pr jpi (ar br ai bi ) j (ar bi ai br )
4 multiplies, 1 add, 1 subtract
Perform sequentially using 1

multiplier, 1 adder/subtracter
35
Verilog
Complex Multiplier
Datapath
a_r
a_i
a_sel
b_r
b_i
b_sel
pp1_ce
pp2_ce
CE
p_r
p_i
CE
clk
clk
0
1
D
CE
clk
D
CE
clk
sub
p_r_ce
p_i_ce
clk
36
Verilog
Complex Multiplier in
Verilog
module multiplier
( output reg signed [7:-24] p_r, p_i,
input
signed [3:-12] a_r, a_i, b_r, b_i,
input
clk, reset, input_rdy );
reg a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce;
wire signed [3:-12] a_operand, b_operand;
wire signed [7:-24] pp, sum
reg signed [7:-24] pp1, pp2;
...
37
Verilog
Complex Multiplier in
Verilog
assign a_operand = ~a_sel ? a_r : a_i;
assign b_operand = ~b_sel ? b_r : b_i;
assign pp = {{4{a_operand[3]}}, a_operand, 12'b0} *
{{4{b_operand[3]}}, b_operand, 12'b0};
always @(posedge clk) // Partial product 1 register
if (pp1_ce) pp1 <= pp;
always @(posedge clk) // Partial product 2 register
if (pp2_ce) pp2 <= pp;
assign sum = ~sub ? pp1 + pp2 : pp1 - pp2;
always @(posedge clk) // Product real-part register
if (p_r_ce) p_r <= sum;
always @(posedge clk) // Product imaginary-part register
if (p_i_ce) p_i <= sum;
...
endmodule
38
Verilog
Multiplier Control
Sequence
Avoid resource conflict

First attempt
1.
2.
3.
4.
5.
6.
a_r * b_r pp1_reg

a_i * b_i pp2_reg
pp1 pp2 p_r_reg
a_r * b_i pp1_reg
a_i * b_r pp2_reg
pp1 + pp2 p_i_reg
Takes 6 clock cycles

39
Verilog
Multiplier Control
Sequence
Merge steps where no resource conflict
Revised attempt
1.
2.
3.
4.
5.
a_r * b_r pp1_reg

a_i * b_i pp2_reg
pp1 pp2 p_r_reg
a_r * b_i pp1_reg
a_i * b_r pp2_reg
pp1 + pp2 p_i_reg
Takes 5 clock cycles

40
Verilog
Multiplier Control Signals

Step
a_sel
b_sel
pp1_c
e
pp2_c
e
sub
p_r_ce p_i_ce
41
Verilog
Finite-State Machines
Used the implement control sequencing
Based on mathematical automaton theory
A FSM is defined by
set of inputs:
set of outputs:
set of states: S
initial state: s0 S
transition function: : S S
output function: : S or : S
42
Verilog
FSM in Hardware
D
reset
clk
inputs
reset
current_state
next
state
logic
clk
output
logic
outputs
Mealy
FSM only
Mealy FSM: : S
Moore FSM: : S
43
Verilog
FSM Example: Multiplier

Control
One state per step

Separate idle state?
Use step 1 as idle state
Wait for input_rdy = 1

Then proceed to steps 1, 2, ...
But this wastes a cycle!
Repeat step 1 if input_rdy 1
Proceed to step 2 otherwise
Output function
Defined by table on slide 43

Moore or Mealy?
Transition function
current
_state
input_
rdy
next_
state
step1
step1
step1
step2
step2
step3
step3
step4
step4
step5
step5
step1
44
Verilog
State Encoding
Encoded in binary
Encoded value used in circuits for

transition and output function
encoding affects circuit complexity
Optimal encoding is hard to find
N states: use at least log2N bits
CAD tools can do this well
One-hot works well in FPGAs

Often use 000...0 for idle state
reset state register to idle

45
Verilog
FSMs in Verilog
Use parameters for state values
Synthesis tool can choose an

alternative encoding
parameter [2:0] step1 = 3'b000, step2 = 3'b001,

step3 = 3'b010, step4 = 3'b011,
step5 = 3'b100;
reg [2:0] current_state, next_state ;
...
46
Verilog
Multiplier Control in Verilog

always @(posedge clk or posedge reset) // State register
if (reset) current_state <= step1;
else
current_state <= next_state;
always @* // Next-state logic
case (current_state)
step1: if (!input_rdy) next_state
else
next_state
step2:
next_state
step3:
next_state
step4:
next_state
step5:
next_state
endcase
=
=
=
=
=
=
step1;
step2;
step3;
step4;
step5;
step1;
47
Verilog
Multiplier Control in Verilog

always @* begin // Output_logic
a_sel = 1'b0; b_sel = 1'b0; pp1_ce = 1'b0; pp2_ce = 1'b0;
sub = 1'b0;
p_r_ce = 1'b0; p_i_ce = 1'b0;
case (current_state)
step1: begin
pp1_ce = 1'b1;
end
step2: begin
a_sel = 1'b1; b_sel = 1'b1; pp2_ce = 1'b1;
end
step3: begin
b_sel = 1'b1; pp1_ce = 1'b1;
sub = 1'b1;
p_r_ce = 1'b1;
end
step4: begin
a_sel = 1'b1; pp2_ce = 1'b1;
end
step5: begin
p_i_ce = 1'b1;
end
endcase
end
48
Verilog
State Transition Diagrams
Bubbles to represent states

Arcs to represent transitions
0, 0
Example
S = {s1, s2, s3}

Inputs (a1, a2):
= {(0,0), (0,1), (1,0),
(1,1)}
defined by diagram
0, 1
1, 0
s1
s2
1, 1
0, 0
1, 1
s3
0, 1
1, 0
49
Verilog
State Transition Diagrams
Annotate diagram
to define output
function
Annotate states for

Moore-style outputs
Annotate arcs for
Mealy-style outputs
Example
x1, x2: Moore-style

y1, y2, y3: Mealy-style
0, 1 / 0, 1, 1
0, 0 / 0, 0, 0
1, 0 / 1, 0, 0
s1
s2
1, 0
0, 0
1, 1 / 1, 1, 1
0, 0 / 0, 0, 0
/ 0, 1, 1
s3
0, 1 / 0, 1, 1
0, 1
1, 1 / 1, 1, 1
1, 0 / 1, 0, 0
50
Verilog
Multiplier Control Diagram
Input: input_rdy
Outputs
a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce
step1
0, 0, 1, 0, , 0, 0
step5
, , 0, 0, 0, 0, 1
step2
1, 1, 0, 1, , 0, 0
step4
1, 0, 0, 1, , 0, 0
step3
0, 1, 1, 0, 1, 1, 0
51
Verilog
Bubble Diagrams or
Verilog?
Many CAD tools provide editors for

bubble diagrams
Diagrams are visually appealing
Automatically generate Verilog for

simulation and synthesis
but can become unwieldy for complex
FSMs
Your choice...
or your manager's!
52
Verilog
Register Transfer Level
RTL a level of abstraction
data stored in registers

transferred via circuits that operate
on data
outputs
inputs
control section
53
Verilog
Clocked Synchronous
Timing
Registers driven by a common clock
Combinational circuits operate during

clock cycles (between rising clock edges)
tc
tco
Q1
tpd
D2
tsu
clk
tco
Q1
tpd
tco + tpd + tsu < tc
tsu
D2
54
Verilog
Control Path Timing

tco
tsu
tpd-s
tco + tpd-s + tpd-o + tpd-c + tsu < tc
tpd-c
tco + tpd-s + tpd-ns + tsu < tc
tpd-o
tpd-ns
tsu
Ignore tpd-s for a Moore FSM
55
Verilog
Timing Constraints
Inequalities must hold for all paths

If tco and tsu the same for all paths
Critical path
Combinational delays make the difference

The combinational path between registers
with the longest delay
Determines minimum clock period for the
entire system
Focus on it to improve performance
Reducing delay may make another path

critical
56
Verilog
Interpretation of
Constraints
1. Clock period depends on delays
System can operate at any frequency

up to a maximum
OK for systems where high
performance is not the main
requirement
2. Delays must fit within a target clock

period
Optimize critical paths to reduce delays

if necessary
May require revising RTL organization
57
Verilog
Clock Skew
clk1
Q1
D2
Q1
clk2
th
D2
Need to ensure clock edges arrive

at all registers at the same time
Use CAD tools to insert clock buffers

and route clock signal paths
58
Verilog
Off-Chip Connections
Delays going off-chip and inter-chip
Input and output pad delays, wire delays
Same timing rules apply
Use input and output registers to avoid

adding external delay to critical path
Q1
D2
59
Verilog
Asynchronous Inputs
External inputs can change at any time
Might violate setup/hold time constraints
Can induce metastable state in a flipflop
Unbounded time to
recover
1
k 2t
e
MTBF
k1 f f f 2
May violate setup/hold

k 2 0
time of subsequent
60
Verilog
Synchronizers
asynch_in
D
clk
synch_in
clk
clk
If input changes outside setup/hold window
If input changes during setup/hold window
Change is simply delayed by one cycle

First flipflop has a whole cycle to resolve
metastability
See data sheets for metastability parameters

61
Verilog
Switch Inputs and

Debouncing
Switches and push-buttons suffer from
contact bounce
Takes up to 10ms to settle
Need to debounce to avoid false triggering

+V
Requires two
inputs and two
R
resistors
Must use a breakS
Q
before-make
double-throw
62
switch
Verilog
Switch Inputs and

Debouncing
Alternative
Use a single-throw switch

Sample input at intervals longer than bounce time
Look for two successive samples with the same
value
+V
Assumption
Extra circuitry inside the

chip is cheaper than extra
components and
connections outside
63
Verilog
Debouncing in Verilog
module debouncer ( output reg pb_debounced,
input pb,
input clk, reset );
reg [18:0] count500000; // values are in the range 0 to 499999
wire
clk_100Hz;
reg
pb_sampled;
always @(posedge clk or posedge reset)
if
(reset)
count500000 <= 499999;
else if (clk_100Hz) count500000 <= 499999;
else
count500000 <= count500000 - 1;
assign clk_100Hz = count500000 == 0;
if (clk_100Hz) begin
if (pb == pb_sampled) pb_debounced <= pb;
pb_sampled <= pb;
end
endmodule
64
Verilog
Verifying Sequential
Circuits
Verification Testbench
Apply
Test Cases
Design Under
Verification
(DUV)
Checker
DUV may take multiple and varying

number of cycles to produce output
Checker needs to
synchronize with test generator

ensure DUV outputs occur when expected
ensure DUV outputs are correct
ensure no spurious outputs occur
65
Verilog
Example: Multiplier
Testbench
`timescale 1ns/1ns
module multiplier_testbench;
parameter t_c = 50;
reg
reg
wire signed [3:-12]
wire signed [7:-24]
clk, reset;
input_rdy;
a_r, a_i, b_r, b_i;
p_r, p_i;
real real_a_r, real_a_i, real_b_r, real_b_i,

real_p_r, real_p_i, err_p_r, err_p_i;
task apply_test ( input real a_r_test, a_i_test,
b_r_test, b_i_test );
begin
real_a_r = a_r_test; real_a_i = a_i_test;
real_b_r = b_r_test; real_b_i = b_i_test;
input_rdy = 1'b1;
@(negedge clk) input_rdy = 1'b0;
repeat (5) @(negedge clk);
end
endtask
66
Verilog
Example: Multiplier
Testbench
multiplier duv ( .clk(clk), .reset(reset),
.input_rdy(input_rdy),
.a_r(a_r), .a_i(a_i),
.b_r(b_r), .b_i(b_i),
.p_r(p_r), .p_i(p_i) );
always begin // Clock generator
#(t_c/2) clk = 1'b1;
#(t_c/2) clk = 1'b0;
end
initial begin // Reset generator
reset <= 1'b1;
#(2*t_c) reset = 1'b0;
end
67
Verilog
Example: Multiplier
Testbench
initial begin // Apply test cases
@(negedge reset)
@(negedge clk)
apply_test(0.0, 0.0, 1.0, 2.0);
apply_test(1.0, 1.0, 1.0, 1.0);
// further test cases ...
$finish;
end
assign
assign
assign
assign
a_r
a_i
b_r
b_i
=
=
=
=
$rtoi(real_a_r
$rtoi(real_a_i
$rtoi(real_b_r
$rtoi(real_b_i
*
*
*
*
2**12);
2**12);
2**12);
2**12);
68
Verilog
Example: Multiplier
Testbench
always @(posedge clk) // Check outputs

if (input_rdy) begin
real_p_r = real_a_r * real_b_r - real_a_i * real_b_i;
real_p_i = real_a_r * real_b_i + real_a_i * real_b_r;
repeat (5) @(negedge clk);
err_p_r = $itor(p_r)/2**(-24) - real_p_r;
err_p_i = $itor(p_i)/2**(-24) - real_p_i;
if (!( -(2.0**(-12)) < err_p_r && err_p_r < 2.0**(-12) &&
-(2.0**(-12)) < err_p_i && err_p_i < 2.0**(-12) ))
$display("Result precision requirement not met");
end
endmodule
69
Verilog
Asynchronous Timing
Clocked synchronous timing requires
Hard to achieve in complex multi-GHz

systems
Globally asynch, local synch (GALS) systems
global clock distribution with minimal skew

path delay between registers < clock period
Divide the systems into local clock domains

Inter-domain signals treated as asynch inputs
Simplifies clock managements and constraints
Delays inter-domain communication
Delay-insensitive asynchronous systems
no clock signals
70
Verilog
Other Clock-Related Issues
Inter-chip clocking
In multi-PCB systems
Distributing high-speed clocks on PCBs is hard

Often use slower off-chip clock, with on-chip
clock a multiple of off-chip clock
Synchronize on-chip with phase-locked loop (PLL)
treat off-PCB signals as asynch inputs
Low power design
Continuous clocking wastes power

Clock gating: turn off clock to idle subsystems
71
Verilog
Summary
Registers for storing data
Latches: level-sensitive
synchronous and asynchronous

control
clock enable, reset, preset
usually unintentional in Verilog
Counters
free-running dividers, terminal count,

reset, load, up/down
72
Verilog
Summary
RTL organization of digital systems
Finite-State Machine (FSM)
states, inputs, transition/output functions

Moore and Mealy FSMs
bubble diagrams
Clocked synch timing and constraints
datapath and control section
critical path and optimization
Asynch inputs, switch debouncing

Verification of sequential systems
73

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Digital Design:

Portions of this work are from the book, Digital Design: An

Outputs depend on current inputs and

Usually governed by a periodic

Digital Design Chapter 4 Sequential Basics

1-bit storage element

We will treat it as a basic component

Other kinds of flipflops

SR (set/reset), JK, T (toggle)

Store a multi-bit encoded value

One D-flipflop per bit

always @(posedge clk)

Digital Design Chapter 4 Sequential Basics

Pipelines Using Registers

Clock period = max(Delay1, Delay2, Delay3)

Compute the average of corresponding

New values arrive on each clock edge

module average_pipeline ( output reg signed [5:-8] avg,

Digital Design Chapter 4 Sequential Basics

assign sum_div_3 = saved_sum * 14'b00000001010101;

Digital Design Chapter 4 Sequential Basics

D-Flipflop with Enable

Storage controlled by a clock-enable

stores only when CE = 1 on a rising

CE is a synchronous control input

Register with Enable

One flipflop per bit

clk and CE wired in common

Digital Design Chapter 4 Sequential Basics

Register with Synchronous

Reset input forces stored value to 0

reset input must be stable around

always @(posedge clk)

Register with Asynchronous

Reset input forces stored value to 0

reset can become 1 at any time, and

Digital Design Chapter 4 Sequential Basics

Asynch Reset in Verilog

reset is an asynchronous control input

include it in the event list so that the

Digital Design Chapter 4 Sequential Basics

Sum a sequence of signed numbers

A new number arrives when data_en = 1

Flipflop and Register

always @( negedge clk_n or

Digital Design Chapter 4 Sequential Basics

Performs shift operation on stored data

Digital Design Chapter 4 Sequential Basics

using one adder

Shift register for multiplier bits

Digital Design Chapter 4 Sequential Basics

Data transmitted while enable is '1'

Data stored while enable is '0'

Digital Design Chapter 4 Sequential Basics

Feedback in gate circuits produces

Example: reset/set (RS) latch

Current RTL synthesis tools dont accept

Latching behavior is usually an error!