Combinational Circuits - 4 bit

Magnitude Comparator
Ms. B. Ramani, AP/ECE
S. S. N. College of Engineering

Objective

At the end of this session, students will
understand the algorithmic procedure
involved in the design of Magnitude
Comparator.

Magnitude Comparator:
Comparison of two numbers determines whether a
number is >, < or = the other number.
Magnitude Comparator is a combinational circuit
that compares two numbers, A & B and determines
their relative magnitudes.
Outputs of a comparator which compares A & B is
A > B, A = B & A < B.

In order to compare two numbers, the truth table

has too many entries.
E.g.: If we compare two numbers of 2 bits each it
has 16 possible entries. Similarly for two numbers
with 4 bit each. The possible entries are 28 = 256.
So it would be difficult to find expression &
design a circuit. So we go for an algorithmic
procedure to compare two numbers as they have
some regularity.

Algorithm for designing a 4-bit Magnitude Comparator:

Consider two numbers, A &B with 4 bits each. Let A =
A3A2A1A0 & B = B3B2B1B0 .
 The two numbers are equal if all the pair of significant bits
are equal. (i.e., A3 = B3, A2 = B2, A1 = B1, A0 = B0) . This is
logically given as,
xi= AiBi + AiBi where i = 0, 1, 2, 3
For equality condition to exist, all variables must be equal to 1.
(A =B) = x3x2x1x0 = 1
 To find if A > B & A < B, we start comparing the MSB.
If A3 > B3, we conclude A >B . If not A < B.
If A3 = B3 ,we see if A2 > B2. If true A> B else A < B.
Similarly we compare till the LSB. The logical expression for A
> B & A< B is given as:
(A>B) = A3B3+x3A2B2+x3x2A1B1+x3x2x1 A0B0 = 1 for A >B.
(A<B) = A3B3+x3A2B2+x3x2A1B1+x3x2x1 A0B0 = 1 for A < B.

The logic diagram implementing the functions A > B, A = B & A < B is

as shown in figure.

Here xi= AiBi + AiBi

is implemented as
xi = (AiBi'+Ai'Bi)'

Fig. 4- bit Magnitude Comparator

Summary

Algorithmic procedure involved in the
design of magnitude comparator is
studied.