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Solutions Manual: Digital Design
Solutions Manual: Digital Design
SOLUTIONS MANUAL
DIGITAL DESIGN
WITH AN INTRODUCTION TO THE VERILOG HDL
Fifth Edition
M. MORRIS MANO
Professor Emeritus
California State University, Los Angeles
MICHAEL D. CILETTI
Professor Emeritus
University of Colorado, Colorado Springs
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
CHAPTER 1
1.1
1.2
Base 10
Octal
Hex
Base 12
: 10
: 12
:A
:A
11
13
B
B
12
14
C
10
13
15
D
11
14
16
E
12
15
17
F
13
16
20
10
14
17
21
11
15
18
22
12
16
19
23
13
17
Base 10
Octal
Hex
Base 12
: 23 24
: 27 30
: 17 18
: 1B 20
25
31
19
21
26 27 28 29 30
32 33 34 35 36
1A 1B 1C 1D 1E
22 23 24 25 26
31
37
1F
27
32
40
20
28
20
24
14
18
21
25
15
19
22
26
16
1A
(a) 16,384
(b) 33,554,432
(c) 3,435,973,837
1.3
(a) (432)5
= 4 52 + 3 51 + 2 50
= 100 + 15 + 2
= (117)10
(b) (A98)12
(c) (475)8
= 4 82 + 7 81 + 5 80
= 256 + 56 + 5
= (317)10
(d) (2345)6 = 2 63 + 3 62 + 4 61 + 5 60
= 432 + 108 + 24 + 5
= (569)10
1.4
12-bit binary :
Decimal
:
Hexadecimal :
1.5
Let b = base
(a) 12 4 = 52
(b) 75/3 = 26
(b + 2) 4 = 5b + 2
4b + 8 = 5b + 2
b=6
(7b + 5) = 3(2b + 6)
7b + 5 = 6b +18
b = 13
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
(c) (2 b + 4) + (b + 7) = 4b, so b = 11
1.6
x2 13x + 32 = 0
(x 5)(x 4) = 0
x2 (5 + 4)x + 5 4 = x2 13x + 32
So, 5 + 4 = b + 3
5 4 = 3b + 2
OR
b=6
b=6
1.7
= (125715)8
1.8
512
256 0
128 0
2
2
2
2
2
2
64
32
16
8
4
2
1
(1000000000)2
0
0
0
0
0
0
0
512
16
32
(200)16
To binary
(200)16 = (10 0000 0000)2
2nd method is faster.
1.9
= 10 16 + 6 + 5 0.0625
= (166.3125)10
(c) (276.24)8
= 2 82 + 7 8 + 6 +
2
4
+
8
64
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
11
16
9
= 1.56310
16
4
= (12.25)10
16
1.11
1010.1
110 | 111111
110
(1010.1)2
111
110
110
110
0
1.12
1.13
(a)
(1100)2
+(110)2
(10010)2
1100 110
0000
1100+
1100+
(1001000)2
(b)
(AB)16
+(1C)16
(C7)16
AB 1C
804
AB+
(12B4)16
(a)
(35.125)10 = (100011.001)2
2
2
2
2
2
35
17 1
8
1
4
0
2
0
1
0
0.125 2 = 0.25
0.25 2 = 0.5
0.5 2 = 1.0
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
(b)
1
= 0.33333333
3
= (0.01010101)2 (0.33203125)10
1.15
(a)
1111 0000
1s comp:0000 1111
2s comp: 0001 0000
(b)
0000 0000
1s comp: 1111 1111
2s comp: 0000 0000
(c)
1101 1000
1s comp: 0010 0111
2s comp: 0010 1000
(d)
0101 0101
1s comp:1010 1010
2s comp: 1010 1011
(e)
1000 0000
1s comp: 0111 1111
2s comp: 1000 0000
(f)
1111 1111
1s comp: 0000 0000
2s comp: 0000 0001
25,918,036
74,081,963
74,081,964
(b)
99,999,999
9s comp : 00,000,000
10s comp : 00,000,001
25,000,000
9s comp : 74,999,999
10s comp : 75,000,000
(d)
00000000
9s comp : 99999999
10s comp : 100000000
(a)
9s comp :
10s comp :
(c)
1.16
(CAD9)16
(a)
16s comp:
(3527)16
(b)
(c)
(d)
1s comp:
2s comp:
(a)
2579
9s comp : 7420
10s comp : 7421
3699
+7421
1120
1
Ans: 1120
drop
(b)
9s comp
1800
: 8199
974
+8200
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
9174
4361
: 5638
2943
+5639
8582
0745
9s comp : 9254
10s comp : 9255
7631
+9255
6886
1
(c)
9s comp
(d)
826
1418
Ans: 6886
drop
1.18
(a)
1s comp
2s comp
10010
: 01101
: 01110
10101
+01110
1 00011
Ans: 00011
drop
(b)
1s comp
100110
: 011001
010010
+011010
2s comp
: 011010
101100
1s comp
110101
: 001010
2s comp
: 001011
011110
1s comp
101101
: 010010
101000
+010011
2s comp
: 010011
(c)
(d)
1.19
+9081 009081
9081 990918 (9s comp)
9081 990919 (10s comp)
010100
010011
+001011
100010
111011 000101
+954 000954
954 999045 (9s comp)
954 999046 (10s comp)
008127
1
drop
989965 10035
=
1
drop
1.20
+56 0 111000
56 1 001000
+35 0 100011
35 1 011101
+0 100011
1 011011
(overflow)
1011011 91
+1 011101
0010101
+21
1
drop
1.21
+9542 009542
9542 990458
+641 000641
641 999359
+999359
008901
1
drop
+000641
8901
991099
10183
989817
1
drop
1.22
(7654)10
BCD: 0111 0110 0101 0100
ASCII: 0 0110111 0110110 0110101 0110100
7
1.23
694
+538
+ 0101 0011
1000
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
1232
1.24
Octal Digit
0
1
2
3
4
5
6
7
6311
0000
0001/0010
0011
0100
0110/0101
0111
1000
1001/1010
1.25
(a) BCD
(b) Excess 3
(c) 2421
(d) 6311
1.26
:
:
:
:
6421
0000
0001
0010
0011
0100
0101
0110/1000
1001/0111
(6514)10
0110 0101 0001 0100
1001 1000 0100 0111
1100 1011 0001 0100
1000 0111 0001 0101
6514
: 3485
: 0011 0100 1110 1011
9s comp
2421
1s comp of
1.27
For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g.,
diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits
select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack,
queen, king). This a jack of spades might be coded as 11 1010. (Note: only 52 out of 64 patterns are
used.)
1.28
G
(space)
1110 0101 0010 0000
1100 0010
1010 1110
1.29
Digital Systems
1.30
(a) C9:
EE:
F3:
74:
69:
74:
F5:
74:
65:
1 100 1001
1 110 1110
1 111 0011
0 111 0100
0 110 1001
0 111 0100
1 111 0101
0 111 0100
0 110 0101
o
1100 0111
B
1110 0101
r
1110 1111
g
1111 0010
e
0110 0111
I
n
s
t
i
t
u
t
e
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.
10
62 + 32 = 94 printing characters
1.32
1.33
0101
0110
0100
(a) BCD
(b) Excess-3
(c) 84-2-1
1.35
(1380)10
1 011 0000
0 011 0001
0 011 0010
1 011 0011
0 011 0100
1 011 0101
1 011 0110
0 011 0111
(a)
a b c
a
f
b
c
f
g
1.36
a
b
a
f
f
g
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.