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Samples of VHDL Codes Presented in The Examples
Samples of VHDL Codes Presented in The Examples
Samples of VHDL Codes Presented in The Examples
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
PORT (a, b: IN BIT_VECTOR(N-1 DOWNTO 0);
cin: IN BIT;
s: OUT BIT_VECTOR(N-1 DOWNTO 0);
cout: OUT BIT);
END carry_ripple_adder;
--------------------------------------------------------------ARCHITECTURE structural OF carry_ripple_adder IS
SIGNAL carry: BIT_VECTOR(N DOWNTO 0);
-----------------------------------------------COMPONENT full_adder IS
PORT (a, b, cin: IN BIT; s, cout: OUT BIT);
END COMPONENT;
-----------------------------------------------BEGIN
carry(0) <= cin;
gen_adder: FOR i IN a'RANGE GENERATE
FA: full_adder PORT MAP (a(i), b(i), carry(i), s(i), carry(i+1));
END GENERATE;
cout <= carry(N);
END structural;
---------------------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
PACKAGE my_functions IS
FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR;
END my_functions;
---------------------------------------------------------------PACKAGE BODY my_functions IS
FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR IS
VARIABLE output: BIT_VECTOR(6 DOWNTO 0);
BEGIN
CASE input IS
WHEN 0 => output:="1111110"; --decimal 126
WHEN 1 => output:="0110000"; --decimal 48
WHEN 2 => output:="1101101"; --decimal 109
WHEN 3 => output:="1111001"; --decimal 121
WHEN 4 => output:="0110011"; --decimal 51
WHEN 5 => output:="1011011"; --decimal 91
WHEN 6 => output:="1011111"; --decimal 95
WHEN 7 => output:="1110000"; --decimal 112
WHEN 8 => output:="1111111"; --decimal 127
WHEN 9 => output:="1111011"; --decimal 123
WHEN OTHERS => output:="1001111";
--letter "E" (Error) -> decimal 79
END CASE;
RETURN output;
END bcd_to_ssd;
END my_functions;
----------------------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
(P(0) AND cin);
c(2) <= G(1) OR
(P(1) AND G(0)) OR
(P(1) AND P(0) AND cin);
c(3) <= G(2) OR
(P(2) AND G(1)) OR
(P(2) AND P(1) AND G(0)) OR
(P(2) AND P(1) AND P(0) AND cin);
cout <= G(3) OR
(P(3) AND G(2)) OR
(P(3) AND P(2) AND G(1)) OR
(P(3) AND P(2) AND P(1) AND G(0)) OR
(P(3) AND P(2) AND P(1) AND P(0) AND cin);
------- Computation of sum:
sum <= P XOR c;
END structure;
---------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
END fibonacci;
----------------------------------------------------ARCHITECTURE fibonacci OF fibonacci IS
SIGNAL a, b, c: INTEGER RANGE 0 TO 2**N-1;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
b <= 1;
c <= 0;
ELSIF (clk'EVENT AND clk='1') THEN
c <= b;
b <= a;
END IF;
a <= b + c;
END PROCESS;
fibo_series <= c;
END fibonacci;
-----------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
fx <= temp;
END IF;
END PROCESS;
test <= twindow;
END behavioral;
------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
siren <= '1';
IF (remote='1' AND flag='1') THEN
nx_state <= disarmed;
ELSE
nx_state <= intrusion;
END IF;
END CASE;
END PROCESS;
END fsm;
----------------------------------------------------------
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008