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Parallel Multiplier - Accumulator Based On Vedic Mathematics
Parallel Multiplier - Accumulator Based On Vedic Mathematics
Objectives
Vedic Multiplier
Compressors
Future plans
08-December-2014
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Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Overview
1 Introduction
2
Objectives
3 Vedic Multiplier
RTL Schematic
4 Compressors
s
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Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Introduction
In Vedic mathematics multiplier is designed by using Urdhwa
Tiryakbyam.
Urdhwa Tiryakbyam is the simplest and fastest multiplication
algorithm.
Compared to modified booth multiplier algorithm Vedic
multiplier has less power dissipation and high speed operation.
By replacing modified booth with Vedic multiplier in MAC
unit performance can be improved.
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Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Objectives
3/15
Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Vedic Multiplier
4/15
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
RTL Schematic
RTL Schematic
Vedic multiplier
4 Bit
8 Bit
Area(um)
593.1
3026.8
Delay(ns)
1.97
3.82
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Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Compressors
6/15
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
7/15
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Area(um)
73.3
251
Delay(ns)
Addition
.
.52
5 Bit
.93
10 Bit
Area
81.2
267
Delay
.7
1.17
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Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Architecture
Vedic Mul.
4 Bit
Area(um)
593.1
Delay(ns)
Compressor
.
1.97
4 Bit
Area
585
Delay
1.77
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Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
* Booth encoder
* good timing * decrease delay
10/15
Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
11/15
Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Vedic encoder
.47ns
Vedic encoder Delay
.
1.13ns
Partial product addition
.17ns
1.07ns
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Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
13/15
Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
Future plans
Design of ALU by using the proposed MAC unit and Nikhilam
Sutra based squarer circuit.
Transistor level power optimization of MAC unit by using
Gate-diffusion input (GDI) technique.
Higher order bits MAC unit development and its FPGA
implementation.
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Parallel Multiplier - Accumulator Based on Vedic Mathematics
Introduction
Objectives
Vedic Multiplier
Compressors
Future plans
References
Young-Ho Seo, Member, IEEE, and Dong-Wook Kim, Member, IEEE, A
New VLSI Architecture of Parallel MultiplierAccumulator Based on
Radix-2 Modified Booth Algorithm, IEEE Transactions on very large scale
integration(VLSI) systems, Vol 18, No.2 February 2010.
Tiwari, Honey Durga, Ganzorig Gankhuyag, Chan Mo Kim, and Yong
Beom Cho.Multiplier design based on ancient Indian Vedic
Mathematics. In SoC Design Conference, 2008. ISOCC08.
International, vol. 2, pp. II-65. IEEE, 2008.
Sushma R. Huddar ,Sudhir Rao Rupanagudi, Kalpana M and Surabhi
Mohan,Novel High Speed Vedic Mathematics Multiplier using
Compressors. 2013 IEEE.
Devika Jaina, Kabiraj Sethi and Rutuparna Panda, Vedic Mathematics
Based Multiply Accumulate Unit .2011 International Conference on
Computational Intelligence and Communication Systems.
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Parallel Multiplier - Accumulator Based on Vedic Mathematics