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  • STD - Logic STD - Logic - Vector: Counters - 2 C S Q Counters - 2

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    sony
    21 views3 pages
    This document contains VHDL code for three different 4-bit counter designs. The first is a 4-bit down counter with synchronous set, the second is also a 4-bit down counter with synchronous set, and the third is a 4-bit up counter with asynchronous load from a primary input. Each design uses signals and processes to increment, decrement, or load a 4-bit counter value which is output on port Q.

    Original Description:

    counters program vhdel

    Original Title

    Counters

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    This document contains VHDL code for three different 4-bit counter designs. The first is a 4-bit down counter with synchronous set, the second is also a 4-bit down counter with synchronous set, and the third is a 4-bit up counter with asynchronous load from a primary input. Each design uses signals and processes to increment, decrement, or load a 4-bit counter value which is output on port Q.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    21 views3 pages

    STD - Logic STD - Logic - Vector: Counters - 2 C S Q Counters - 2

    Uploaded by

    sony
    This document contains VHDL code for three different 4-bit counter designs. The first is a 4-bit down counter with synchronous set, the second is also a 4-bit down counter with synchronous set, and the third is a 4-bit up counter with asynchronous load from a primary input. Each design uses signals and processes to increment, decrement, or load a 4-bit counter value which is output on port Q.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 3

    C:\Users\onigas\Documents\_Cursuri\Cursuri 2012-2013\PCN\HDL_Coding_Techniques\counters\counters_2.

    vhd

    --- 4-bit unsigned down counter with a synchronous set.


    -library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity counters_2 is
    port(C, S : in std_logic;
    Q : out std_logic_vector(3 downto 0));
    end counters_2;
    architecture archi of counters_2 is
    signal tmp: std_logic_vector(3 downto 0);
    begin
    process (C)
    begin
    if (C'event and C='1') then
    if (S='1') then
    tmp <= "1111";
    else
    tmp <= tmp - 1;
    end if;
    end if;
    end process;
    Q <= tmp;
    end archi;

    -1-

    21 mai 2013 08:52

    C:\Users\onigas\Documents\_Cursuri\Cursuri 2012-2013\PCN\HDL_Coding_Techniques\counters\counters_2.vhd

    --- 4-bit unsigned down counter with a synchronous set.


    -library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity counters_2 is
    port(C, S : in std_logic;
    Q : out std_logic_vector(3 downto 0));
    end counters_2;
    architecture archi of counters_2 is
    signal tmp: std_logic_vector(3 downto 0);
    begin
    process (C)
    begin
    if (C'event and C='1') then
    if (S='1') then
    tmp <= "1111";
    else
    tmp <= tmp - 1;
    end if;
    end if;
    end process;
    Q <= tmp;
    end archi;

    -1-

    21 mai 2013 08:52

    C:\Users\onigas\Documents\_Cursuri\Cursuri 2012-2013\PCN\HDL_Coding_Techniques\counters\counters_3.vhd

    --- 4-bit Unsigned Up Counter with Asynchronous Load from Primary Input
    -library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity counters_3 is
    port(C, ALOAD : in std_logic;
    D : in std_logic_vector(3 downto 0);
    Q : out std_logic_vector(3 downto 0));
    end counters_3;
    architecture archi of counters_3 is
    signal tmp: std_logic_vector(3 downto 0);
    begin
    process (C, ALOAD, D)
    begin
    if (ALOAD='1') then
    tmp <= D;
    elsif (C'event and C='1') then
    tmp <= tmp + 1;
    end if;
    end process;
    Q <= tmp;
    end archi;

    -1-

    21 mai 2013 08:54

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