INTA

RST 6.5
TRAP
RST 5.5

RST 7.5

SID

INTR

Interrupt Control

SOD

Serial I/O

8-bit internal data bus

Accumulator

Temp. Reg.

IR

Flags
Instruction
Decoder &
m/c cycle
ALU

encoding

MUX
W

Stack Pointer
Program Counter
Inc/Dec Address Latch

Address Buffer

Timing and Control

X0
X1

CLK
GEN

Control

Status

DMA

Reset
A15 A8
Address Bus

Clk out

RD
READY

WR

ALE

S0

S1

IO/M

HOLD

Data/adr
Buffer

HLDA

RESET OUT

RESET IN

AD0 AD7
Address/Data
Bus