16 Bit SRAM Implementation and Analysis

Project
by

Aamodh K , Arjun S Kumar and Vikas Bhardwaj

(M.Tech VLSI Design)
6th November 2015

Problem Statement
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To Design and Implement 16 bit SRAM (4 x 4 array)

To Implement the peripheral circuitry
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Write Enable
Precharge
Row and column decoder
Sense Amplifier

To characterize SRAM cell in terms of

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Read delay
Write delay
Power dissipation
Area

Implementation Methodology

Schematic of the circuit was drawn

Layout corresponding to schematic was laid out in Magic

Layout was simulated in IRSIM and functional testing was

done

Parasitic capacitances were extracted from layout

Parasitics were appended to manually written NG Spice netlist

and simulated

Characterization of SRAM cell was conducted using Perl

Schematic

Layout

Observations 1: Transient analysis of Write operation

Observation 2: Transient analysis of Read operation

Results Tabulated

Challenges and Learnings: Sizing decoder

Challenges and Learnings: Sense Amplifier

Challenges and Learnings: SRAM cell