Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002, pp.

543545

Scheme for No Dead Zone, Fast PFD Design

Han-il Lee, Tae-won Ahn, Duck-young Jung and Byeong-ha Park
RFIC Development, Semiconductor System LSI Business, Samsung Electronics Co. Ltd., Suwon 440-600
(Received 12 April 2000, in final form 27 March 2002)
A useful scheme for improving important performance parameters of phase locked loop applications, such as the dead-zone, the reference spur, the maximum operating frequency of phase
frequency detector, the lock time, the phase error, etc., is proposed. It provides the relationship
between the dead-zone and the operating frequency of the PFD. Thus, it enables the circuit designer to design the PFD with both no dead-zone and high operating frequency. This scheme was
verified by using a HSPICE simulation. The Samsung 0.5 m 15 GHz fT Si BiCMOS process model
parameters were used, and the circuits were designed to operate with a supply voltage of 3.0 V.
PACS numbers: 85.40, 84.30
Keywords: Phase Locked Loops, Phase Frequency detecter, Dead zone

problems. A careful design needs to consider the delay

length of the PFD. Aside from the characteristics of the
reference spur and the dead zone, the reset delay length
of the PFD is important in many PLL characteristics,
such as the maximum operating frequency of the PFD,
the phase error, and the lock time. Therefore, in this paper, a useful scheme for optimal delay in the PFD reset
path is proposed to improve all of the characteristics.

I. INTRODUCTION
Phase Locked Loops (PLLs) have many characteristics, such as the lock time, the phase noise, the reference
spur, the dead zone, and the comparison frequency, and
those characteristics are related to one another [13]. If
we improve some performances, others may deteriorate.
Many techniques exist for achieving a PFD (phase frequency detector) with no dead zone and many methods exist for increasing the operating frequency of the
PFD. In this paper, a simple relationship between the
dead zone and the operating frequency of the PFD is described, and a useful scheme for obtaining both characteristics is proposed. No dead zone is important for accurate frequency generation, low phase noise in frequency
synthesizer PLLs, and low timing jitter in clock generator PLLs. In some applications, such as radio tunes, an
appropriate dead zone is needed. If the input frequency
of the PFD is increased, the lock time can be shortened
by using a PLL with a fixed loop bandwidth and the reference spur can be reduced in many PLL applications,
especially in a fractional-N frequency synthesizer.
In many PLL applications, an appropriate delay is
added in the PFD reset path to avoid the dead zone
problem. Unfortunately, because of this delay, there will
be short pulses on both the UP and the DOWN signals,
even in the locked state. Thus, the charge-pump current
will switch on and off, and current spikes will appear on
the charge-pump output at the reference frequency. This
will cause reference spurs to appear in the PLL output
spectrum at a frequency offset from the carrier equal to
this reference frequency [4]. Thus, too long a delay in
the PFD for no dead zone is the cause of reference spur
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II. PERFORMANCE PARAMETERS FOR A

PLL
1. Dead Zone in the PLL

The dead zone, crossover distortion, of the PLL is the

region where the charge-pump currents can not flow proportionally to the phase error, in Fig. 4(b). The main
cause of the dead zone is the relationship between the
propagation delay of the internal gates for the reset of
the PFD and the switching time of the charge-pump
currents. A conventional technique to avoid the dead
zone problem is to make the delay in the PFD reset path
longer than the switching time of the charge-pump currents. This is described in Fig. 1. This switching time
of the charge-pump currents is a function of the chargepump currents, the load capacitance of the charge-pump
MOS switch, and the drivability of the buffer.

2. Operating Frequency of the PFD

As the comparison frequency of the PLL increases,

some characteristics, such as the lock time, the phase

hilee211@samsung.co.kr

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Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002

Fig. 1. Circuits of PFD and charge pump.

noise, and the reference spur, can be improved. The

maximum operating frequency of the PFD is derived in
Soyuers paper [5]:
fP F Dmax = 1/(2 TR )

(1)

Fig. 2. Timing diagrams of PFD and charge-pump: (a)

TR < Tth and (b) TR > Tth .

As the reset delay of the PFD, TR , decreases, the maximum operating frequency of the PFD increases.

3. Reference Spur in the PLL

The reference spur is due to periodic charge-pump current spikes at the reference frequency, even in the lock
state.

III. PROPOSED SCHEME FOR OPTIMAL

TR IN DESIGN OF THE PFD
As seen from the above, the amount of delay in the
PFD reset path is the key parameter common to the
dead zone, the operating frequency of the PFD, and the
reference spur. Therefore, if these three characteristics
are to be improved the delay of the PFD reset path must
be determined carefully in many PLL applications. Figure 1 presents the PFD circuit with D flip-flops. A timing
diagram of the signals for the PFD in Fig. 1 is shown in
Fig. 2, where TR is the delay in the PFD reset path,
Te is a given phase error, Vth is the threshold voltage of
the charge-pump current switch, and Tth is the time for
the input voltage of the charge-pump switch from zero to
Vth . Tth is also the switching time of the charge-pump
currents. Vth and Tth are determined for a given PLL
application.
The difference between Fig. 2(a) and Fig. 2(b) is
the size of TR . If TR < Tth , as in Fig. 2(a), the
charge-pump switch can not be closed, Iout can not flow
during the time Te , and there is a dead zone. However, if TR > Tth , as shown in Fig. 2(b), charge-pump
switch can be closed, Iout can flow during the time Te ,
and there is no dead zone. Therefore, to avoid the dead

zone problem, we must design the delay of PFD reset

path (TR ) to be longer than the charge-pump current
switching time (Tth ). The minimum delay in the PFD
reset path (TRmin ) in order to avoid a dead zone is
related to Tth as
TRmin = Tth

(2)

The maximum delay in the PFD reset path (TRmax )

is the maximum operating frequency of the PFD
(fP F Dmax ), which is derived in Ref. 5:
TRmax = 1/(2 fP F Dmax )

(3)

In addition, to reduce the reference spur, we made the

delay in the PFD reset path (TR ) as short as possible.
Therefore, from the above relations, a useful scheme for
optimal TR in PFD design is as follows: First, for a
particular application, Tth is calculated, and TRmin is
determined. Second, fP F Dmax and TRmax are determined for the application. Last, TR is made to be a
little longer than TRmin in order to reduce the reference
spur.
TRmin < TR < TRmax

(4)

IV. SWITHCING TIME CALCULATION AND

SIMULATION RESULTS
1. Switching Time Calculation

The switching time of the charge-pump currents (Tth )

is a function of the charge-pump current, the load capacitance of the charge-pump MOS switch, and the drivability of the buffer. For the calculation of Tth , the last
inverter of the charge-pump buffer and the charge-pump

Scheme for No Dead Zone, Fast PFD Design Han-il Lee et al.

-545-

(W/L)DP M OS = 5.2 m/0.5 m, (W/L)DP M OS = 1.8

m/0.5 m. If Samsung 0.5 m BiCMOS model parameters are used, the parameters of Eq. (5) are Cox =
2.5 fF/m2 , VDD = 3 V, kr = 4.19, kf = 3.93, p =
432 A/V2 , n = 414 A/V2 . Therefore, from Eq. (5),
TRmin is simply calculated 2.0 ns.

2. Simulation Results

The simulation results of the above case are shown in

Fig. 4. Figure 4 shows that if we design TR to be
longer than TRmin (Tth = 2.0 ns) the dead zone does
not appear.

Fig. 3. Modeling of inverter and MOS switch.

V. CONCLUSIONS

Fig. 4. Simulation results comparing two cases: (a) TR >

Tth (=2 ns) and (b) TR < Tth (=2 ns).

switch of the MOS transistor in Fig. 1 are modeled as

the inverter and a load capacitor (CL ) in Fig. 3. The
charge-pump switching time (Tth ) can be approximated
by the average of the rise time and the fall time of the
UU (DD) signal of Fig. 2. The rise time (Tr ) and the fall
time (Tf ) can be calculated as in Ref. 6. A useful equation for the minimum reset delay of the PFD (TRmin )
in order to avoid dead-zone is given by
Tr + Tf
CL kf
kf
=
+
2
2V DD p
n
Cox (W L M )L kf
kf
=
+
2V DD
p
n

TRmin = Tth =

(5)

For certain applicationa of a 500 A charge-pump current, the appropriate sizes of the MOS switch (as a load)
and the last inverter of the charge-pump buffer (as a
driver) are (W L M)L = 10 m 0.5 m 50,

A useful scheme for improving important characteristics, such as the dead zone, the reference spur, and the
operating frequency of the PFD, in PLLs is proposed
and is verified by using the HSPICE simulation with the
Samsung 0.5 m 15 GHz fT Si BiCMOS process model
parameters. This scheme provides a common key parameter, the reset delay of the PFD TR , for the relationship between the dead zone and the operating frequency
of the PFD. Thus, a circuit designer can design the PFD
with no dead zone and with a fast operating frequency
by control of this key parameter.

REFERENCES
[1] Junghyun Lee, Sangoh Lee, Minjong Yoh, Inhyo Ryu and
Byung-Ha Park, J. Korean Phys. Soc. 35, S914 (1999).
[2] Tae-won Ahn and Byung-ha Park, J. Korean Phys. Soc.
40, 1 (2002).
[3] Kyung-suc Nah, Duck-young Jung and Byung-Ha Park,
J. Korean Phys. Soc. 37, 808 (2000).
[4] J. Cranincks and M. Steyaert, Wireless CMOS Frequency Synthesizer Design. (Kluwer Academic Publishers,
Boston, 1998), Ch. 7.
[5] Mehmet Soyuer and Robert G. Meyer, IEEE J. SolidState Circ. 29, 1019 (1990).
[6] Neil Weste and Kamran Eshragian, Principles of CMOS
VLSI: A System Perspective, 2nd ed. (Addison-Wesley,
New York, 1992), Ch. 4.