Digital Logic Sol CH02

July 2013
Digital Logic
Chapter (2):
Intorduction to Logic Circutis
Chapter (3):
Implementation Technology
Chapter (4):
Otimized Implement Mentation of Logic Function
Chapter (5):
Number Representation & Arithmetic Circuit
Chapter (6):
Combinational-Circuit Building Blocks
Chapter (7):
Flip-Flops, Registers, and Counters

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Chapter
2
INTRODUCTION TO LOGIC CIRCUITS

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2.4
Gate
Logic Gates and Networks
Symbol
Inputs
AND
Truth Table
Output
Output
0
Any
0
All
1
.
.
.
0
0
1
1
OR
+
.
.
.
NOT
0
1
0
1
0
1
1
1
All
0
Any
1
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Example 1:
Given the logic network shown in the figure below, find the following:
I.
(the output expression).
II.
Truth table for the logic function
.
III. Timing diagram for the logic function
.
Solution:
I:
1- Name the output of each gate and show its logic symbol:
2- Write the output ( ) in terms of output names, expand it to reach the inputs. (moving
from outputs to inputs)
=
(A
(( )
= (
+
D
) + (B
) + (( )
) + ( )
)
)
:
) (
) (

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II :
1- From part ( I ) above, = ( ) + (
equal to 1 (review OR gate truth table).
Expanding C and D:
C = 1: when
D = 1: when
), means
= 1 when either C or D is
, and
, and
(review AND gate truth table).

The rest of the possible input values give 0s by default.
2- Fill-in all possible combination inputs in the truth table as follows, and then the outputs
are deduced from the previous step :
(Notice: #Rows = 2
#inputs
)
.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
III :
Copy-paste from the truth table to the timing diagram as follows:
1
0
1
0
1
0
1
0
()
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2.5
Boolean Algebra
Axioms of Boolean
Algebra
1a.
1b.
2a.
2b.
3a.
3b.
4a.
4b.
00=0
1+1=1
11=1
0+0=0
01=10=0
1+0=0+1=1
Single-Variable Theorems
5a.
5b.
6a.
6b.
7a.
7b.
8a.
8b.
9.
Duality ()
replace each with + and vice versa

and replace each 0 with 1 and vice versa
To convert Logic Expression Dual Logic Expression
(Notice that any a is a dual of b below it and vice versa)
Two- or Three-Variables Properties.

10a.
10b.
11a.
11b.
12a.
12b.
13a.
13b.
14a.
14b.
15a.
15b.
16a.
16b.
17a.
17b.
Commutative
Associative
Distributive
Absorption
Combining
DeMorgans
theorem
Consensus

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July 2013
Example 2 (exercise 2.1 - 2nd ed):

Use algebraic manipulation to prove that:
).
Note that this is the distributive rule, as stated in identity 12b in section 2.5.
Solution:
Starting with Right Hand Side:
Why choose RHS?
Has more manipulations than LHS.
Using 12a (left to right) to

distribute the left parentheses over
the right one
Using 12a (left to right) again for

each small parentheses
Using 7a (
Take out as a common factor

from all terms containing
=1
(OR gate = 1, when any input = 1)
Using 6a,
= LHS

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July 2013
Example 3 (example 2.2 - 2nd ed):

Validate the following expression:
Solution:
In this example, since both sides have approximately equivalent amount of
manipulations, we can try to simplify both sides.
Using 10b to exchange places of
2nd and 3rd terms.
Using 12a (right to left) to take out

as a common factor from 1st &
2nd terms; and
from 3rd and 4th.
Using 8b,
(*)
Using 6a,
Using 12a (right to left) to take out

as a common factor from 2nd &
3rd terms.
Using 8b
6a
(*)
and
nd
for the 2 term.
Using 16a,
both sides are equivalent after simplifying.

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Example 4 (2.7 - 2nd ed): Validate the following expressions:

(a)
Solution - Using truth table:
Idea: We may construct a truth table for each side of the expression (LHS & RHS). If the truth tables are
identical, then the expression is valid.
1- Since each side of the expression is an OR function (4-inputs), then its easier to find when the output =
1 (OR gate = 1, when any term = 1). The rest of the possible input values give 0s by default.
0/1
A
0
E
1
B
1
C
0/1
+
OR
0
D
+
OR
1
H
0/1
For each term, recall AND truth table:

Output = 1 when All inputs = 1
Since is missing, then

its value could be 0 or 1.
0/1
OR
+
OR
0
0
0
0
1
1
1
1
LHS = RHS Valid
OR
0
0
1
1
0
0
1
1
0/1
F
0
1
0
1
0
1
0
1
+
OR
A
C
A, C
D
D
B
0/1
0
1
1
1
1
1
1
0
1
G
E
G
H
F
E
F, G
0
1
1
1
1
1
1
0
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July 2013
Example 5 (2.7 - 2nd ed): Validate the following expressions:

(c)
Solution - Using truth table:
Idea: We need to construct a truth table for each side of the expression (LHS & RHS). If the
truth tables are identical, then the expression is valid.
2- Since each side of the expression is an AND function (3-inputs), then its easier to find
when the output = 0 (AND gate = 0, when any term = 0). The rest of the possible input
values gives 1s by default.
)
0
0/1
A
AND
1
B
AND
0
C
0/1
0/1
F
For each parenthesis, recall OR truth table:

Output = 0 when All inputs = 0
Since is missing, then

it value could be 0 or 1.
+
0
LHS
0
D
0/1
0
0
0
0
1
1
1
1
RHS Not Valid
AND
0
0
1
1
0
0
1
1
0/1
0
E
0
1
0
1
0
1
0
1
A
A
C
C
B
0
1
0
1
0
0
1
0
AND 1
D, E
D
E
F
F
0
0
1
1
0
0
1
0
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July 2013
2.6
Functions Synthesis
(Using AND, OR, NOT Gates)
Row#
Minterm
Maxterm
(Force to 1,
then product the inputs)
(Force to 0,
then Sum the inputs)
(e.g.)
0
1
2
3
0
0
0
0
0
0
1
1
0
1
0
1
1
1
4
5
1
1
0
0
0
1
0
1
0
0
Let n = #inputs,
#inputs
then #Rows = 2
Let be a function of variables, then can be represented in the canonical form as Sum-ofProducts (SOP), or as Product-of-Sums (POS) as follows:
=
=
=
=
=
=
=
=

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July 2013
Example 6:
Given the truth table below, write the expression of
a. Sum-of-products.
b. Product-of-sums.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
as the following:
0
1
0
1
1
1
1
0
Solution:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
=
=
=
=
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July 2013
Example 7 (2.10 - 2nd ed):

Use algebraic manipulation to show that for three input variables
and
Solution:
Which is Sum-of-Products
Writing the minterms from 1 to 7.
Comparing both sides of the expression,

we need to gather the terms that have
and take as a common factor from those
terms. Do the same for
and .
Note: the same term can be used more than
once if you use 7a. (
from right to
left.
Using 12a to factor out common terms.
Using 8b,
the small parenthesizes
into 1.
Using 6a
Using 8b and 6a again for the

parenthesis.
to reduce
=

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July 2013

Use algebraic manipulation to find the minimum product-of-sums
expression for the function :
Solution:
Lets see the truth table for more insight into the question:
Sum#
0
1
2
3
4
5
6
7
.
.
15
0
0
0
0
0
0
0
0
.
.
1
0
0
0
0
1
1
1
1
.
.
1
0
0
1
1
0
0
1
1
.
.
1
0
1
0
1
0
1
0
1
.
.
1
0
1
1
1
0
0
0
1
.
.
1
1st
1st, 2nd
2nd
3rd
In order to minimize the 3rd

sum, we need to add row# 4 as
4 terms into the expression
(row# 4 2nd sum)
Using 14b
Using 8a and 6b.
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July 2013
2.7
Gate
NAND, NOR Logic Networks
Symbol
NAND
NOR
Inputs
Output
Truth Table
0
0
1
1
0
0
1
1
0
1
0
1
Output
1
1
1
0
0
1
0
1
Output
1
0
0
0
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July 2013

Implement the function
in the figure below using only NAND gates:
Solution:

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July 2013

Implement the function
in the figure below using only NOR gates:
Solution:

082

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July 2013
2.8
Design Examples
(Multiplexer Circuit)
Figure 2: Multiplexer Truth Table
Figure 1: Multiplexer Circuit

0-to-0 multiplexer
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
Figure 4: Compact truth-table representation
.
0
1
Figure 3: Multiplexer Graphical symbol

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July 2013

Design the simplest circuit that has four inputs,
which
produces an output value of 1 whenever three or more of the input variables
have value 1; otherwise, the output has to be 0.
Solution:
1. Fill-in all possible combination inputs in the truth table. Assign 1 as an output for all
combinations with three or more inputs equal to 1. Otherwise assign 0.
Term#
0
1st
2nd
3rd
4th
5th

. . .
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July 2013
2. Use Sum-of-products since the 1s are less than 0s.
=
Minimizing:
Lets try to move from 4 to 3 variables per term. To do so, we need to find each
terms differ-by-one couple term (
. From the truth table we notice:
-
1st and 5th differ by , which results:

2nd and 5th differ by , which results:
3rd and 5th differ by , which results:
4th and 5th differ by , which results:
=
=
=
=
Note: the same 5th term can be used more than once if you use 7a. (
.
.
.
.
from right to left.
=
+
+
+
=
+
=
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July 2013
2.9
Introduction to CAD Tools

(Introduction to Verilog Code)
Example A
Always
(procedural statements)
Continuous Assignment
(logic expressions)
Structural
(gate level primitives)
Verilog
Specification
module exampleA (x1, x2, x3, f);

input x1, x2, x3;
output f;
module moduleName (input & output list);

input inputs list;
output outputs list;
not (a, x1);

and (b, x2, x3);
or (f, a, b);
endmodule
not (output, input);

and (output, inputs list);
or (output, inputs list);
endmodule

input x1, x2, x3;
output f;
assign f = ~x1 | (x2 & x3);
endmodule
~ NOT
|
OR
assign LHS = RHS:

means continuous assignment
for the signal LHS (i.e f ).
Whenever any signal on RHS
changes its state, the value at
LHS will be re-evaluated.
& AND
always @ (sensitivity list):

input x1, x2, x3;
output f;
reg f;
always @ (x1, x2, x3)
f = ~x1 | (x2 & x3);
endmodule
The statements inside an always block are

executed by the simulator only when one or more
of the signals (i.e. x1, x2, x3) in the sensitivity list
changes values.
Any assigned signal (e.g f ) using always must be
declared as a variable using the keyword reg.
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July 2013
Example B
Always
(procedural statements)
Continuous Assignment
(logic expressions)
Structural
(gate level primitives)
Verilog
Specification
module exampleB (x1, x2, x3, f);

input x1, x2, x3;
output f;
not (notx1, x1);
not (notx2, x2);
not (notx3, x3);
and (a, notx1, notx2, x3);
and (b, notx1, x2, notx3);
and (c, x1, notx2, notx3);
and (d, x1, x2, x3);
or (f, a, b, c, d);
endmodule

input x1, x2, x3;
output f;
assign f = (~x1 & ~x2 & x3) |
(~x1 & x2 & ~x3) |
(x1 & ~x2 & ~x3) |
(x1 & x2 & x3);
endmodule

input x1, x2, x3;
output reg f;
always @ (x1, x2, x3)
assign f = (~x1 & ~x2 & x3) |
(~x1 & x2 & ~x3) |
(x1 & ~x2 & ~x3) |
(x1 & x2 & x3);
endmodule

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Example C: (Using ifelse)
Implement the above circuit using ifelse procedural statements.

Solution:
Note: ifelse can only be used inside always block.
module
exampleC(s, x1, x2, f);
input s, x1, x2;

output reg f;
always @ (s,
if (s ==
x1, x2)
1)
f = x2;
else
f = x1;
endmodule
Other Solution: (using conditional operator
module
(. ? : ) )
exampleC(s, x1, x2, f);
input s, x1, x2;

output reg f;
always @
(s, x1, x2)

f = (s==1? X2 : x1);
endmodule

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July 2013
Example 11 (modified 2.50 - 2nd ed):

(a) Write Verilog code to describe the following functions
(b)
Use algebraic manipulation to prove that
Solution:
module prob2_50(x1, x2, x3,
input x1, x2, x3, x4;
output f1, f2;
assign
assign
endmodule
x4, f1, f2);
f1 = (x1 & ~x3) | (x2 & ~x3) |

(~x3 & ~x4) | (x1 & x2) | (x1 & ~x4);
f2 = (x1 | ~x3) & (x1 | x2 | ~x4) & (x2 | ~x3 | ~x4);
Term#
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
From the truth table,
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
Term#
rd
2nd, 3rd
2nd
1st, 3rd, 5th

1st
5th
All terms
1st, 2nd, 4th
4th, 5th
4th
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
2nd
1st
All terms
1st
1st
3rd
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Digital Logic Sol CH02

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July 2013

info@eng-hs.com 9 4444 260 .

Logic Gates and Networks

info@eng-hs.com 9 4444 260 .

info@eng-hs.com 9 4444 260 .

(review AND gate truth table).

info@eng-hs.com 9 4444 260 .

replace each with + and vice versa

Two- or Three-Variables Properties.

info@eng-hs.com 9 4444 260 .

Example 2 (exercise 2.1 - 2nd ed):

Using 12a (left to right) to

Using 12a (left to right) again for

Take out as a common factor

info@eng-hs.com 9 4444 260 .

Example 3 (example 2.2 - 2nd ed):

Using 12a (right to left) to take out

Using 12a (right to left) to take out

for the 2 term.

both sides are equivalent after simplifying.

info@eng-hs.com 9 4444 260 .

Example 4 (2.7 - 2nd ed): Validate the following expressions:

For each term, recall AND truth table:

Since is missing, then

info@eng-hs.com 9 4444 260 .

Example 5 (2.7 - 2nd ed): Validate the following expressions:

For each parenthesis, recall OR truth table:

Since is missing, then

info@eng-hs.com 9 4444 260 .

(Using AND, OR, NOT Gates)

info@eng-hs.com 9 4444 260 .

info@eng-hs.com 9 4444 260 .

Example 7 (2.10 - 2nd ed):

Writing the minterms from 1 to 7.

Comparing both sides of the expression,

Using 12a to factor out common terms.

Using 8b and 6a again for the

info@eng-hs.com 9 4444 260 .

Example 8 (2.14 - 2nd ed):

In order to minimize the 3rd

Using 8a and 6b.

info@eng-hs.com 9 4444 260 .

NAND, NOR Logic Networks

info@eng-hs.com 9 4444 260 .

Example 9 (2.37 - 2nd ed):

in the figure below using only NAND gates:

info@eng-hs.com 9 4444 260 .

Example 10 (2.38 - 2nd ed):

in the figure below using only NOR gates:

info@eng-hs.com 9 4444 260 .

Figure 2: Multiplexer Truth Table

Figure 1: Multiplexer Circuit

Figure 4: Compact truth-table representation

info@eng-hs.com 9 4444 260 .

Example 11 (2.30 - 2nd ed):

info@eng-hs.com 9 4444 260 .

2. Use Sum-of-products since the 1s are less than 0s.

1st and 5th differ by , which results:

from right to left.

info@eng-hs.com 9 4444 260 .

Introduction to CAD Tools

module exampleA (x1, x2, x3, f);

module moduleName (input & output list);

not (a, x1);