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Jeppiaar Engineering College: Department of Electronics & Communicaton Engg
Jeppiaar Engineering College: Department of Electronics & Communicaton Engg
Instruction SIM: Set Interrupt Mask. This is a 1 byte instruction and can be used
three different functions as follows
i)to set mask for RST 7.5,6.5 AND 5.5 INTERRUPTS.
ii) to reset RST 7.5 Flip Flop.
iii)to implement serial I/O operation.
Instruction RIM: Read Interrupt Mask .this is a 1 byte instruction and can be used for the
following three functions.
i)to read interrupt masks.
ii)to identify pending interrupts.
iii)to receive serial data.
Note: draw the register format
2. List the different types of flags affected by the arithmetic and logic operations.
[NOV/DEC 2007]
Carry flag, auxillary carry flag, parity flag, sign flag, zero flag
3. List the interrupt signals present in 8085 processor in the priority order. [ Apr/may
2008]
Interrupts Priority
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
4. Compare CALL and PUSH instructions
When CALL is executed the microprocessor automatically stores the 16-bit
address of the instruction next to CALL on the stack. The programmer uses the
instruction PUSH to save the contents of accumulator on to the stack. When CALL is
executed the stack pointer is decremented by two. When PUSH is executed the stack
pointer register is decremented by two
5. What is the use of ALE?
The ALE (Address latch enable) is used to latch the lower order address so that it
can be available in T2 and T3 and used for identifying the memory address. During T1
the ALE goes high. When ALE goes low the lower order address is latched until the next
ALE.
6. Define instruction cycle, machine cycle and T-state
Instruction cycle is defined, as the time required for completing the execution of
an instruction. Machine cycle is defined as the time required for completing one
7.
8.
9.
10.
11.
3.
4.
5.
6.
7.
8.
9.
th
STD- Set Direction Flag: when this instruction is executed, the direction flag of
8086 is set to 1.
IRET-Interrupt Return: this instruction is used to terminate an interrupt service
procedure and transfer the program control back to main program.
11. Explain the process control instructions
STC It sets the carry flag & does not affect any other flag
CLC it resets the carry flag to zero &does not affect any other flag
CMC It complements the carry flag & does not affect any other flag
STD It sets the direction flag to 1 so that SI and/or DI can be decremented
automatically after execution of string instruction & does not affect other flags
CLD It resets the direction flag to 0 so that SI and/or DI can be incremented
automatically after execution of string instruction & does not affect other flags
STI Sets the interrupt flag to 1. Enables INTR of 8086.
CLI Resets the interrupt flagto0. 8086 will not respond to INTR.
Unit-III :MULTIPROCESSOR CONFIGURATIONS
All the masters use a single bus request line for requesting the bus access. The
controller sends a bus grant signal, in response to the request, if the busy signal is
inactive when the bus is free. The bus grant pulse goes to each of the masters in the
sequence till it reaches a requesting master .The master then receives the grant signal,
activates the busy line and gains the control of the bus. The priority is decided by the
position of the requesting master in the sequence.
7. What is independent bus request scheme?
Each of the masters requires a pair of request and grant pins which are connected
to the controlling logic. The busy line is common for all the masters. . f the controlling
logic receives a request on a bus request line, it immediately grants the bus access using
the corresponding bus grant signal, provided the BUSY line is inactive, and then grants
the request. This is quite fast, because each of the masters can independently
communicate with the controller.
8. What is meant by polling?
In polling schemes, a set of address lines is driven by the controller to address
each of the masters in sequence. When a bus request is received from a device by the
controller, it generates the address on the address lines. If the generated address matches
with that of the requesting masters, the controller activates the BUSY line.
9. Name the data types of 8087.
Binary integer
o Word
o Short
o Long
Packed decimal number(BCD)
Floating point /real number
o Short
o Long
o Temporary real
10. Explain numeric processor 8087.
Numeric processor 8087 is a coprocessor which has been designed to work under
the control of the processor 8086 and offer it additional numeric processing capabilities.
It supports 16, 32, 64-bit integers 32, 64, 80-bit floating point and 16 digit BCD data
types.
11. What are the functional units available in 8087?
CU-control unit
NEU - Numeric execution unit.
Unit IV: I/O INTERFACING
1. Name the three modes used by the DMA processor to transfer data? [ NOV/DEC
2006]
3.
4.
5.
6.
7.
8.
Each of the four DMA channels of 8257 has one terminal count register. This 16bit register is used for ascertaining that the data transfer through a DMA channel ceases
or stops after the required number of DMA cycles.
10. Define HRQ?
The hold request output requests the access of the system bus. In non- cascaded
8257 systems, this is connected with HOLD pin of CPU. In cascade mode, this pin of a
slave is connected with a DRQ input line of the master 8257,while that of the master is
connected with HOLD input of the CPU.
Unit-V: MICROCONTROLLERS
1. Explain DJNZ instructions of intel 8051 microcontroller?
2.
3.
4.
5.
DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a
low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as
a 16-bit data register or as two independent 8-bit registers. It serves as a base
register in indirect jumps, lookup table instructions and external data transfer.
SP: SP stands for stack pointer. SP is a 8- bit wide register. It is incremented
before data is stored during PUSH and CALL instructions. The stack array can
reside anywhere in on-chip RAM. The stack pointer is initialised to 07H after a
reset. This causes the stack to begin at location 08H.
6. List the applications of microcontroller. [MAY/JUNE 2009]
Serial Interrupt