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An Efficient Design of A Reversible Barrel Shifter
An Efficient Design of A Reversible Barrel Shifter
Abstract
Designing reversible circuits using reversible gates have
several constraints [3]:
a. The fan-out of every signal is equal to one.
The key objective of today’s circuit design is to increase the
performance without the proportional increase in power b. Loops are not permitted in a strictly reversible system.
consumption. In this regard, reversible logic has become an On the other hand, data shifting and rotating is important
immensely promising technology in the field of low power and frequently used in arithmetic operations, variable-length
computing and designing. On the other hand, data shifting and coding, bit-indexing and many more. In this consequence,
rotating are required in many operations such as arithmetic barrel shifters which are capable of performing n-bit shifting
and logical operations, address decoding and indexing etc. In and rotating of data in a single cycle, are normally used in
this consequence, barrel shifters, which can shift and rotate embedded processors such as: digital signal processors [4] and
multiple bits in a single cycle, have become a common design high performance processors [5], high-speed/low-power
choice for high speed applications. For this reason, this paper applications [6] etc. However, only one paper [7] has been
presents an efficient design of a reversible barrel shifter. It proposed so far on reversible barrel shifter. Thus this research
has also been shown that the new circuit outperforms the focuses on designing an efficient barrel shifter and then
previously proposed one in terms of number of gates, number evaluates several significant parameters for this reversible
of garbage outputs, delay and quantum cost. circuit design.
The structure of the paper is as follows: Section II provides
the necessary background on reversible logic as well as the
definitions of some commonly used reversible logic gates.
Several irreversible barrel shifters are described in Section III.
Section IV presents the existing reversible barrel shifter as well
1. Introduction as our proposed one and discusses about some properties of the
proposed circuit. Then it compares the novel shifter to the
Reversible system does not allow information to be erased. existing one. Lastly, the conclusions and further studies are
Thus the reversible gates have the same number of inputs and discussed in Section VI.
outputs which means that the input stage can always be
retained from the output stage. Landauer [1] pointed out that in
an irreversible system, erasure of a single bit generates kTln2 2. Basic Definitions
joules of heat energy where k is Boltzmann’s constant of
1.38x10-23 and T is the absolute temperature of the
environment. Based on this observation, Bennett [2] showed, In this, section we present some definitions on reversible
for a reversible computer the heat dissipation is exactly kTln1 logic for future reference. Then we formally illustrate the
which is logically zero. Thus reversible computation is a highly commonly used reversible logic gates and mention their
potential field for upcoming low power/high performance quantum cost.
computing. For this reason, designing different reversible gates
and combinational circuits has gained considerable importance
than ever before.
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Definition 1. A Reversible Gate is an n-input, n-output Definition 6. The 3*3 Toffoli gate (TG) [11] is defined as
(denoted by n * n) circuit that uniquely maps the output vector follows: input vector Iv = (A, B, C) and output vector Ov = ( P
Ov to the corresponding input vector Iv where Iv = (I0, I1, I2 … Ik- = A, Q = B and R = AB⊕ C). The block diagram for 3*3
1, Ik,) and Ov = (O0, O1, O2 … Ok-1, Ok) [8]. Toffoli gate is shown in Figure 2. The quantum cost of Toffoli
gate is 5 [9].
A P=A
Feynman Definition 7. The input and output vector for 3*3 Fredkin
Gate gate (FR) [12] are defined as follows: Iv = ( A, B, C ) and Ov =
B P = A⊕B
(P=A, Q= AB ⊕ AC and R = AC ⊕ AB ). Figure 3 shows the
block diagram of a 3x3 Fredkin gate. The quantum cost of FR
Figure 1. Garbage output of Feynman Gate
is also 5 [9].
A P=A
Definition 3. The calculation of quantum cost (QC) has
several approximations. Firstly the quantum cost of every 2*2 Fredkin
B Gate R = A'C ⊕ AB
gate is the same [9] and it is 1. Secondly, since each 1*1 gate
can always be included to any 2*2 gate that precedes or follows C Q = A'B ⊕AC
it, the quantum cost of the 1*1 gate is considered to be zero.
Thus every reversible gate is a combination of 1x1 or 2x2 Figure 3. Block diagram of a 3*3 Fredkin Gate.
reversible gate. So the quantum cost of a reversible circuit
calculates the total number of 2*2 gates used.
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parameters include total number of gates to be used in the
design, garbage outputs, delay and quantum cost of the circuit.
Figure 4. Section of a Barrel Shifter [13] 4.1. Existing Reversible Barrel Shifter
The shifter from [7] with 4-bit data value and 2-bit shift value
Input
is shown in Figure 6.
n
s0 20 Shifter
n
1
s1 2 Shifter
.
.
. n
.
k-1
sk-1 2 Shifter
n
Left/ Right
Output
Figure 5. (n, k ) Logarithmic Barrel Shifter Figure 6. Reversible (4, 2) Barrel Shifter proposed in [7]
Several other complex design patterns for irreversible The existing shifter is complex in design and requires
shifter have also been proposed. Barrel shifter using large number of gates. As a result the total number of garbage
multipliers [14], MUX based data reversal barrel shifter and outputs is high. Thus there is great room for improving the
shifter/rotator with overflow flag have also been discussed in circuit complexity, total number of gates and garbage outputs,
[15]. But only one paper [7] has been published so far on delay and quantum cost.
reversible barrel shifter. In the next section we will discuss
about this existing one and then propose our novel reversible 4.2. Proposed Reversible Barrel Shifter
circuit. Then we will also make a comparative study between
these two based on several designing parameters. The
For efficient designing of a reversible circuit several criteria
are needed to be considered:
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a. Minimize the number of gates as possible.
b. Minimize the quantum cost of the circuit.
c. Total number of garbage outputs and usage of
constant inputs should be minimized.
By maintaining the above parameters and observing the
previous design, we have proposed a novel logarithmic
Reversible Barrel Shifter. The proposed barrel shifter is a left
rotating shifter which uses Fredkin gates for reversible (2:1)
multiplexing and Feynman Gates for producing fan outs.
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Proof: Each Feynman gate produces two copies of single GO 244 52
input as described in Section 4. For the proposed n-bit barrel D 132 28
shifter each stage requires copying each input twice, but for the
fr 992 144
design pattern the last stage of the shifter does not need the
copying circuits. So the circuit can be realized with at least (32, 5) fe 992 128
n(k-1) number of Feynman Gates for fan out operations. GO 997 133
D 517 52
Theorem 3. Let n be the total number of data input bit and fr = Total number of Fredkin gates
k be the shift value of a unidirectional reversible barrel shifter. fe = Total number of Feynman gates
Let GO be the total number of garbage outputs of the proposed GO = Total number of Garbage Outputs
shifter, then D = Total Delay of the circuit
GO = n(k-1) + k
Proof: The number of Garbage output is proportional to
the number of Fredkin gates as each Fredkin gate except the Table 2. Comparison of the quantum cost of the barrel
last one of each stage produces at least one garbage bit. The shifters
last Fredkin gate of each stage adds an extra garbage bit to the Existing Design [7]
(n, k) Proposed Design
shifter. On the other hand, for the last stage of shifting
operation the cascaded Fredkin gates produces only one extra (4, 2) 72 34
bit. Thus the (k-1) number of stages produce a total of n(k- (8, 3) 336 116
1)+(k-1) Garbage bits and last stage adds only one garbage bit. (16, 4) 1440 328
Thus, the proposed shifter produces n(k-1) + (k-1) + 1 which is
n(k-1)+ k number of garbage outputs. (32, 5) 5952 848
Comparing with the existing barrel shifter to the proposed In this paper, an efficient novel logarithmic reversible
one, we observe the result shown in Table 1 and Table 2. From Barrel Shifter has been proposed. Then based on reversible
Table 1 we can see that the proposed circuit requires less circuit designing criteria several theorems have been proposed
number of gates, produce less garbage outputs. The delay costs for total number of gates required by the combinational circuit.
(D) of the two circuits have also been calculated according to The Garbage outputs, delay and quantum cost have also been
the definition [4]. The quantum cost of the circuit, calculated estimated. At last a comparison study between the only existing
according to the [9], is also shown in Table 2 which proves that circuit and the proposed one has been shown. At present, the
the present circuit performs much efficiently than the previous proposed barrel shifter is capable of left shift/rotate. Future
one. The performance improves as the size of the circuit grows. enhancements include bi-directional shift and shift/rotate
operations, logical or arithmetic shift operations. In that case,
more control inputs are needed to be added in the circuit.
Table 1. Comparative study of the reversible barrel
shifters
Existing Proposed
6. References
Criteria
(n, k) Design [7] Design
fr 12 6 [1] Rolf Landauer, "Irreversibility and Heat Generation in the
(4, 2) Computing Process," IBM Journal of Research and Development,
fe 12 4
vol. 5, pp. 183-191, 1961.
GO 14 6
D 10 6 [2] C.H. Bennett, Logical reversibility of computation, IBM J. Res.
fr 56 20 Dev. 17 (1973) 525-532.
(8, 3) fe 56 16
59 19 [3] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja
GO
Chowdhury and Syed Mostahed Ali Chowdhury, “Reversible Logic
D 35 14 Synthesis for Minimization of Full-adder Circuit”, IEEE Conference
fr 240 56 on Digital System Design 2003, Euro-Micro’03, Belek, Antalya,
(16, 4) Fe 240 48 Turkey, 2003, pp. 50-54.
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[4] Voyiatzis, D. Gizopoulos, and A. Paschalis, “Accumulator-Based
Test Generation for Robust Sequential Fault Testing in DSP Cores in
Near-Optimal Time” , IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 13, No. 9, pp. 1079– 1086,
September 2005.
[8] Ashis Kumer Biswas, Lafifa Jamal and Hafiz Md. Hasan Babu,
“An Efficient Design of Parallel Loading Shift Register Using
Reversible Flip-Flops,” Advanced Technical Program, VLSI-SOC,
16th IFIP/IEEE international conference on very large scale
integration, 13-15 October, 2008.
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