Lecture 3

Atmel AVR Architecture

Shaharyar Mahmood
RISC (Reduced Instruction Set
Computer)
 Entire computer system contained within a single
integrated circuit or chip.
 Operation is controlled by a user-written program
interacting with the fixed hardware architecture.
 Register-based architecture.
 RISC processor: 131 RISC-type instructions.
 Most can be executed in a single clock cycle.
 2-cycle multiplication operation.
 Harvard architecture: separate dedicated memories and
buses for program and data information.
 Fast and efficient program execution: 16 million
instructions per second when operating at 16 MHz clock.

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Harvard vs. Von Neumann
 A von Neumann architecture has
only one bus which is used for both
data transfers and instruction
fetches, and therefore data
transfers and instruction fetches
must be scheduled - they can not
be performed at the same time.
The program can be easily
modified by itself since it is stored
in read-write memory.
 Harvard architecture has
separate data and instruction
busses, allowing transfers to be
performed simultaneously on both
busses. Typically, code (or
program) memory is read-only and
data memory is read-write.
Therefore, it is impossible for
program contents to be modified
by the program itself.
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Endianness of AVR
 When communicating, Little Endian means that
the LSB is sent first followed by rest. In a
memory, Little Endian means that the LSB is
stored at the lowest storage address.
 When communicating, Big Endian means that
the MSB is sent first followed by the lower order
bytes. In a memory, Big Endian means that the
MSB is stored at the lowest storage address.
 Data stored in the AVR program and data
memories, are normally accessed as Little
Endian (Even if the Flash program memory is
physically organized as Big Endian).
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Assembly Language Instruction Set

 Group of instructions a machine

understands to execute.
 Instruction set is unique for a given
hardware and cannot be used with another
hardware configuration.
 131 different instructions.
 Fast and efficient.

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Assembly Language Instruction Set
 Assembly language efficiently interacts with a
specific MC’s resident hardware.
 Familiarity with low-level architecture is required.
 C language: hardware control at register level
also portable to other MCs in the AVR line.
 C Language program converted to Assembly
and then to machine code.
 Both have inherent advantages and
disadvantages.
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Block Diagram

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Pin Description
 VCC Digital supply voltage
 GND Ground
 Port A Serves as the analog inputs to the A/D
Converter, 8-bit bi-directional I/O port. Internal pull-up
resistors. Will source current as input if externally pulled
low.
 Port B 8-bit bi-directional I/O port with internal pull-up
resistors. Will source current as input if externally pulled
low. Other Special functions.
 Port C 8-bit bi-directional I/O port with internal pull-up
resistors. Will source current as input if externally pulled
low. Also provides JTAG interface.
 Port D 8-bit bi-directional I/O port with internal pull-up
resistors. Will source current as input if externally pulled
low. Other special functions.
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Pin Description
 RESET Reset Input. A low on this pin for longer than
the minimum length will generate a reset, even if the
clock is not running.
 XTAL1 Input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
 XTAL2 Output from the inverting Oscillator amplifier.
 AVCC Supply voltage pin for Port A and the A/D
Converter. It should be externally connected to Vcc even
if the ADC is not used. If the ADC is used, it should be
connected to Vcc through a low-pass filter.
 AREF Analog reference pin for the A/D Converter.

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AVR MCU Architecture

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ALU – Arithmetic Logic Unit
 Direct connection with all the 32 general
purpose working registers.
 Within a single clock cycle, arithmetic
operations between general purpose
registers or between a register and an
immediate is executed
 ALU operations: arithmetic, logical and bit
functions.
 Powerful multiplier.

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Status Register
 Contains information about the result of
the most recently executed arithmetic
instruction.
 This information can be used to alter
program flow based upon conditions.
 Updated after all ALU operations.
 Upon entering Interrupt routine must be
stored by software. Not automatic.
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Status Register

 Bit 7 – I: Global Interrupt Enable

Must be set for the interrupts to be enabled. If cleared,
none of the interrupts are enabled.
 Bit 6 – T: Bit Copy Storage
A bit from a Register File can be copied to it or vice
versa. Commands: BLD (bit load) and BST(Bit Store)
use T-bit as source or destination.
 Bit 5 – H: Half Carry Flag
Indicates Half Carry in some arithmetic operations.
Useful in BCD arithmetic.

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Status Register
 Bit 4 – S: Sign Bit, S=N(XOR)V
Exclusive or between the Negative Flag N and the Two’s
Complement Overflow Flag V.
 Bit 3 – V: Two’s Complement Overflow Flag
Supports two’s complement arithmetic.
 Bit 2 – N: Negative Flag
Indicates a negative result in an arithmetic or logic
operation.
 Bit 1 – Z: Zero Flag
Indicates a zero result in an arithmetic or logic operation.
 Bit 0 – C: Carry Flag
Indicates a carry in an arithmetic or logic operation.

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General Purpose Register File
 The Register File is optimized for the
AVR Enhanced RISC instruction set.
 Following input/output schemes are
supported by the Register File:
1. One 8-bit output operand and one 8-
bit result input.
2. Two 8-bit output operands and one 8-
bit result input.
3. Two 8-bit output operands and one
16-bit result input.
4. One 16-bit output operand and one
16-bit result input.

 Most of the instructions operating on

the Register File have direct access
to all registers, and most of them are
single cycle instructions
 Each register is also assigned a data
memory address, mapping them
directly into the first 32 locations.

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The X-, Y-, and Z-registers

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Stack Pointer

 The Stack Pointer Register always points

to the top of the Stack.
 Stack is implemented as growing from
higher memory locations to lower memory
locations.
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Memory
 In-System Programmable Flash EEPROM: for
global variables and for storing programs,
Nonvolatile, 16Kbytes.
 Byte-Addressable EEPROM: To permanent
store and recall variables during program
execution. 512 bytes of EEPROM.
 SRAM: volatile, 1120bytes. 96 locations for
registers and I/O subsystem. Used to store
global variables, support dynamic allocation of
variables and location for stack.
 Six memory lock bits to prevent serial or parallel
programming of memory.
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AVR Processor Memory Map

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Parallel Instruction Fetch and Execute

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Single Cycle ALU Operation

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Data Memory Map

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On-chip Data SRAM Access cycles

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Port System
 Four 8-bit general
purpose, digital I/O
ports: PORTA, PORTB,
PORTC and PORTD.

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Initialization and reading of Ports

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Note: unsigned used because both the port abd this variable are 8bits wide25
Time Base
 Internal: clock using a user-selectable
resistor capacitor (RC) time base, or
externally. RC internal time base is
selected using programmable fuse bits.
Internal fixed clock operating frequency of
1, 2, 4, or 8 MHz.
 External: wider frequency selections. It
could be an external RC network, a
ceramic resonator, or a crystal oscillator.
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Clock Distribution

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Crystal Oscillator Connections

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Reset

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Reset
 Power-On Reset

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Reset
 External Reset

When the applied signal reaches the Reset Threshold Voltage – VRST-
On its positive edge, the delay counter starts the MCU after the Time-
out period tTOUT has expired.
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Timing subsystem
 Used to generate precision output signal,
measure the characteristics (period, duty
cycle, frequency) of an incoming digital
signal, or count external events.
 Two 8-bit timer/counters and one 16-bit
counter.

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Pulse Width Modulation Channels
 PWM, signal is characterized by a fixed frequency and a
varying duty cycle.
 Duty cycle (%)=(on time/period) x (100%)
 Equipped with four PWM channels.
 The PWM channels coupled with the flexibility of dividing
the time base down to different PWM subsystem clock
source frequencies allows the user to generate a wide
variety of PWM signals, from relatively high-frequency,
low-duty cycle signals to relatively low –frequency, high-
duty cycle signals.
 Wide variety of applications, including controlling the
position of a servo motor and controlling the speed of a
DC motor.

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Serial Communications
 Serial USART: Used for full duplex (two-way)
communication between a receiver and
transmitter. Used for asynchronous
communication. Framing start and stop bits are
used for synchronization. Variety of transmission
rates known as baud (bits per second) may be
set. Also equipped with a hardware-generated
parity bit (even or odd) and parity check
hardware at the receiver.
 A single parity bit allows for the detection of a
single bit error within a byte of data.
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Serial Peripheral Interface (SPI)
 Two-way serial communication between a
transmitter and a receiver.
 Share a common clock source.
 Higher data transmission rates as compared
with the USART.
 Synchronous 16-bit shift register with an 8-bit
half residing in the transmitter and the other 8-bit
half residing in the receiver.
 Transmitter is master while receiver is slave.
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Two-Wire Serial Interface (TWI)
 Allows to network devices into a system using a
two-wire interconnecting scheme.
 Maximum of 128 devices can be connected
together.
 Each device has its own unique address and
may both transmit and receive over the two-wire
bus at frequencies up to 400kHz.
 This allows the device to freely exchange
information with other devices in the network
within a small area.

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Analog-to-Digital Converter
 Eight-channel ADC subsystem.
 10-bit resolution
 Analog voltage between 0 and 5V will be
encoded into one of 1024 binary
representations between (000)16 and
(3FF)16. Resolution is approx. 4.88mV.

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Interrupts
 Sometimes normal sequence of events
must be interrupted to respond to high-
priority faults and status both inside and
outside the MC.
 ISR (Interrupt Service Routine) is
executed upon interrupt.
 21 Interrupt sources.
 3 external interrupt sources.

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Packaging

40-pin dual in-line package (DIP)

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AVR in a circuit

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Power Consumption
 When ATmega16L is actively operating at 3MHz
from a 3-VDC power source, the current draw is
1.1mA.
 In idle mode: less than 0.35mA.
 Power down: less than 1µA.
 6 different sleep modes: using SLEEP
command. Awakened when an interrupt occurs.
 Power consumption can be further reduced by
operating the MC at the lowest practical clock
frequency for a given application.
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Speed Grades
 ATmega16L operates from 0 to 8 MHz, whereas
the ATmega16 operates from 0 to 16MHz.
 Faster microcontroller operation is not always
better. The system designer must determine the
minimum practical speed of MC operation for a
given application.
 MC’s power consumption is directly related to
operating speed.
 Faster speed means higher power consumption.
 This becomes especially critical in portable,
battery-operated embedded systems
applications.
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