Example VHDL Entity - 2 to 4 Decoder Output Bit [-®N 0-LsB ts outputs ‘ A B[K L MN A M 1 o 0fo 0 0 1 e o 1/0010 B L 2 1 0/0 1 0 0 11i1 0 0 0 [eK usp decoder decoder Truth Table A210 4 decoder generates an output signal on its output pins that is dependent on the binary code applied ta its inputs. Only one of the output pine is high at any time. For'n’ inputs there will he 2" outputs. e.g. 2t0 4, 3 10 8, 4to 16 et. VHDL Model VHDL Test Bench Library THEE? entity Decoder_24 is Port (Rt in STD_Loarc, in ST0_Losrcy STD _Lostc; STDLLOGIC'} fend Decoder_24; architecture Behavioral of Decodar_24 is begin “agsune that for input A and B that B is Least Significant Bit (Ls8) + and for outputs K,L,M, N that N is ise s When A= 10! and B= 10" else ™ When R= *0" and B else 1 when A= "2" and B else KS at wnen As ‘2! and B= ‘1! else + LIBRARY ieee; Use ieee.sta logic 116¢.ALLy END Decoder 24-78; ARCHITECTURE behavior OF Decoder_24_78 IS = component Declaration for the unit Under Test (UT) covpenn? Becoder 24 PORE( A's IN stdzlogic; 1 sed Logics ovr sta togic: Our sta_legie; oor sta_logie ); Inputs Signal A 1 sta_logic signal B+ std logic *-outpute signal K 1 std_logicy Signal L : std logic; Signal M : std_logic: BEGIN wut: Decoder 24 PORT MAP ( WoW; -- +44 Test Bench ~ User Defined Section +++ tb: PROCESS Ace 101; Bee 10" ‘wait for 100 ns; Ree 10; Bex 17 for 100 ni for 100 na) wait; -- will wait forever END PROCESS; BND; ~~ define input waveforme for Aand B