Malaviya National Institute of Technology Jaipur

EC-624

VLSI Design Techniques CREDITS: 4 (2-0-3)

@IIT Rajasthan, Jodhpur

Weightage assignment
MTE- 40%
PRS- 20%
(Inclusive of quizzes in class)
ETE- 40%
Quizzes are not open books/notes.
Examinations are normally open notes/books.
Syllabus
CAD tools for modeling & description, synthesis, optimization, simulation and verification of design at
various levels- high level, RTL, Gate; as well as for special realizations and structure such as
microprogrammes, PLAs, gate arrays etc. Low power issues in high level synthesis and logic synthesis.
Technological alternatives and technology mapping;
Layout of Integrated Circuits. Use of the layout tool for Analog and Digital Integrated Circuits Circuit
partitioning, placement and routing algorithms. Circuit Compaction; Deep sub-micron issues;
interconnects modeling and synthesis.
Lecture-plan
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Contents

CAD tools for modeling & description, data path & control design
synthesis, optimization, simulation and verification of design at
various levels-high level, RTL
as well as for special realizations and structure such as
microprogrammes, PLAs, gate arrays etc.
synthesis, optimization, simulation and verification of design at Gate
level;
Low power issues in high level synthesis and logic synthesis.
Technological alternatives and technology mapping
Total

Contents

Layout of Integrated Circuits

Integrated Circuits Circuit partitioning
Floor-planning
Placement
Global routing
Detailed routing
Circuit Compaction;
Deep sub-micron issues;
interconnects modeling and synthesis.
Total

Total contact hours- 32 Hours lectures

# of hours
1
2
4
4
2
2
1
1
4
21

# of hours
3
8
0
10
1
1
23

Brief coverage
2
2
2
1
2