Delay and Power Minimization

in VLSI Interconnects with

Spatio-Temporal BusEncoding Scheme
Nalla Manohar Reddy
152114203

Advances in IC Technologies
A journey that started in
1959

First integrated circuit

Fairchild

First microprocessor

Semiconductor 1959

Intel 4004

Pentium 4

1971

Intel Corporation
2002

History of Interconnect Modeling

Gate delay was dominant
Interconnect was modeled as short-circuit

Interconnect capacitance
became comparable to gate
capacitance

Cline = Cl

Interconnect resistance
became comparable to gate
resistance
Rline = Rl
Rz

Cz

l
Rz

Cline = Cl

Cz

Rz

Cz

Crosstalk Between Coupled RLC Interconnects

Significant inductive effects in the upper metal layers

Faster rise times
Lower resistance
Wider lines
Copper interconnect

Capacitive/inductive coupling degrades the signal

integrity
Crosstalk noise increases

Analytical Model for Delay and Energy

Delay Vs Crosstalk Class

Encoding Scheme

Hardware Implementation

Comparison of Coding Schemes

%Energy reduction(SPEC95 Bench marks)

Thank You !!