Daffodil

Course Code: EEE-426

International
University

Department of Electrical and Electronic Engineering

Faculty of Engineering
Lab Quiz, Semester-Spring.2014
Course Title: VLSI Circuits Laboratory

Time : 40 minutes
Name:

Marks: 50
ID:

1. True/False: If true write T and if false write F on the left of the statement.
[81=8]
a) PMOS is pull-down device.
b) In SPICE, input line with first character an asterisk (*) is interpreted as comment line.
c) In SPICE, node numbers can both be positive and negative.
d) In SPICE, device name can be upto 8 characters.
e) In SPICE only DC voltage source can be applied.
f) In SPICE, simulation of NAND gate needs extra parameter than inverter.
g) Dsch2 gives the layout of the design directly.
h) DC analysis in SPICE is performed in order to find inversion voltage.
2. What will be netlist code for the following voltage source as pulsed voltage and piecewise linear
voltage.
[22=4]
a) Pulsed voltage source

b) Piecewise linear voltage source

3. Write the netlist of the following circuits.

[4]

4. If we want to perform a transient analysis from 0ns to 2ns with step of 0.005ns, what line should
be added to the netlist?
[2]

5. Implement the function f =( A+ B ) .C

in CMOS technology. Sketch the layout of your designed

circuit.

6. What is the function that is implemented in the following layout?

[3+5]

[4]

7. Draw a schematic to implement a 6 bit full adder. You can use full adder symbol, hexadisplay
symbol and hexa-keyboard symbol in your schematic. You will show sum and carryout in the
display.
[6]

8. For a 3 I/P NOR gate what will be