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    Leslie Wright
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    This document describes an 8b/10b codec VHDL project that provides asynchronous encoding and decoding for high-speed fiber optic SERDES interfaces. It uses a large lookup table implementation to offer minimal deterministic delay, and was tested on a Xilinx FPGA where it used only logic gates instead of block memory as initially stated.

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    8b10encoding

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    kk

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    This document describes an 8b/10b codec VHDL project that provides asynchronous encoding and decoding for high-speed fiber optic SERDES interfaces. It uses a large lookup table implementation to offer minimal deterministic delay, and was tested on a Xilinx FPGA where it used only logic gates instead of block memory as initially stated.

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    21 views1 page

    KK

    Uploaded by

    Leslie Wright
    This document describes an 8b/10b codec VHDL project that provides asynchronous encoding and decoding for high-speed fiber optic SERDES interfaces. It uses a large lookup table implementation to offer minimal deterministic delay, and was tested on a Xilinx FPGA where it used only logic gates instead of block memory as initially stated.

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    © All Rights Reserved
    Download as RTF, PDF, TXT or read online from Scribd
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    Description

    Usually, 8b/10b codec is required with using a fibre-optic SERDES interface.


    A SERDES converts fast serial optic-stream into less fast 10bit parallel electricsignals.
    Even though less fast electric-signals, that has almost or more 100Mhz speed.
    so the FPGA logic processing 8b/10b must have capable to terminate processing
    encode and decode with minimal delay.
    This project provide you the VHDL code, processing 8b/10b enc/dec
    asynchronously.
    It is implemented by a large lookup-table for better performance.
    a lookup-table implementation can offer you with minimal deterministic inter delay.
    it can be used with clocked signals also, if you want.
    I tested this project with Xilinx XC3S50AN.
    Xilinx tools produced the result using just two block-memory within XC3S50AN.
    one block-memory is used for an encoder. another block-memory is used for a
    decoder each.
    ************************************
    Oh!. I find my bad..
    This project can offer async 8b/10b enc/dec, but not use a block-memory.
    a block-memory is needed to shrink logic-gates.
    I will change the title of this project soon.
    *************************

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