Features:

The two main modules provide a complete VHDL implementation that closely
follows the original IBM article "A DC-Balanced, Partitioned-Block, 8B/10B
Transmission Code" published by A.X. Widmer and P.A. Franaszek and the resulting
US patent #4,486,739. For clarity, the VHDL code references the figures and tables
of the patent document. Please note that the patent has now expired.
Encoder:
+ 8b/10b Encoder (file: 8b10b_enc.vhd)
+ Synchronous clocked inputs (latched on each clock rising edge)
+ 8-bit parallel unencoded data input
+ KI input selects data or control encoding
+ Asynchronous active high reset initializes all logic
+ Encoded data output
+ 10-bit parallel encoded output valid 1 clock later
Decoder:
+ 8b/10b Decoder (file: 8b10b_dec.vhd)
+ Synchronous clocked inputs (latched on each clock rising edge)
+ 10-bit parallel encoded data input
+ Asynchronous active high reset initializes all logic
+ Decoded data, disparity and KO outputs
+ 8-bit parallel unencoded output valid 1 clock later
There are two Testbench files; one that tests the encoder and a second that drives
the decoder with the latched output from the encoder. All 256 data characters, "D",
and all 12 control characters , "K", are sequenced.
- Encoder Testbench (file: enc_8b10b_TB.vhd)
- Combined Testbench (file: endec_8b10b_TB.vhd)

Status
The two source files and the two testbench files are now complete and have been
functionally simulated. The files, and a brief usage document have been uploaded
to CVS